1 /* $NetBSD: sc16is7xxreg.h,v 1.1 2025/10/24 23:16:11 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2025 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DEV_IC_SC16IS7XXREG_H_ 20 #define _DEV_IC_SC16IS7XXREG_H_ 21 22 #define SC16IS7XX_LOW_I2C_ADDR 0x48 23 #define SC16IS7XX_HIGH_I2C_ADDR 0x57 24 25 /* Available generally */ 26 #define SC16IS7XX_REGISTER_RHR 0x00 27 #define SC16IS7XX_REGISTER_THR 0x00 28 #define SC16IS7XX_REGISTER_IER 0x01 29 #define SC16IS7XX_REGISTER_FCR 0x02 30 #define SC16IS7XX_REGISTER_IIR 0x02 31 #define SC16IS7XX_REGISTER_LCR 0x03 32 #define SC16IS7XX_REGISTER_MCR 0x04 33 #define SC16IS7XX_REGISTER_LSR 0x05 34 #define SC16IS7XX_REGISTER_MSR 0x06 35 #define SC16IS7XX_REGISTER_SPR 0x07 36 #define SC16IS7XX_REGISTER_TCR 0x06 /* Accessable when MCR[2] = 1 and 37 * EFR[4] = 1 */ 38 #define SC16IS7XX_REGISTER_TLR 0x07 /* Accessable when MCR[2] = 1 and 39 * EFR[4] = 1 */ 40 #define SC16IS7XX_REGISTER_TXLVL 0x08 41 #define SC16IS7XX_REGISTER_RXLVL 0x09 42 #define SC16IS7XX_REGISTER_IODIR 0x0a /* Only on 43 * SC16IS75[02]/SC16IS76[02] */ 44 #define SC16IS7XX_REGISTER_IOSTATE 0x0b /* Only on 45 * SC16IS75[02]/SC16IS76[02] */ 46 #define SC16IS7XX_REGISTER_IOENA 0x0c /* Only on 47 * SC16IS75[02]/SC16IS76[02] */ 48 #define SC16IS7XX_REGISTER_RESERVED 0x0d 49 #define SC16IS7XX_REGISTER_IOCONTROL 0x0e /* Only on 50 * SC16IS75[02]/SC16IS76[02], 51 * except for the SRESET bit */ 52 #define SC16IS7XX_IOCONTROL_7_4 0x02 53 #define SC16IS7XX_IOCONTROL_3_0 0x04 54 #define SC16IS7XX_IOCONTROL_SRESET 0x08 55 #define SC16IS7XX_REGISTER_EFCR 0x0f 56 57 /* IODIR, IOSTATE, IOENA, and IOCONTROL apply to both channels 58 * on the SCIS16752 and SCIS16762 59 */ 60 61 /* Special register set. Available when LCR[7] = 1 and not 0xBF */ 62 #define SC16IS7XX_REGISTER_DLL 0x00 63 #define SC16IS7XX_REGISTER_DLH 0x01 64 65 /* Enhanced register set. Available when LCR = 0xBF */ 66 #define SC16IS7XX_REGISTER_EFR 0x02 67 #define SC16IS7XX_REGISTER_XON1 0x04 68 #define SC16IS7XX_REGISTER_XON2 0x05 69 #define SC16IS7XX_REGISTER_XOFF1 0x06 70 #define SC16IS7XX_REGISTER_XOFF2 0x07 71 72 #endif 73
Indexes created Fri Oct 31 11:10:07 GMT 2025