1 /* $NetBSD: seeq8005reg.h,v 1.4 2001/04/01 21:15:15 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1995-1998 Mark Brinicombe 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 /* 35 * SEEQ 8005/80C04/80C04A registers 36 * 37 * Note that A0 is only used to distinguish halves of 16-bit registers in 38 * 8-bit mode. 39 */ 40 41 #define SEEQ_COMMAND 0x0 42 #define SEEQ_STATUS 0x0 43 #define SEEQ_CONFIG1 0x2 44 #define SEEQ_CONFIG2 0x4 45 #define SEEQ_RX_END 0x6 46 #define SEEQ_BUFWIN 0x8 47 #define SEEQ_RX_PTR 0xa 48 #define SEEQ_TX_PTR 0xc 49 #define SEEQ_DMA_ADDR 0xe 50 51 #define SEEQ_CMD_DMA_INTEN (1 << 0) /* 8005 */ 52 #define SEEQ_CMD_TEST_INTEN (1 << 0) /* 8004 */ 53 #define SEEQ_CMD_RX_INTEN (1 << 1) 54 #define SEEQ_CMD_TX_INTEN (1 << 2) 55 #define SEEQ_CMD_BW_INTEN (1 << 3) 56 #define SEEQ_CMD_DMA_INTACK (1 << 4) /* 8005 */ 57 #define SEEQ_CMD_TEST_INTACK (1 << 4) /* 8004 */ 58 #define SEEQ_CMD_RX_INTACK (1 << 5) 59 #define SEEQ_CMD_TX_INTACK (1 << 6) 60 #define SEEQ_CMD_BW_INTACK (1 << 7) 61 #define SEEQ_CMD_DMA_ON (1 << 8) /* 8005 */ 62 #define SEEQ_CMD_TEST_INT1 (1 << 8) /* 8004 */ 63 #define SEEQ_CMD_RX_ON (1 << 9) 64 #define SEEQ_CMD_TX_ON (1 << 10) 65 #define SEEQ_CMD_DMA_OFF (1 << 11) /* 8005 */ 66 #define SEEQ_CMD_TEST_INT2 (1 << 11) /* 8004 */ 67 #define SEEQ_CMD_RX_OFF (1 << 12) 68 #define SEEQ_CMD_TX_OFF (1 << 13) 69 #define SEEQ_CMD_FIFO_READ (1 << 14) 70 #define SEEQ_CMD_FIFO_WRITE (1 << 15) 71 72 #define SEEQ_STATUS_DMA_INT (1 << 4) /* 8005 */ 73 #define SEEQ_STATUS_TEST_INT (1 << 4) /* 8004 */ 74 #define SEEQ_STATUS_RX_INT (1 << 5) 75 #define SEEQ_STATUS_TX_INT (1 << 6) 76 #define SEEQ_STATUS_BW_INT (1 << 7) 77 #define SEEQ_STATUS_DMA_ON (1 << 8) /* 8005 */ 78 #define SEEQ_STATUS_TEST_ON (1 << 8) /* 8004 */ 79 #define SEEQ_STATUS_RX_ON (1 << 9) 80 #define SEEQ_STATUS_TX_ON (1 << 10) 81 #define SEEQ_STATUS_TX_NOFAIL (1 << 12) /* 8004 */ 82 #define SEEQ_STATUS_FIFO_FULL (1 << 13) 83 #define SEEQ_STATUS_FIFO_EMPTY (1 << 14) 84 #define SEEQ_STATUS_FIFO_DIR (1 << 15) 85 #define SEEQ_STATUS_FIFO_READ (1 << 15) 86 87 #define SEEQ_BUFCODE_STATION_ADDR0 0x00 88 #define SEEQ_BUFCODE_STATION_ADDR1 0x01 /* 8005 and 80C04A */ 89 #define SEEQ_BUFCODE_STATION_ADDR2 0x02 /* 8005 */ 90 #define SEEQ_BUFCODE_CRCERR_COUNT 0x02 /* 80C04A */ 91 #define SEEQ_BUFCODE_STATION_ADDR3 0x03 /* 8005 */ 92 #define SEEQ_BUFCODE_DRIBBLE_COUNT 0x03 /* 80C04A */ 93 #define SEEQ_BUFCODE_STATION_ADDR4 0x04 /* 8005 */ 94 #define SEEQ_BUFCODE_OVERSIZE_COUNT 0x04 /* 80C04A */ 95 #define SEEQ_BUFCODE_STATION_ADDR5 0x05 /* 8005 */ 96 #define SEEQ_BUFCODE_ADDRESS_PROM 0x06 97 #define SEEQ_BUFCODE_TX_EAP 0x07 98 #define SEEQ_BUFCODE_LOCAL_MEM 0x08 99 #define SEEQ_BUFCODE_INT_VECTOR 0x09 /* 8005 */ 100 #define SEEQ_BUFCODE_LC_DFR_COUNT 0x09 /* 80C04A */ 101 #define SEEQ_BUFCODE_TX_COLLS 0x0b /* 8004 */ 102 #define SEEQ_BUFCODE_CONFIG3 0x0c /* 8004 */ 103 #define SEEQ_BUFCODE_PRODUCTID 0x0d /* 8004 */ 104 #define SEEQ_BUFCODE_TESTENABLE 0x0e /* 8004 */ 105 #define SEEQ_BUFCODE_MULTICAST 0x0f /* 8004 */ 106 107 #define SEEQ_CFG1_DMA_BURST_CONT (0 << 4) /* 8005 */ 108 #define SEEQ_CFG1_DMA_BURST_800 (1 << 4) /* 8005 */ 109 #define SEEQ_CFG1_DMA_BURST_1600 (2 << 4) /* 8005 */ 110 #define SEEQ_CFG1_DMA_BURST_3200 (3 << 4) /* 8005 */ 111 #define SEEQ_CFG1_DMA_BSIZE_1 (0 << 6) /* 8005 */ 112 #define SEEQ_CFG1_DMA_BSIZE_4 (1 << 6) /* 8005 */ 113 #define SEEQ_CFG1_DMA_BSIZE_8 (2 << 6) /* 8005 */ 114 #define SEEQ_CFG1_DMA_BSIZE_16 (3 << 6) /* 8005 */ 115 116 #define SEEQ_CFG1_STATION_ADDR0 (1 << 8) /* 8005 */ 117 #define SEEQ_CFG1_STATION_ADDR1 (1 << 9) /* 8005 */ 118 #define SEEQ_CFG1_STATION_ADDR2 (1 << 10) /* 8005 */ 119 #define SEEQ_CFG1_STATION_ADDR3 (1 << 11) /* 8005 */ 120 #define SEEQ_CFG1_STATION_ADDR4 (1 << 12) /* 8005 */ 121 #define SEEQ_CFG1_STATION_ADDR5 (1 << 13) /* 8005 */ 122 #define SEEQ_CFG1_SPECIFIC ((0 << 15) | (0 << 14)) 123 #define SEEQ_CFG1_BROADCAST ((0 << 15) | (1 << 14)) 124 #define SEEQ_CFG1_MULTICAST ((1 << 15) | (0 << 14)) 125 #define SEEQ_CFG1_PROMISCUOUS ((1 << 15) | (1 << 14)) 126 127 #define SEEQ_CFG2_BYTESWAP (1 << 0) 128 #define SEEQ_CFG2_REA_AUTOUPDATE (1 << 1) /* 8004 only */ 129 #define SEEQ_CFG2_RX_TX_DISABLE (1 << 2) /* 8004 only */ 130 #define SEEQ_CFG2_CRC_ERR_ENABLE (1 << 3) 131 #define SEEQ_CFG2_DRIB_ERR_ENABLE (1 << 4) 132 #define SEEQ_CFG2_PASS_SHORT (1 << 5) /* 8005 */ 133 #define SEEQ_CFG2_PASS_LONGSHORT (1 << 5) /* 8004 */ 134 #define SEEQ_CFG2_SLOT_SELECT (1 << 6) /* 8005 only */ 135 #define SEEQ_CFG2_PREAM_SELECT (1 << 7) 136 #define SEEQ_CFG2_ADDR_LENGTH (1 << 8) /* 8005 only */ 137 #define SEEQ_CFG2_RX_CRC (1 << 9) 138 #define SEEQ_CFG2_NO_TX_CRC (1 << 10) 139 #define SEEQ_CFG2_LOOPBACK (1 << 11) 140 #define SEEQ_CFG2_OUTPUT (1 << 12) 141 #define SEEQ_CFG2_RESET (1 << 15) 142 143 #define SEEQ_CFG3_AUTOPAD (1 << 0) /* 80C04 */ 144 #define SEEQ_CFG3_SAHASHENABLE (1 << 1) /* 80C04A */ 145 #define SEEQ_CFG3_SQEENABLE (1 << 2) /* 80C04 */ 146 #define SEEQ_CFG3_SLEEP (1 << 3) /* 80C04 */ 147 #define SEEQ_CFG3_READYADVD (1 << 4) /* 80C04 only */ 148 #define SEEQ_CFG3_SECONDADDRENABLE (1 << 5) /* 80C04A */ 149 #define SEEQ_CFG3_GROUPADDR (1 << 6) /* 80C04 */ 150 #define SEEQ_CFG3_NPPBYTE (1 << 7) /* 80C04 */ 151 152 #define SEEQ_PRODUCTID_MASK 0xf0 153 #define SEEQ_PRODUCTID_8004 0xa0 154 #define SEEQ_PRODUCTID_REV_MASK 0x0f 155 #define SEEQ_PRODUCTID_REV_80C04 0x0f 156 #define SEEQ_PRODUCTID_REV_80C04A 0x0e 157 158 #define SEEQ_PKTCMD_TX (1 << 7) 159 #define SEEQ_PKTCMD_RX (0 << 7) 160 #define SEEQ_PKTCMD_CHAIN_CONT (1 << 6) 161 #define SEEQ_PKTCMD_DATA_FOLLOWS (1 << 5) 162 163 #define SEEQ_PKTSTAT_DONE (1 << 7) 164 165 #define SEEQ_TXSTAT_BABBLE (1 << 0) 166 #define SEEQ_TXSTAT_COLLISION (1 << 1) 167 #define SEEQ_TXSTAT_COLLISION16 (1 << 2) 168 #define SEEQ_TXSTAT_COLLISIONS_SHIFT 3 /* SEEQ 8004 */ 169 #define SEEQ_TXSTAT_COLLISION_MASK 0x0f /* SEEQ 8004 */ 170 #define SEEQ_TXSTAT_CARRIER_DROPOUT (1 << 3) /* SEEQ 80C04A */ 171 #define SEEQ_TXSTAT_OK_BUT_DEFERRED (1 << 4) /* SEEQ 80C04A */ 172 #define SEEQ_TXSTAT_OK_BUT_COLLISIONS (1 << 5) /* SEEQ 80C04A */ 173 #define SEEQ_TXSTAT_OK_BUT_COLLISION (1 << 6) /* SEEQ 80C04A */ 174 175 #define SEEQ_TXCMD_BABBLE_INT (1 << 0) 176 #define SEEQ_TXCMD_COLLISION_INT (1 << 1) 177 #define SEEQ_TXCMD_COLLISION16_INT (1 << 2) 178 #define SEEQ_TXCMD_XMIT_SUCCESS_INT (1 << 3) 179 #define SEEQ_TXCMD_SQE_TEST_INT (1 << 4) /* SEEQ 8004 */ 180 181 #define SEEQ_RXSTAT_OVERSIZE (1 << 0) 182 #define SEEQ_RXSTAT_CRC_ERROR (1 << 1) 183 #define SEEQ_RXSTAT_DRIBBLE_ERROR (1 << 2) 184 #define SEEQ_RXSTAT_SHORT_FRAME (1 << 3) 185 #define SEEQ_RXSTAT_ERROR_MASK 0x0f 186 187 #define SEEQ_MAX_BUFFER_SIZE 0x10000 188
Indexes created Sat Sep 20 22:09:52 GMT 2025