sm502reg.h revision 1.5
1 /* $NetBSD: sm502reg.h,v 1.5 2011/12/07 08:49:29 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Silicon Motion SM502 / Voyager GX register definitions */ 29 30 #ifndef SM502REG_H 31 #define SM502REG_H 32 33 /* System Control Registers */ 34 #define SM502_SYSTEM_CTRL 0x00000000 35 #define SM502_SYSCTL_PANEL_3STATE 0x00000001 36 #define SM502_SYSCTL_MEM_3STATE 0x00000002 37 #define SM502_SYSCTL_CRT_3STATE 0x00000004 38 #define SM502_SYSCTL_BURST_32 0x00000000 39 #define SM502_SYSCTL_BURST_64 0x00000010 40 #define SM502_SYSCTL_BURST_128 0x00000020 41 #define SM502_SYSCTL_BURST_256 0x00000030 42 #define SM502_SYSCTL_PCI_CLOCK_RUN_E 0x00000040 43 #define SM502_SYSCTL_PCI_RETRY_E 0x00000080 44 #define SM502_SYSCTL_PCI_LOCK 0x00000800 45 /* stop drawing engine */ 46 #define SM502_SYSCTL_ENGINE_ABORT 0x00003000 47 #define SM502_SYSCTL_BURST_READ_E 0x00008000 48 #define SM502_SYSCTL_ZV_VSYNC_DET 0x00010000 49 #define SM502_SYSCTL_CRT_FLIP_PENDING 0x00020000 50 #define SM502_SYSCTL_ENGINE_BUSY 0x00080000 51 #define SM502_SYSCTL_FIFO_EMPTY 0x00100000 52 #define SM502_SYSCTL_VIDEO_FLIP_PENDING 0x00400000 53 #define SM502_SYSCTL_PANEL_FLIP_PENDING 0x00800000 54 #define SM502_SYSCTL_PCI_LT_E 0x01000000 55 #define SM502_SYSCTL_PCI_BM_E 0x02000000 56 #define SM502_SYSCTL_CSC_BUSY 0x10000000 57 #define SM502_SYSCTL_PCI_BURST_E 0x20000000 58 #define SM502_SYSCTL_DISABLE_HSYNC 0x40000000 59 #define SM502_SYSCTL_DISABLE_VSYNC 0x80000000 60 61 #define SM502_MISC_CONTROL 0x00000004 62 #define SM502_DAC_POWER_DOWN 0x00001000 63 /* each bit: 0 - GPIO, 1 - other stuff */ 64 #define SM502_GPIO0_CONTROL 0x00000008 65 #define SM502_GPIO1_CONTROL 0x0000000c 66 #define SM502_DRAM_CONTROL 0x00000010 67 #define SM502_ARB_CONTROL 0x00000014 68 #define SM502_COMMANDLIST_STATUS 0x00000024 69 #define SM502_INTR_STATUS_R 0x00000028 /* on read */ 70 #define SM502_INTR_CLEAR_R 0x00000028 /* on write */ 71 #define SM502_RINTR_ZV1 0x00000040 /* zoomed video 1 */ 72 #define SM502_RINTR_UP 0x00000020 /* USB slave plug */ 73 #define SM502_RINTR_ZV0 0x00000010 /* zoomed video 0 */ 74 #define SM502_RINTR_CV 0x00000008 /* CRT vsync */ 75 #define SM502_RINTR_US 0x00000004 /* USB slave */ 76 #define SM502_RINTR_PV 0x00000002 /* panel vsync */ 77 #define SM502_RINTR_CI 0x00000001 /* command interpreter */ 78 79 #define SM502_INTR_STATUS 0x0000002c 80 #define SM502_INTR_MASK 0x00000030 81 #define SM502_INTR_UP 0x80000000 /* USB slave plug */ 82 #define SM502_INTR_GPIO54 0x40000000 83 #define SM502_INTR_GPIO53 0x20000000 84 #define SM502_INTR_GPIO52 0x10000000 85 #define SM502_INTR_GPIO51 0x08000000 86 #define SM502_INTR_GPIO50 0x04000000 87 #define SM502_INTR_GPIO49 0x02000000 88 #define SM502_INTR_GPIO48 0x01000000 89 #define SM502_INTR_I2C 0x00800000 90 #define SM502_INTR_PWM 0x00400000 91 #define SM502_INTR_RES 0x00200000 /* reserved */ 92 #define SM502_INTR_DMA 0x00100000 93 #define SM502_INTR_PCI 0x00080000 94 #define SM502_INTR_I2S 0x00040000 95 #define SM502_INTR_AC97 0x00020000 96 #define SM502_INTR_US 0x00010000 97 #define SM502_INTR_RES2 0x0000c000 /* reserved */ 98 #define SM502_INTR_UART1 0x00002000 99 #define SM502_INTR_UART0 0x00001000 100 #define SM502_INTR_CV 0x00000800 /* CRT vsync */ 101 #define SM502_INTR_MC 0x00000400 /* microcontroller */ 102 #define SM502_INTR_SSP1 0x00000200 103 #define SM502_INTR_SSP0 0x00000100 104 #define SM502_INTR_RES3 0x00000080 /* reserved */ 105 #define SM502_INTR_UH 0x00000040 /* USB host */ 106 #define SM502_INTR_RES4 0x00000020 /* reserved */ 107 #define SM502_INTR_ZV1 0x00000010 /* zoomed video 1 */ 108 #define SM502_INTR_2D 0x00000008 /* 2D engine */ 109 #define SM502_INTR_ZV0 0x00000004 /* zoomed video 0 */ 110 #define SM502_INTR_PV 0x00000002 /* panel vsync */ 111 #define SM502_INTR_CI 0x00000001 /* command interpreter */ 112 113 #define SM502_DEBUG_CONTROL 0x00000034 114 115 #define SM502_CURRENT_GATE 0x00000038 116 #define SM502_GATE_AUDIO_ENABLE 0x00040000 117 #define SM502_GATE_8051_ENABLE 0x00020000 118 #define SM502_GATE_USB_SLAVE_ENABLE 0x00001000 119 #define SM502_GATE_USB_HOST_ENABLE 0x00000800 120 #define SM502_GATE_SSP_ENABLE 0x00000400 121 #define SM502_GATE_UART1_ENABLE 0x00000100 122 #define SM502_GATE_UART0_ENABLE 0x00000080 123 #define SM502_GATE_GPIO_ENABLE 0x00000040 124 #define SM502_GATE_ZV_ENABLE 0x00000020 125 #define SM502_GATE_CSC_ENABLE 0x00000010 126 #define SM502_GATE_2D_ENGINE_ENABLE 0x00000008 127 #define SM502_GATE_DISPLAY_ENABLE 0x00000004 128 #define SM502_GATE_MEMORY_ENABLE 0x00000002 129 #define SM502_GATE_HOST_ENABLE 0x00000001 130 #define SM502_CURRENT_CLOCK 0x0000003c 131 #define SM502_POWER_MODE0_GATE 0x00000040 132 #define SM502_POWER_MODE0_CLOCK 0x00000044 133 #define SM502_POWER_MODE1_GATE 0x00000048 134 #define SM502_POWER_MODE1_CLOCK 0x0000004c 135 #define SM502_SLEEP_MODE_GATE 0x00000050 136 #define SM502_POWER_MODE_CONTROL 0x00000054 137 138 /* GPIO */ 139 #define SM502_GPIO_DATA0 0x00010000 140 #define SM502_GPIO_DATA1 0x00010004 141 #define SM502_GPIO_DIR0 0x00010008 /* 1 is output */ 142 #define SM502_GPIO_DIR1 0x0001000c 143 #define SM502_GPIO_INTR_SETUP 0x00010010 144 #define SM502_GPIO_INTR_STATUS 0x00010014 /* read */ 145 #define SM502_GPIO_INTR_CLEAR 0x00010014 /* write */ 146 147 /* PWM - Pulse Width Modulation */ 148 #define SM502_PWM0 0x00010020 149 #define SM502_PWM1 0x00010024 150 #define SM502_PWM2 0x00010028 151 #define SM502_PWM_ENABLE 0x00000001 152 #define SM502_PWM_ENABLE_INTR 0x00000004 153 #define SM502_PWM_INTR_PENDING 0x00000008 /* write 1 to clear */ 154 /* 96MHz divided by 1 << n */ 155 #define SM502_PWM_CLOCK_DIV_MASK 0x000000f0 156 #define SM502_PWM_CLOCK_DIV_SHIFT 4 157 /* output remains low for n+1 cycles */ 158 #define SM502_PWM_CLOCK_LOW_MASK 0x000fff00 159 #define SM502_PWM_CLOCK_LOW_SHIFT 8 160 /* output remains high for n+1 cycles */ 161 #define SM502_PWM_CLOCK_HIGH_MASK 0xfff00000 162 #define SM502_PWM_CLOCK_HIGH_SHIFT 20 163 164 /* Video Controller Registers */ 165 #define SM502_PANEL_DISP_CTRL 0x080000 166 #define SM502_PDC_8BIT 0x00000000 167 #define SM502_PDC_16BIT 0x00000001 168 #define SM502_PDC_32BIT 0x00000002 169 #define SM502_PDC_DEPTH_MASK 0x00000003 170 #define SM502_PDC_PANEL_ENABLE 0x00000004 171 #define SM502_PDC_GAMMA_ENABLE 0x00000008 172 #define SM502_PDC_HPAN_AUTO 0x00000010 173 #define SM502_PDC_HPAN_DIR_LEFT 0x00000000 174 #define SM502_PDC_HPAN_DIR_RIGHT 0x00000020 175 #define SM502_PDC_VPAN_AUTO 0x00000040 176 #define SM502_PDC_VPAN_DIR_UP 0x00000080 177 #define SM502_PDC_VPAN_DIR_DOWN 0x00000000 178 #define SM502_PDC_TIMING_ENABLE 0x00000100 179 #define SM502_PDC_COLORKEY_ENABLE 0x00000200 180 #define SM502_PDC_CAPTURE_ZV_0 0x00000400 181 #define SM502_PDC_HSYNC_PHASE_LOW 0x00001000 182 #define SM502_PDC_HSYNC_PHASE_HIGH 0x00000000 183 #define SM502_PDC_VSYNC_PHASE_LOW 0x00002000 184 #define SM502_PDC_VSYNC_PHASE_HIGH 0x00000000 185 #define SM502_PDC_CLOCK_ACT_LOW 0x00004000 186 #define SM502_PDC_CLOCK_ACTIVE_HIGH 0x00000000 187 #define SM502_PDC_8BIT_TV_ENABLE 0x00008000 188 #define SM502_PDC_FIFO_HWATER_1 0x00000000 189 #define SM502_PDC_FIFO_HWATER_3 0x00010000 190 #define SM502_PDC_FIFO_HWATER_7 0x00020000 191 #define SM502_PDC_FIFO_HWATER_11 0x00030000 192 #define SM502_PDC_FIFO_HWATE_MASK 0x00030000 193 #define SM502_PDC_TYPE_TFT 0x00000000 194 #define SM502_PDC_TYPE_8BIT_STN 0x00040000 195 #define SM502_PDC_TYPE_12BIT_STN 0x00080000 196 #define SM502_PDC_TYPE_MASK 0x000c0000 197 #define SM502_PDC_DITHERING_ENABLE 0x00100000 198 #define SM502_PDC_TFT_RGB888 0x00000000 199 #define SM502_PDC_TFT_RGB333 0x00200000 200 #define SM502_PDC_TFT_RGB444 0x00400000 201 #define SM502_PDC_TFT_RGB_MASK 0x00600000 202 #define SM502_PDC_DITHER_8_GREY 0x00800000 203 #define SM502_PDC_FPVDDEN_HIGH 0x01000000 204 #define SM502_PDC_FPVDDEN_LOW 0x00000000 205 #define SM502_PDC_PANEL_SIGNALS_ENABLE 0x02000000 206 #define SM502_PDC_VBIASEN_HIGH 0x04000000 207 #define SM502_PDC_VBIASEN_LOW 0x00000000 208 #define SM502_PDC_GPEN_ENABLE 0x08000000 209 210 #define SM502_PANEL_PAN_CTRL 0x080004 211 #define SM502_PANEL_COLOR_KEY 0x080008 212 #define SM502_PANEL_FB_ADDRESS 0x08000C 213 #define SM502_FBA_MASK 0x03fffff0 /* 128bit align */ 214 #define SM502_FBA_CS1 0x04000000 215 #define SM502_FBA_CS0 0x00000000 216 #define SM502_FBA_SYSTEM_MEM 0x08000000 217 #define SM502_FBA_LOCAL_MEM 0x00000000 218 #define SM502_FBA_FLIP_PENDING 0x80000000 219 220 #define SM502_PANEL_FB_OFFSET 0x080010 221 #define SM502_FBO_FB_STRIDE_MASK 0x00003ff0 /* 128bit align */ 222 #define SM502_FBA_WIN_STRIDE_MASK 0x3ff00000 /* 128bit align */ 223 224 #define SM502_PANEL_FB_WIDTH 0x080014 225 #define SM502_FBW_WIN_X_MASK 0x00003fff 226 #define SM502_FBW_WIN_WIDTH_MASK 0x3fff0000 227 228 #define SM502_PANEL_FB_HEIGHT 0x080018 229 #define SM502_FBH_WIN_Y_MASK 0x00003fff 230 #define SM502_FBH_WIN_HEIGHT_MASK 0x3fff0000 231 #define SM502_PANEL_TL 0x08001C 232 #define SM502_TL_LEFT_MASK 0x000007ff 233 #define SM502_TL_TOP_MASK 0x07ff0000 234 235 #define SM502_PANEL_BR 0x080020 236 #define SM502_BR_RIGHT_MASK 0x000007ff 237 #define SM502_BR_BOTTOM_MASK 0x07ff0000 238 239 #define SM502_PANEL_HTOTAL 0x080024 240 #define SM502_HT_HDISPE_MASK 0x00000fff 241 #define SM502_HT_HTOTAL_MASK 0x0fff0000 242 #define SM502_PANEL_HSYNC 0x080028 243 #define SM502_PANEL_VTOTAL 0x08002C 244 #define SM502_VT_VDISPE_MASK 0x00000fff 245 #define SM502_VT_VTOTAL_MASK 0x0fff0000 246 #define SM502_PANEL_VSYNC 0x080030 247 #define SM502_PANEL_CRSR_ADDR 0x0800f0 248 #define SM502_CRSR_ENABLE 0x80000000 249 #define SM502_CRSR_SYSTEM_MEM 0x08000000 250 #define SM502_CRSR_SYSMEM_CS1 0x04000000 251 #define SM502_CRSR_ADDRESS_M 0x03fffff0 252 #define SM502_PANEL_CRSR_XY 0x0800f4 253 #define SM502_CRSR_X_MASK 0x00000fff 254 #define SM502_CRSR_Y_MASK 0x0fff0000 255 #define SM502_PANEL_CRSR_COL12 0x0800f8 256 #define SM502_CRSR_COLOR_1_MASK 0x0000ffff 257 #define SM502_CRSR_COLOR_2_MASK 0xffff0000 258 #define SM502_PANEL_CRSR_COL3 0x0800fc 259 #define SM502_CRSR_COLOR_3_MASK 0x0000ffff 260 261 262 #define SM502_PALETTE_PANEL 0x080400 263 #define SM502_PALETTE_VIDEO 0x080800 264 #define SM502_PALETTE_CRT 0x080c00 265 266 /* drawing engine */ 267 #define SM502_SRC 0x100000 268 #define SM502_SRC_WRAP_ENABLE 0x80000000 269 #define SM502_SRC_X_MASK 0x3fff0000 270 #define SM502_SRC_Y_MASK 0x0000ffff 271 272 #define SM502_DST 0x100004 273 #define SM502_DST_WRAP_ENABLE 0x80000000 274 #define SM502_DST_X_MASK 0x3fff0000 275 #define SM502_DST_Y_MASK 0x0000ffff 276 277 #define SM502_DIMENSION 0x100008 278 #define SM502_DIM_X_MASK 0x3fff0000 279 #define SM502_DIM_Y_MASK 0x0000ffff 280 281 #define SM502_CONTROL 0x10000c 282 #define ROP_COPY 0x0c 283 #define ROP_INVERT 0x03 284 #define SM502_CTRL_ROP_MASK 0x000000ff 285 #define SM502_CTRL_TRANSP_EN 0x00000100 286 #define SM502_CTRL_TRANSP_DST 0x00000200 287 #define SM502_CTRL_TRANSP_SRC 0x00000000 288 #define SM502_CTRL_TRANSP_MATCH 0x00000400 289 #define SM502_CTRL_OPAQUE_MATCH 0x00000000 290 #define SM502_CTRL_REPEAT_ROT 0x00000800 291 #define SM502_CTRL_MONO_PACK_MASK 0x00003000 292 #define SM502_CTRL_MONO_PACK_8BIT 0x00001000 293 #define SM502_CTRL_MONO_PACK_16BIT 0x00002000 294 #define SM502_CTRL_MONO_PACK_32BIT 0x00003000 295 #define SM502_CTRL_ROP2_SRC_PAT 0x00004000 /* otherwise src is bmp */ 296 #define SM502_CTRL_USE_ROP2 0x00008000 /* X-style ROPs vs. Win */ 297 #define SM502_CTRL_COMMAND_MASK 0x001f0000 298 #define SM502_CTRL_CMD_BITBLT 0x00000000 299 #define SM502_CTRL_CMD_RECTFILL 0x00010000 300 #define SM502_CTRL_CMD_DETILE 0x00020000 301 #define SM502_CTRL_CMD_TRAPFILL 0x00030000 302 #define SM502_CTRL_CMD_ALPHA 0x00040000 303 #define SM502_CTRL_CMD_RLESTRIP 0x00050000 304 #define SM502_CTRL_CMD_SHRTSTRK 0x00060000 305 #define SM502_CTRL_CMD_LINE 0x00070000 306 #define SM502_CTRL_CMD_HOSTWRT 0x00080000 307 #define SM502_CTRL_CMD_HOSTREAD 0x00090000 308 #define SM502_CTRL_CMD_WRT_BT 0x000a0000 309 #define SM502_CTRL_CMD_ROTATE 0x000b0000 310 #define SM502_CTRL_CMD_FONT 0x000c0000 311 #define SM502_CTRL_CMD_TEXLOAD 0x000f0000 312 #define SM502_CTRL_DRAWLAST 0x00200000 /* last pixel in line */ 313 #define SM502_CTRL_HOSTBLT_MONO 0x00400000 /* colour otherwise */ 314 #define SM502_CTRL_YSTRETCH_E 0x00800000 315 #define SM502_CTRL_Y_STEP_NEG 0x01000000 /* line, otherwise pos */ 316 #define SM502_CTRL_X_STEP_NEG 0x02000000 /* line, otherwise pos */ 317 #define SM502_CTRL_LINE_AX_Y 0x04000000 /* otherwise X */ 318 #define SM502_CTRL_R_TO_L 0x08000000 /* otherwise L to R */ 319 /* run command when writing SM502_DIMENSION */ 320 #define SM502_CTRL_QUICKSTART_E 0x10000000 321 #define SM502_CTRL_UPD_DESTX 0x20000000 322 #define SM502_CTRL_PAT_COLOR 0x40000000 /* otherwise mono */ 323 #define SM502_CTRL_ENGINE_START 0x80000000 324 325 #define SM502_PITCH 0x100010 326 #define SM502_PITCH_SRC_MASK 0x00003fff 327 #define SM502_PITCH_DST_MASK 0x3fff0000 328 329 #define SM502_FOREGROUND 0x100014 330 #define SM502_BACKGROUND 0x100018 331 #define SM502_STRETCH 0x10001c 332 #define SM502_STRETCH_HEIGHT_MASK 0x00000fff /* source */ 333 #define SM502_STRETCH_ADDR_LINEAR 0x000f0000 /* XY otherwise */ 334 #define SM502_STRETCH_PIXEL_FORMAT_MASK 0x00300000 335 #define SM502_STRETCH_8BIT 0x00000000 336 #define SM502_STRETCH_16BIT 0x00100000 337 #define SM502_STRETCH_32BIT 0x00200000 338 #define SM502_STRETCH_PAT_X_ORIGIN_MASK 0x03800000 339 #define SM502_STRETCH_PAT_Y_ORIGIN_MASK 0x38000000 340 #define SM502_STRETCH_PAT_XY_ENABLE 0x40000000 341 342 #define SM502_COLOR_COMPARE 0x100020 343 #define SM502_COLOR_COMP_MASK 0x100024 344 #define SM502_PLANEMASK 0x100028 345 #define SM502_CLIP_TOP_LEFT 0x10002c 346 #define SM501_CLIP_TOP_MASK 0xffff0000 347 #define SM501_CLIP_LEFT_MASK 0x00000fff 348 #define SM501_CLIP_BLOCK_INSIDE 0x00001000 /* otherwise block outside */ 349 #define SM501_CLIP_ENABLE 0x00002000 350 351 #define SM502_CLIP_BOTTOM_RIGHT 0x100030 352 #define SM501_CLIP_BOTTOM_MASK 0xffff0000 353 #define SM501_CLIP_RIGHT_MASK 0x00001fff 354 355 #define SM502_MONO_PATTERN_0 0x100034 356 #define SM502_MONO_PATTERN_1 0x100038 357 #define SM502_WINDOW_WIDTH 0x10003c 358 #define SM502_WIN_SRC_MASK 0x00001fff 359 #define SM502_WIN_DST_MASK 0x1fff0000 360 361 #define SM502_SRC_BASE 0x100040 362 #define SM502_SRC_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 363 #define SM502_SRC_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 364 #define SM502_SRC_BASE_SYSMEM 0x08000000 /* local otherw. */ 365 366 #define SM502_DST_BASE 0x100044 367 #define SM502_DST_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 368 #define SM502_DST_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 369 #define SM502_DST_BASE_SYSMEM 0x08000000 /* local otherw. */ 370 371 #define SM502_ALPHA 0x100048 372 #define SM502_WRAP 0x10004c 373 #define SM502_WRAP_HEIGHT_MASK 0x0000ffff 374 #define SM502_WRAP_WIDTH_MASK 0xffff0000 375 376 #define SM502_STATUS 0x100050 377 #define SM502_CMD_DONE 0x00000001 378 #define SM502_CSC_DONE 0x00000002 379 380 #define SM502_DATAPORT 0x110000 381 382 /* AC97 Link */ 383 #define SM502_AC97_TX_TAG 0x0A0100 384 #define SM502_AC97_FRAME_VALID 0x8000 385 #define SM502_AC97_S1_VALID 0x4000 386 #define SM502_AC97_S2_VALID 0x2000 387 #define SM502_AC97_S3_VALID 0x1000 388 #define SM502_AC97_S4_VALID 0x0800 389 #define SM502_AC97_TX_ADDR 0x0A0104 390 #define SM502_AC97_READ 0x00100000 /* write otherwise */ 391 #define SM502_AC97_ADDR_MASK 0x000fe000 392 #define SM502_AC97_TX_DATA 0x0A0108 393 #define SM502_AC97_DATA_MASK 0x000ffff0 394 #define SM502_AC97_TX_LEFT 0x0A010C 395 #define SM502_AC97_TX_RIGHT 0x0A0110 396 #define SM502_AC97_RX_TAG 0x0A0140 397 #define SM502_AC97_RX_ADDR 0x0A0144 398 #define SM502_AC97_RX_DATA 0x0A0148 399 #define SM502_AC97_RX_LEFT 0x0A014C 400 #define SM502_AC97_RX_RIGHT 0x0A0150 401 #define SM502_AC97_CONTROL 0x0A0180 402 #define SM502_AC97_DROP_COUNT 0x0000fc00 403 #define SM502_AC97_STOP_SYNC 0x00000200 404 #define SM502_AC97_BCLK_RUNNING 0x00000100 405 #define SM502_AC97_WAKEUP_REQ 0x00000080 406 #define SM502_AC97_STATUS_MASK 0x00000030 407 #define SM502_AC97_STATUS_OFF 0x00000000 408 #define SM502_AC97_STATUS_RESET 0x00000010 409 #define SM502_AC97_STATUS_WAIT 0x00000020 410 #define SM502_AC97_STATUS_ON 0x00000030 411 #define SM502_AC97_WI_ENABLE 0x00000008 /* wakeup interrupt */ 412 #define SM502_AC97_WARM_RESET 0x00000004 /* 1uS at least */ 413 #define SM502_AC97_COLD_RESET 0x00000002 /* 1uS at least */ 414 #define SM502_AC97_ENABLE 0x00000001 415 416 #define SM502_AUDIO_GPIO_MASK 0x1f000000 /* pins used */ 417 418 /* 8051 Microcontroller */ 419 #define SM502_uC_RESET 0x000b0000 420 #define SM502_uC_ENABLE 0x00000001 /* reset otherwise */ 421 #define SM502_uC_MODE_SELECT 0x000b0004 422 #define SM502_uC_CLOCK_MASK 0x00000003 423 #define SM502_uC_CLOCK_DIV2 0x00000000 424 #define SM502_uC_CLOCK_DIV3 0x00000001 425 #define SM502_uC_CLOCK_DIV4 0x00000002 426 #define SM502_uC_CLOCK_DIV5 0x00000003 427 #define SM502_uC_CODEC_I2S 0x00000004 /* AC97 otherwise */ 428 #define SM502_uC_AUDIO_TEST 0x00000008 /* test mode */ 429 #define SM502_uC_IO_8BIT 0x00000010 /* 12 bit otherwise */ 430 #define SM502_uC_SRAM_DISABLE 0x00000020 431 #define SM502_uC_USB_WAIT_MASK 0x000000c0 432 #define SM502_uC_USB_NO_WAIT 0x00000000 433 #define SM502_uC_USB_1_WAIT 0x00000040 434 #define SM502_uC_USB_2_WAIT 0x00000080 435 #define SM502_uC_8051_INTR 0x000b0008 436 #define SM502_uC_CPU_INTR 0x000b000c 437 438 #define SM502_uC_SRAM_PROG 0x00dc0000 /* only readable in RESET */ 439 #define SM502_uC_SRAM_DATA 0x00dc3000 440 441 #endif /* SM502REG_H */ 442
Indexes created Mon Sep 29 21:09:56 GMT 2025