1 /* $NetBSD: sm502reg.h,v 1.7 2013/03/13 21:31:01 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Silicon Motion SM502 / Voyager GX register definitions */ 29 30 #ifndef SM502REG_H 31 #define SM502REG_H 32 33 /* System Control Registers */ 34 #define SM502_SYSTEM_CTRL 0x00000000 35 #define SM502_SYSCTL_PANEL_3STATE 0x00000001 36 #define SM502_SYSCTL_MEM_3STATE 0x00000002 37 #define SM502_SYSCTL_CRT_3STATE 0x00000004 38 #define SM502_SYSCTL_BURST_32 0x00000000 39 #define SM502_SYSCTL_BURST_64 0x00000010 40 #define SM502_SYSCTL_BURST_128 0x00000020 41 #define SM502_SYSCTL_BURST_256 0x00000030 42 #define SM502_SYSCTL_PCI_CLOCK_RUN_E 0x00000040 43 #define SM502_SYSCTL_PCI_RETRY_E 0x00000080 44 #define SM502_SYSCTL_PCI_LOCK 0x00000800 45 /* stop drawing engine */ 46 #define SM502_SYSCTL_ENGINE_ABORT 0x00003000 47 #define SM502_SYSCTL_BURST_READ_E 0x00008000 48 #define SM502_SYSCTL_ZV_VSYNC_DET 0x00010000 49 #define SM502_SYSCTL_CRT_FLIP_PENDING 0x00020000 50 #define SM502_SYSCTL_ENGINE_BUSY 0x00080000 51 #define SM502_SYSCTL_FIFO_EMPTY 0x00100000 52 #define SM502_SYSCTL_VIDEO_FLIP_PENDING 0x00400000 53 #define SM502_SYSCTL_PANEL_FLIP_PENDING 0x00800000 54 #define SM502_SYSCTL_PCI_LT_E 0x01000000 55 #define SM502_SYSCTL_PCI_BM_E 0x02000000 56 #define SM502_SYSCTL_CSC_BUSY 0x10000000 57 #define SM502_SYSCTL_PCI_BURST_E 0x20000000 58 #define SM502_SYSCTL_DISABLE_HSYNC 0x40000000 59 #define SM502_SYSCTL_DISABLE_VSYNC 0x80000000 60 61 #define SM502_MISC_CONTROL 0x00000004 62 #define SM502_DAC_POWER_DOWN 0x00001000 63 /* each bit: 0 - GPIO, 1 - other stuff */ 64 #define SM502_GPIO0_CONTROL 0x00000008 65 #define SM502_GPIO1_CONTROL 0x0000000c 66 #define SM502_DRAM_CONTROL 0x00000010 67 #define SM502_MEM_4M 0x00000000 68 #define SM502_MEM_8M 0x00002000 69 #define SM502_MEM_16M 0x00004000 70 #define SM502_MEM_32M 0x00006000 71 #define SM502_MEM_64M 0x00008000 72 #define SM502_MEM_2M 0x0000a000 73 74 #define SM502_ARB_CONTROL 0x00000014 75 #define SM502_COMMANDLIST_STATUS 0x00000024 76 #define SM502_INTR_STATUS_R 0x00000028 /* on read */ 77 #define SM502_INTR_CLEAR_R 0x00000028 /* on write */ 78 #define SM502_RINTR_ZV1 0x00000040 /* zoomed video 1 */ 79 #define SM502_RINTR_UP 0x00000020 /* USB slave plug */ 80 #define SM502_RINTR_ZV0 0x00000010 /* zoomed video 0 */ 81 #define SM502_RINTR_CV 0x00000008 /* CRT vsync */ 82 #define SM502_RINTR_US 0x00000004 /* USB slave */ 83 #define SM502_RINTR_PV 0x00000002 /* panel vsync */ 84 #define SM502_RINTR_CI 0x00000001 /* command interpreter */ 85 86 #define SM502_INTR_STATUS 0x0000002c 87 #define SM502_INTR_MASK 0x00000030 88 #define SM502_INTR_UP 0x80000000 /* USB slave plug */ 89 #define SM502_INTR_GPIO54 0x40000000 90 #define SM502_INTR_GPIO53 0x20000000 91 #define SM502_INTR_GPIO52 0x10000000 92 #define SM502_INTR_GPIO51 0x08000000 93 #define SM502_INTR_GPIO50 0x04000000 94 #define SM502_INTR_GPIO49 0x02000000 95 #define SM502_INTR_GPIO48 0x01000000 96 #define SM502_INTR_I2C 0x00800000 97 #define SM502_INTR_PWM 0x00400000 98 #define SM502_INTR_RES 0x00200000 /* reserved */ 99 #define SM502_INTR_DMA 0x00100000 100 #define SM502_INTR_PCI 0x00080000 101 #define SM502_INTR_I2S 0x00040000 102 #define SM502_INTR_AC97 0x00020000 103 #define SM502_INTR_US 0x00010000 104 #define SM502_INTR_RES2 0x0000c000 /* reserved */ 105 #define SM502_INTR_UART1 0x00002000 106 #define SM502_INTR_UART0 0x00001000 107 #define SM502_INTR_CV 0x00000800 /* CRT vsync */ 108 #define SM502_INTR_MC 0x00000400 /* microcontroller */ 109 #define SM502_INTR_SSP1 0x00000200 110 #define SM502_INTR_SSP0 0x00000100 111 #define SM502_INTR_RES3 0x00000080 /* reserved */ 112 #define SM502_INTR_UH 0x00000040 /* USB host */ 113 #define SM502_INTR_RES4 0x00000020 /* reserved */ 114 #define SM502_INTR_ZV1 0x00000010 /* zoomed video 1 */ 115 #define SM502_INTR_2D 0x00000008 /* 2D engine */ 116 #define SM502_INTR_ZV0 0x00000004 /* zoomed video 0 */ 117 #define SM502_INTR_PV 0x00000002 /* panel vsync */ 118 #define SM502_INTR_CI 0x00000001 /* command interpreter */ 119 120 #define SM502_DEBUG_CONTROL 0x00000034 121 122 #define SM502_CURRENT_GATE 0x00000038 123 #define SM502_GATE_AUDIO_ENABLE 0x00040000 124 #define SM502_GATE_8051_ENABLE 0x00020000 125 #define SM502_GATE_USB_SLAVE_ENABLE 0x00001000 126 #define SM502_GATE_USB_HOST_ENABLE 0x00000800 127 #define SM502_GATE_SSP_ENABLE 0x00000400 128 #define SM502_GATE_UART1_ENABLE 0x00000100 129 #define SM502_GATE_UART0_ENABLE 0x00000080 130 #define SM502_GATE_GPIO_ENABLE 0x00000040 131 #define SM502_GATE_ZV_ENABLE 0x00000020 132 #define SM502_GATE_CSC_ENABLE 0x00000010 133 #define SM502_GATE_2D_ENGINE_ENABLE 0x00000008 134 #define SM502_GATE_DISPLAY_ENABLE 0x00000004 135 #define SM502_GATE_MEMORY_ENABLE 0x00000002 136 #define SM502_GATE_HOST_ENABLE 0x00000001 137 #define SM502_CURRENT_CLOCK 0x0000003c 138 #define SM502_POWER_MODE0_GATE 0x00000040 139 #define SM502_POWER_MODE0_CLOCK 0x00000044 140 #define SM502_POWER_MODE1_GATE 0x00000048 141 #define SM502_POWER_MODE1_CLOCK 0x0000004c 142 #define SM502_SLEEP_MODE_GATE 0x00000050 143 #define SM502_POWER_MODE_CONTROL 0x00000054 144 145 /* GPIO */ 146 #define SM502_GPIO_DATA0 0x00010000 147 #define SM502_GPIO_DATA1 0x00010004 148 #define SM502_GPIO_DIR0 0x00010008 /* 1 is output */ 149 #define SM502_GPIO_DIR1 0x0001000c 150 #define SM502_GPIO_INTR_SETUP 0x00010010 151 #define SM502_GPIO_INTR_STATUS 0x00010014 /* read */ 152 #define SM502_GPIO_INTR_CLEAR 0x00010014 /* write */ 153 154 /* PWM - Pulse Width Modulation */ 155 #define SM502_PWM0 0x00010020 156 #define SM502_PWM1 0x00010024 157 #define SM502_PWM2 0x00010028 158 #define SM502_PWM_ENABLE 0x00000001 159 #define SM502_PWM_ENABLE_INTR 0x00000004 160 #define SM502_PWM_INTR_PENDING 0x00000008 /* write 1 to clear */ 161 /* 96MHz divided by 1 << n */ 162 #define SM502_PWM_CLOCK_DIV_MASK 0x000000f0 163 #define SM502_PWM_CLOCK_DIV_SHIFT 4 164 /* output remains low for n+1 cycles */ 165 #define SM502_PWM_CLOCK_LOW_MASK 0x000fff00 166 #define SM502_PWM_CLOCK_LOW_SHIFT 8 167 /* output remains high for n+1 cycles */ 168 #define SM502_PWM_CLOCK_HIGH_MASK 0xfff00000 169 #define SM502_PWM_CLOCK_HIGH_SHIFT 20 170 171 /* Video Controller Registers */ 172 #define SM502_PANEL_DISP_CTRL 0x080000 173 #define SM502_PDC_8BIT 0x00000000 174 #define SM502_PDC_16BIT 0x00000001 175 #define SM502_PDC_32BIT 0x00000002 176 #define SM502_PDC_DEPTH_MASK 0x00000003 177 #define SM502_PDC_PANEL_ENABLE 0x00000004 178 #define SM502_PDC_GAMMA_ENABLE 0x00000008 179 #define SM502_PDC_HPAN_AUTO 0x00000010 180 #define SM502_PDC_HPAN_DIR_LEFT 0x00000000 181 #define SM502_PDC_HPAN_DIR_RIGHT 0x00000020 182 #define SM502_PDC_VPAN_AUTO 0x00000040 183 #define SM502_PDC_VPAN_DIR_UP 0x00000080 184 #define SM502_PDC_VPAN_DIR_DOWN 0x00000000 185 #define SM502_PDC_TIMING_ENABLE 0x00000100 186 #define SM502_PDC_COLORKEY_ENABLE 0x00000200 187 #define SM502_PDC_CAPTURE_ZV_0 0x00000400 188 #define SM502_PDC_HSYNC_PHASE_LOW 0x00001000 189 #define SM502_PDC_HSYNC_PHASE_HIGH 0x00000000 190 #define SM502_PDC_VSYNC_PHASE_LOW 0x00002000 191 #define SM502_PDC_VSYNC_PHASE_HIGH 0x00000000 192 #define SM502_PDC_CLOCK_ACT_LOW 0x00004000 193 #define SM502_PDC_CLOCK_ACTIVE_HIGH 0x00000000 194 #define SM502_PDC_8BIT_TV_ENABLE 0x00008000 195 #define SM502_PDC_FIFO_HWATER_1 0x00000000 196 #define SM502_PDC_FIFO_HWATER_3 0x00010000 197 #define SM502_PDC_FIFO_HWATER_7 0x00020000 198 #define SM502_PDC_FIFO_HWATER_11 0x00030000 199 #define SM502_PDC_FIFO_HWATE_MASK 0x00030000 200 #define SM502_PDC_TYPE_TFT 0x00000000 201 #define SM502_PDC_TYPE_8BIT_STN 0x00040000 202 #define SM502_PDC_TYPE_12BIT_STN 0x00080000 203 #define SM502_PDC_TYPE_MASK 0x000c0000 204 #define SM502_PDC_DITHERING_ENABLE 0x00100000 205 #define SM502_PDC_TFT_RGB888 0x00000000 206 #define SM502_PDC_TFT_RGB333 0x00200000 207 #define SM502_PDC_TFT_RGB444 0x00400000 208 #define SM502_PDC_TFT_RGB_MASK 0x00600000 209 #define SM502_PDC_DITHER_8_GREY 0x00800000 210 #define SM502_PDC_FPVDDEN_HIGH 0x01000000 211 #define SM502_PDC_FPVDDEN_LOW 0x00000000 212 #define SM502_PDC_PANEL_SIGNALS_ENABLE 0x02000000 213 #define SM502_PDC_VBIASEN_HIGH 0x04000000 214 #define SM502_PDC_VBIASEN_LOW 0x00000000 215 #define SM502_PDC_GPEN_ENABLE 0x08000000 216 217 #define SM502_PANEL_PAN_CTRL 0x080004 218 #define SM502_PANEL_COLOR_KEY 0x080008 219 #define SM502_PANEL_FB_ADDRESS 0x08000C 220 #define SM502_FBA_MASK 0x03fffff0 /* 128bit align */ 221 #define SM502_FBA_CS1 0x04000000 222 #define SM502_FBA_CS0 0x00000000 223 #define SM502_FBA_SYSTEM_MEM 0x08000000 224 #define SM502_FBA_LOCAL_MEM 0x00000000 225 #define SM502_FBA_FLIP_PENDING 0x80000000 226 227 #define SM502_PANEL_FB_OFFSET 0x080010 228 #define SM502_FBO_FB_STRIDE_MASK 0x00003ff0 /* 128bit align */ 229 #define SM502_FBA_WIN_STRIDE_MASK 0x3ff00000 /* 128bit align */ 230 231 #define SM502_PANEL_FB_WIDTH 0x080014 232 #define SM502_FBW_WIN_X_MASK 0x00003fff 233 #define SM502_FBW_WIN_WIDTH_MASK 0x3fff0000 234 235 #define SM502_PANEL_FB_HEIGHT 0x080018 236 #define SM502_FBH_WIN_Y_MASK 0x00003fff 237 #define SM502_FBH_WIN_HEIGHT_MASK 0x3fff0000 238 #define SM502_PANEL_TL 0x08001C 239 #define SM502_TL_LEFT_MASK 0x000007ff 240 #define SM502_TL_TOP_MASK 0x07ff0000 241 242 #define SM502_PANEL_BR 0x080020 243 #define SM502_BR_RIGHT_MASK 0x000007ff 244 #define SM502_BR_BOTTOM_MASK 0x07ff0000 245 246 #define SM502_PANEL_HTOTAL 0x080024 247 #define SM502_HT_HDISPE_MASK 0x00000fff 248 #define SM502_HT_HTOTAL_MASK 0x0fff0000 249 #define SM502_PANEL_HSYNC 0x080028 250 #define SM502_PANEL_VTOTAL 0x08002C 251 #define SM502_VT_VDISPE_MASK 0x00000fff 252 #define SM502_VT_VTOTAL_MASK 0x0fff0000 253 #define SM502_PANEL_VSYNC 0x080030 254 #define SM502_PANEL_CRSR_ADDR 0x0800f0 255 #define SM502_CRSR_ENABLE 0x80000000 256 #define SM502_CRSR_SYSTEM_MEM 0x08000000 257 #define SM502_CRSR_SYSMEM_CS1 0x04000000 258 #define SM502_CRSR_ADDRESS_M 0x03fffff0 259 #define SM502_PANEL_CRSR_XY 0x0800f4 260 #define SM502_CRSR_X_MASK 0x00000fff 261 #define SM502_CRSR_Y_MASK 0x0fff0000 262 #define SM502_PANEL_CRSR_COL12 0x0800f8 263 #define SM502_CRSR_COLOR_1_MASK 0x0000ffff 264 #define SM502_CRSR_COLOR_2_MASK 0xffff0000 265 #define SM502_PANEL_CRSR_COL3 0x0800fc 266 #define SM502_CRSR_COLOR_3_MASK 0x0000ffff 267 268 269 #define SM502_PALETTE_PANEL 0x080400 270 #define SM502_PALETTE_VIDEO 0x080800 271 #define SM502_PALETTE_CRT 0x080c00 272 273 /* drawing engine */ 274 #define SM502_SRC 0x100000 275 #define SM502_SRC_WRAP_ENABLE 0x80000000 276 #define SM502_SRC_X_MASK 0x3fff0000 277 #define SM502_SRC_Y_MASK 0x0000ffff 278 279 #define SM502_DST 0x100004 280 #define SM502_DST_WRAP_ENABLE 0x80000000 281 #define SM502_DST_X_MASK 0x3fff0000 282 #define SM502_DST_Y_MASK 0x0000ffff 283 284 #define SM502_DIMENSION 0x100008 285 #define SM502_DIM_X_MASK 0x3fff0000 286 #define SM502_DIM_Y_MASK 0x0000ffff 287 288 #define SM502_CONTROL 0x10000c 289 #define ROP_COPY 0x0c 290 #define ROP_INVERT 0x03 291 #define SM502_CTRL_ROP_MASK 0x000000ff 292 #define SM502_CTRL_TRANSP_EN 0x00000100 293 #define SM502_CTRL_TRANSP_DST 0x00000200 294 #define SM502_CTRL_TRANSP_SRC 0x00000000 295 #define SM502_CTRL_TRANSP_MATCH 0x00000400 296 #define SM502_CTRL_OPAQUE_MATCH 0x00000000 297 #define SM502_CTRL_REPEAT_ROT 0x00000800 298 #define SM502_CTRL_MONO_PACK_MASK 0x00003000 299 #define SM502_CTRL_MONO_PACK_8BIT 0x00001000 300 #define SM502_CTRL_MONO_PACK_16BIT 0x00002000 301 #define SM502_CTRL_MONO_PACK_32BIT 0x00003000 302 #define SM502_CTRL_ROP2_SRC_PAT 0x00004000 /* otherwise src is bmp */ 303 #define SM502_CTRL_USE_ROP2 0x00008000 /* X-style ROPs vs. Win */ 304 #define SM502_CTRL_COMMAND_MASK 0x001f0000 305 #define SM502_CTRL_CMD_BITBLT 0x00000000 306 #define SM502_CTRL_CMD_RECTFILL 0x00010000 307 #define SM502_CTRL_CMD_DETILE 0x00020000 308 #define SM502_CTRL_CMD_TRAPFILL 0x00030000 309 #define SM502_CTRL_CMD_ALPHA 0x00040000 310 #define SM502_CTRL_CMD_RLESTRIP 0x00050000 311 #define SM502_CTRL_CMD_SHRTSTRK 0x00060000 312 #define SM502_CTRL_CMD_LINE 0x00070000 313 #define SM502_CTRL_CMD_HOSTWRT 0x00080000 314 #define SM502_CTRL_CMD_HOSTREAD 0x00090000 315 #define SM502_CTRL_CMD_WRT_BT 0x000a0000 316 #define SM502_CTRL_CMD_ROTATE 0x000b0000 317 #define SM502_CTRL_CMD_FONT 0x000c0000 318 #define SM502_CTRL_CMD_TEXLOAD 0x000f0000 319 #define SM502_CTRL_DRAWLAST 0x00200000 /* last pixel in line */ 320 #define SM502_CTRL_HOSTBLT_MONO 0x00400000 /* colour otherwise */ 321 #define SM502_CTRL_YSTRETCH_E 0x00800000 322 #define SM502_CTRL_Y_STEP_NEG 0x01000000 /* line, otherwise pos */ 323 #define SM502_CTRL_X_STEP_NEG 0x02000000 /* line, otherwise pos */ 324 #define SM502_CTRL_LINE_AX_Y 0x04000000 /* otherwise X */ 325 #define SM502_CTRL_R_TO_L 0x08000000 /* otherwise L to R */ 326 /* run command when writing SM502_DIMENSION */ 327 #define SM502_CTRL_QUICKSTART_E 0x10000000 328 #define SM502_CTRL_UPD_DESTX 0x20000000 329 #define SM502_CTRL_PAT_COLOR 0x40000000 /* otherwise mono */ 330 #define SM502_CTRL_ENGINE_START 0x80000000 331 332 #define SM502_PITCH 0x100010 333 #define SM502_PITCH_SRC_MASK 0x00003fff 334 #define SM502_PITCH_DST_MASK 0x3fff0000 335 336 #define SM502_FOREGROUND 0x100014 337 #define SM502_BACKGROUND 0x100018 338 #define SM502_STRETCH 0x10001c 339 #define SM502_STRETCH_HEIGHT_MASK 0x00000fff /* source */ 340 #define SM502_STRETCH_ADDR_LINEAR 0x000f0000 /* XY otherwise */ 341 #define SM502_STRETCH_PIXEL_FORMAT_MASK 0x00300000 342 #define SM502_STRETCH_8BIT 0x00000000 343 #define SM502_STRETCH_16BIT 0x00100000 344 #define SM502_STRETCH_32BIT 0x00200000 345 #define SM502_STRETCH_PAT_X_ORIGIN_MASK 0x03800000 346 #define SM502_STRETCH_PAT_Y_ORIGIN_MASK 0x38000000 347 #define SM502_STRETCH_PAT_XY_ENABLE 0x40000000 348 349 #define SM502_COLOR_COMPARE 0x100020 350 #define SM502_COLOR_COMP_MASK 0x100024 351 #define SM502_PLANEMASK 0x100028 352 #define SM502_CLIP_TOP_LEFT 0x10002c 353 #define SM501_CLIP_TOP_MASK 0xffff0000 354 #define SM501_CLIP_LEFT_MASK 0x00000fff 355 #define SM501_CLIP_BLOCK_INSIDE 0x00001000 /* otherwise block outside */ 356 #define SM501_CLIP_ENABLE 0x00002000 357 358 #define SM502_CLIP_BOTTOM_RIGHT 0x100030 359 #define SM501_CLIP_BOTTOM_MASK 0xffff0000 360 #define SM501_CLIP_RIGHT_MASK 0x00001fff 361 362 #define SM502_MONO_PATTERN_0 0x100034 363 #define SM502_MONO_PATTERN_1 0x100038 364 #define SM502_WINDOW_WIDTH 0x10003c 365 #define SM502_WIN_SRC_MASK 0x00001fff 366 #define SM502_WIN_DST_MASK 0x1fff0000 367 368 #define SM502_SRC_BASE 0x100040 369 #define SM502_SRC_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 370 #define SM502_SRC_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 371 #define SM502_SRC_BASE_SYSMEM 0x08000000 /* local otherw. */ 372 373 #define SM502_DST_BASE 0x100044 374 #define SM502_DST_BASE_ADDR_MASK 0x03fffff0 /* 128bit align */ 375 #define SM502_DST_BASE_SYSMEM_CS1 0x04000000 /* SC0 otherw. */ 376 #define SM502_DST_BASE_SYSMEM 0x08000000 /* local otherw. */ 377 378 #define SM502_ALPHA 0x100048 379 #define SM502_WRAP 0x10004c 380 #define SM502_WRAP_HEIGHT_MASK 0x0000ffff 381 #define SM502_WRAP_WIDTH_MASK 0xffff0000 382 383 #define SM502_STATUS 0x100050 384 #define SM502_CMD_DONE 0x00000001 385 #define SM502_CSC_DONE 0x00000002 386 387 #define SM502_DATAPORT 0x110000 388 389 /* AC97 Link */ 390 #define SM502_AC97_TX_TAG 0x0A0100 391 #define SM502_AC97_FRAME_VALID 0x8000 392 #define SM502_AC97_S1_VALID 0x4000 393 #define SM502_AC97_S2_VALID 0x2000 394 #define SM502_AC97_S3_VALID 0x1000 395 #define SM502_AC97_S4_VALID 0x0800 396 #define SM502_AC97_TX_ADDR 0x0A0104 397 #define SM502_AC97_READ 0x00100000 /* write otherwise */ 398 #define SM502_AC97_ADDR_MASK 0x000fe000 399 #define SM502_AC97_TX_DATA 0x0A0108 400 #define SM502_AC97_DATA_MASK 0x000ffff0 401 #define SM502_AC97_TX_LEFT 0x0A010C 402 #define SM502_AC97_TX_RIGHT 0x0A0110 403 #define SM502_AC97_RX_TAG 0x0A0140 404 #define SM502_AC97_RX_ADDR 0x0A0144 405 #define SM502_AC97_RX_DATA 0x0A0148 406 #define SM502_AC97_RX_LEFT 0x0A014C 407 #define SM502_AC97_RX_RIGHT 0x0A0150 408 #define SM502_AC97_CONTROL 0x0A0180 409 #define SM502_AC97_DROP_COUNT 0x0000fc00 410 #define SM502_AC97_STOP_SYNC 0x00000200 411 #define SM502_AC97_BCLK_RUNNING 0x00000100 412 #define SM502_AC97_WAKEUP_REQ 0x00000080 413 #define SM502_AC97_STATUS_MASK 0x00000030 414 #define SM502_AC97_STATUS_OFF 0x00000000 415 #define SM502_AC97_STATUS_RESET 0x00000010 416 #define SM502_AC97_STATUS_WAIT 0x00000020 417 #define SM502_AC97_STATUS_ON 0x00000030 418 #define SM502_AC97_WI_ENABLE 0x00000008 /* wakeup interrupt */ 419 #define SM502_AC97_WARM_RESET 0x00000004 /* 1uS at least */ 420 #define SM502_AC97_COLD_RESET 0x00000002 /* 1uS at least */ 421 #define SM502_AC97_ENABLE 0x00000001 422 423 #define SM502_AUDIO_GPIO_MASK 0x1f000000 /* pins used */ 424 425 /* 8051 Microcontroller */ 426 #define SM502_uC_RESET 0x000b0000 427 #define SM502_uC_ENABLE 0x00000001 /* reset otherwise */ 428 #define SM502_uC_MODE_SELECT 0x000b0004 429 #define SM502_uC_CLOCK_MASK 0x00000003 430 #define SM502_uC_CLOCK_DIV2 0x00000000 431 #define SM502_uC_CLOCK_DIV3 0x00000001 432 #define SM502_uC_CLOCK_DIV4 0x00000002 433 #define SM502_uC_CLOCK_DIV5 0x00000003 434 #define SM502_uC_CODEC_I2S 0x00000004 /* AC97 otherwise */ 435 #define SM502_uC_AUDIO_TEST 0x00000008 /* test mode */ 436 #define SM502_uC_IO_8BIT 0x00000010 /* 12 bit otherwise */ 437 #define SM502_uC_SRAM_DISABLE 0x00000020 438 #define SM502_uC_USB_WAIT_MASK 0x000000c0 439 #define SM502_uC_USB_NO_WAIT 0x00000000 440 #define SM502_uC_USB_1_WAIT 0x00000040 441 #define SM502_uC_USB_2_WAIT 0x00000080 442 #define SM502_uC_8051_INTR 0x000b0008 443 #define SM502_uC_CPU_INTR 0x000b000c 444 445 #define SM502_uC_SRAM_PROG 0x00dc0000 /* only readable in RESET */ 446 #define SM502_uC_SRAM_DATA 0x00dc3000 447 448 #endif /* SM502REG_H */ 449
Indexes created Sat Sep 20 22:09:52 GMT 2025