1 /* $NetBSD: w83l518d_sdmmc.c,v 1.7 2023/05/10 00:11:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: w83l518d_sdmmc.c,v 1.7 2023/05/10 00:11:08 riastradh Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/kernel.h> 33 #include <sys/systm.h> 34 #include <sys/errno.h> 35 #include <sys/ioctl.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <sys/proc.h> 39 40 #include <sys/bus.h> 41 42 #include <dev/sdmmc/sdmmcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmc_ioreg.h> 45 46 #include <dev/ic/w83l518dreg.h> 47 #include <dev/ic/w83l518dvar.h> 48 #include <dev/ic/w83l518d_sdmmc.h> 49 50 /* #define WB_SDMMC_DEBUG */ 51 52 #ifdef WB_SDMMC_DEBUG 53 static int wb_sdmmc_debug = 1; 54 #else 55 static int wb_sdmmc_debug = 0; 56 #endif 57 58 #if defined(__NetBSD__) && __NetBSD_Version__ < 599000600 59 #define snprintb(b, l, f, v) bitmask_snprintf((v), (f), (b), (l)) 60 #endif 61 62 #define REPORT(_wb, ...) \ 63 if (wb_sdmmc_debug > 0) \ 64 aprint_normal_dev(((struct wb_softc *)(_wb))->wb_dev, \ 65 __VA_ARGS__) 66 67 static int wb_sdmmc_host_reset(sdmmc_chipset_handle_t); 68 static uint32_t wb_sdmmc_host_ocr(sdmmc_chipset_handle_t); 69 static int wb_sdmmc_host_maxblklen(sdmmc_chipset_handle_t); 70 static int wb_sdmmc_card_detect(sdmmc_chipset_handle_t); 71 static int wb_sdmmc_write_protect(sdmmc_chipset_handle_t); 72 static int wb_sdmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 73 static int wb_sdmmc_bus_clock(sdmmc_chipset_handle_t, int); 74 static int wb_sdmmc_bus_width(sdmmc_chipset_handle_t, int); 75 static int wb_sdmmc_bus_rod(sdmmc_chipset_handle_t, int); 76 static void wb_sdmmc_exec_command(sdmmc_chipset_handle_t, 77 struct sdmmc_command *); 78 static void wb_sdmmc_card_enable_intr(sdmmc_chipset_handle_t, int); 79 static void wb_sdmmc_card_intr_ack(sdmmc_chipset_handle_t); 80 81 static struct sdmmc_chip_functions wb_sdmmc_chip_functions = { 82 .host_reset = wb_sdmmc_host_reset, 83 .host_ocr = wb_sdmmc_host_ocr, 84 .host_maxblklen = wb_sdmmc_host_maxblklen, 85 .card_detect = wb_sdmmc_card_detect, 86 .write_protect = wb_sdmmc_write_protect, 87 .bus_power = wb_sdmmc_bus_power, 88 .bus_clock = wb_sdmmc_bus_clock, 89 .bus_width = wb_sdmmc_bus_width, 90 .bus_rod = wb_sdmmc_bus_rod, 91 .exec_command = wb_sdmmc_exec_command, 92 .card_enable_intr = wb_sdmmc_card_enable_intr, 93 .card_intr_ack = wb_sdmmc_card_intr_ack, 94 }; 95 96 static void 97 wb_sdmmc_read_data(struct wb_softc *wb, uint8_t *data, int len) 98 { 99 bus_space_read_multi_1(wb->wb_iot, wb->wb_ioh, WB_SD_FIFO, data, len); 100 } 101 102 static void 103 wb_sdmmc_write_data(struct wb_softc *wb, uint8_t *data, int len) 104 { 105 bus_space_write_multi_1(wb->wb_iot, wb->wb_ioh, WB_SD_FIFO, data, len); 106 } 107 108 static void 109 wb_sdmmc_discover(void *opaque) 110 { 111 struct wb_softc *wb = opaque; 112 113 REPORT(wb, "TRACE: discover(wb)\n"); 114 115 sdmmc_needs_discover(wb->wb_sdmmc_dev); 116 } 117 118 static bool 119 wb_sdmmc_enable(struct wb_softc *wb) 120 { 121 int i = 5000; 122 123 REPORT(wb, "TRACE: enable(wb)\n"); 124 125 /* put the device in a known state */ 126 wb_idx_write(wb, WB_INDEX_SETUP, WB_SETUP_SOFT_RST); 127 while (--i > 0 && wb_idx_read(wb, WB_INDEX_SETUP) & WB_SETUP_SOFT_RST) 128 delay(100); 129 if (i == 0) { 130 aprint_error_dev(wb->wb_dev, "timeout resetting device\n"); 131 return false; 132 } 133 wb_idx_write(wb, WB_INDEX_CLK, wb->wb_sdmmc_clk); 134 wb_idx_write(wb, WB_INDEX_FIFOEN, 0); 135 wb_idx_write(wb, WB_INDEX_DMA, 0); 136 wb_idx_write(wb, WB_INDEX_PBSMSB, 0); 137 wb_idx_write(wb, WB_INDEX_PBSLSB, 0); 138 /* drain FIFO */ 139 while ((wb_read(wb, WB_SD_FIFOSTS) & WB_FIFO_EMPTY) == 0) 140 wb_read(wb, WB_SD_FIFO); 141 142 wb_write(wb, WB_SD_CSR, 0); 143 144 wb_write(wb, WB_SD_INTCTL, WB_INT_DEFAULT); 145 146 wb_sdmmc_card_detect(wb); 147 148 return true; 149 } 150 151 static bool 152 wb_sdmmc_disable(struct wb_softc *wb) 153 { 154 uint8_t val; 155 156 REPORT(wb, "TRACE: disable(wb)\n"); 157 158 val = wb_read(wb, WB_SD_CSR); 159 val |= WB_CSR_POWER_N; 160 wb_write(wb, WB_SD_CSR, val); 161 162 return true; 163 } 164 165 void 166 wb_sdmmc_attach(struct wb_softc *wb) 167 { 168 struct sdmmcbus_attach_args saa; 169 170 callout_init(&wb->wb_sdmmc_callout, 0); 171 callout_setfunc(&wb->wb_sdmmc_callout, wb_sdmmc_discover, wb); 172 173 wb->wb_sdmmc_width = 1; 174 wb->wb_sdmmc_clk = WB_CLK_375K; 175 176 if (wb_sdmmc_enable(wb) == false) 177 return; 178 179 memset(&saa, 0, sizeof(saa)); 180 saa.saa_busname = "sdmmc"; 181 saa.saa_sct = &wb_sdmmc_chip_functions; 182 saa.saa_sch = wb; 183 saa.saa_clkmin = 375; 184 saa.saa_clkmax = 24000; 185 if (!ISSET(wb->wb_quirks, WB_QUIRK_1BIT)) 186 saa.saa_caps = SMC_CAPS_4BIT_MODE; 187 188 wb->wb_sdmmc_dev = config_found(wb->wb_dev, &saa, NULL, CFARGS_NONE); 189 } 190 191 int 192 wb_sdmmc_detach(struct wb_softc *wb, int flags) 193 { 194 int error; 195 196 error = config_detach_children(wb->wb_dev, flags); 197 if (error) 198 return error; 199 wb_sdmmc_disable(wb); 200 201 callout_halt(&wb->wb_sdmmc_callout, NULL); 202 callout_destroy(&wb->wb_sdmmc_callout); 203 204 return 0; 205 } 206 207 /* 208 * SD/MMC interface 209 */ 210 static int 211 wb_sdmmc_host_reset(sdmmc_chipset_handle_t sch) 212 { 213 REPORT(sch, "TRACE: sdmmc/host_reset(wb)\n"); 214 215 return 0; 216 } 217 218 static uint32_t 219 wb_sdmmc_host_ocr(sdmmc_chipset_handle_t sch) 220 { 221 REPORT(sch, "TRACE: sdmmc/host_ocr(wb)\n"); 222 223 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 224 } 225 226 static int 227 wb_sdmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 228 { 229 REPORT(sch, "TRACE: sdmmc/host_maxblklen(wb)\n"); 230 231 return 512; /* XXX */ 232 } 233 234 static int 235 wb_sdmmc_card_detect(sdmmc_chipset_handle_t sch) 236 { 237 struct wb_softc *wb = sch; 238 int rv; 239 240 wb_led(wb, true); 241 rv = (wb_read(wb, WB_SD_CSR) & WB_CSR_CARD_PRESENT) ? 1 : 0; 242 wb_led(wb, false); 243 244 REPORT(wb, "TRACE: sdmmc/card_detect(wb) -> %d\n", rv); 245 246 return rv; 247 } 248 249 static int 250 wb_sdmmc_write_protect(sdmmc_chipset_handle_t sch) 251 { 252 struct wb_softc *wb = sch; 253 int rv; 254 255 wb_led(wb, true); 256 rv = (wb_read(wb, WB_SD_CSR) & WB_CSR_WRITE_PROTECT) ? 1 : 0; 257 wb_led(wb, false); 258 259 REPORT(wb, "TRACE: sdmmc/write_protect(wb) -> %d\n", rv); 260 261 return rv; 262 } 263 264 static int 265 wb_sdmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 266 { 267 REPORT(sch, "TRACE: sdmmc/bus_power(wb, ocr=%x)\n", ocr); 268 269 return 0; 270 } 271 272 static int 273 wb_sdmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 274 { 275 struct wb_softc *wb = sch; 276 uint8_t clk; 277 278 REPORT(wb, "TRACE: sdmmc/bus_clock(wb, freq=%d)\n", freq); 279 280 if (freq >= 24000) 281 clk = WB_CLK_24M; 282 else if (freq >= 16000) 283 clk = WB_CLK_16M; 284 else if (freq >= 12000) 285 clk = WB_CLK_12M; 286 else 287 clk = WB_CLK_375K; 288 289 wb->wb_sdmmc_clk = clk; 290 291 if (wb_idx_read(wb, WB_INDEX_CLK) != clk) 292 wb_idx_write(wb, WB_INDEX_CLK, clk); 293 294 return 0; 295 } 296 297 static int 298 wb_sdmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 299 { 300 struct wb_softc *wb = sch; 301 302 REPORT(wb, "TRACE: sdmmc/bus_width(wb, width=%d)\n", width); 303 304 if (width != 1 && width != 4) 305 return 1; 306 307 wb->wb_sdmmc_width = width; 308 309 return 0; 310 } 311 312 static int 313 wb_sdmmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 314 { 315 316 /* Not support */ 317 return -1; 318 } 319 320 321 static void 322 wb_sdmmc_rsp_read_long(struct wb_softc *wb, struct sdmmc_command *cmd) 323 { 324 uint8_t *p = (uint8_t *)cmd->c_resp; 325 int i; 326 327 if (wb_idx_read(wb, WB_INDEX_RESPLEN) != 1) { 328 cmd->c_error = ENXIO; 329 return; 330 } 331 332 for (i = 12; i >= 0; i -= 4) { 333 #if BYTE_ORDER == LITTLE_ENDIAN 334 p[3] = wb_idx_read(wb, WB_INDEX_RESP(i + 0)); 335 p[2] = wb_idx_read(wb, WB_INDEX_RESP(i + 1)); 336 p[1] = wb_idx_read(wb, WB_INDEX_RESP(i + 2)); 337 p[0] = wb_idx_read(wb, WB_INDEX_RESP(i + 3)); 338 #else 339 p[0] = wb_idx_read(wb, WB_INDEX_RESP(i + 0)); 340 p[1] = wb_idx_read(wb, WB_INDEX_RESP(i + 1)); 341 p[2] = wb_idx_read(wb, WB_INDEX_RESP(i + 2)); 342 p[3] = wb_idx_read(wb, WB_INDEX_RESP(i + 3)); 343 #endif 344 REPORT(wb, "TRACE: sdmmc/read_long (%d) 0x%08x\n", 345 (12 - i) / 4, cmd->c_resp[(12 - i) / 4]); 346 p += 4; 347 } 348 } 349 350 static void 351 wb_sdmmc_rsp_read_short(struct wb_softc *wb, struct sdmmc_command *cmd) 352 { 353 uint8_t *p = (uint8_t *)cmd->c_resp; 354 355 if (wb_idx_read(wb, WB_INDEX_RESPLEN) != 0) { 356 cmd->c_error = ENXIO; 357 return; 358 } 359 360 #if BYTE_ORDER == LITTLE_ENDIAN 361 p[3] = wb_idx_read(wb, WB_INDEX_RESP(12)); 362 p[2] = wb_idx_read(wb, WB_INDEX_RESP(13)); 363 p[1] = wb_idx_read(wb, WB_INDEX_RESP(14)); 364 p[0] = wb_idx_read(wb, WB_INDEX_RESP(15)); 365 #else 366 p[0] = wb_idx_read(wb, WB_INDEX_RESP(12)); 367 p[1] = wb_idx_read(wb, WB_INDEX_RESP(13)); 368 p[2] = wb_idx_read(wb, WB_INDEX_RESP(14)); 369 p[3] = wb_idx_read(wb, WB_INDEX_RESP(15)); 370 #endif 371 REPORT(wb, "TRACE: sdmmc/read_short 0x%08x\n", 372 cmd->c_resp[0]); 373 } 374 375 static int 376 wb_sdmmc_transfer_data(struct wb_softc *wb, struct sdmmc_command *cmd) 377 { 378 uint8_t fifosts; 379 int datalen, retry = 5000; 380 381 if (wb->wb_sdmmc_intsts & WB_INT_CARD) 382 return EIO; 383 384 fifosts = wb_read(wb, WB_SD_FIFOSTS); 385 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 386 if (fifosts & WB_FIFO_EMPTY) { 387 while (--retry > 0) { 388 fifosts = wb_read(wb, WB_SD_FIFOSTS); 389 if ((fifosts & WB_FIFO_EMPTY) == 0) 390 break; 391 delay(100); 392 } 393 if (retry == 0) 394 return EBUSY; 395 } 396 397 if (fifosts & WB_FIFO_FULL) 398 datalen = 16; 399 else 400 datalen = fifosts & WB_FIFO_DEPTH_MASK; 401 } else { 402 if (fifosts & WB_FIFO_FULL) { 403 while (--retry > 0) { 404 fifosts = wb_read(wb, WB_SD_FIFOSTS); 405 if ((fifosts & WB_FIFO_FULL) == 0) 406 break; 407 delay(100); 408 } 409 if (retry == 0) 410 return EBUSY; 411 } 412 413 if (fifosts & WB_FIFO_EMPTY) 414 datalen = 16; 415 else 416 datalen = 16 - (fifosts & WB_FIFO_DEPTH_MASK); 417 } 418 419 datalen = MIN(datalen, cmd->c_resid); 420 if (datalen > 0) { 421 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 422 wb_sdmmc_read_data(wb, cmd->c_buf, datalen); 423 else 424 wb_sdmmc_write_data(wb, cmd->c_buf, datalen); 425 426 cmd->c_buf += datalen; 427 cmd->c_resid -= datalen; 428 } 429 430 return 0; 431 } 432 433 static void 434 wb_sdmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 435 { 436 static const int opcodes[] = { 437 11, 17, 18, 20, 24, 25, 26, 27, 30, 42, 51, 56 438 }; 439 struct wb_softc *wb = sch; 440 uint8_t val; 441 int blklen; 442 int error; 443 int i, retry; 444 int s; 445 446 REPORT(wb, "TRACE: sdmmc/exec_command(wb, cmd) " 447 "opcode %d flags 0x%x data %p datalen %d arg 0x%08x\n", 448 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 449 cmd->c_arg); 450 451 if (cmd->c_datalen > 0) { 452 /* controller only supports a select number of data opcodes */ 453 for (i = 0; i < __arraycount(opcodes); i++) 454 if (opcodes[i] == cmd->c_opcode) 455 break; 456 if (i == __arraycount(opcodes)) { 457 cmd->c_error = ENOTSUP; 458 aprint_debug_dev(wb->wb_dev, 459 "unsupported opcode %d\n", cmd->c_opcode); 460 goto done; 461 } 462 463 /* Fragment the data into proper blocks */ 464 blklen = MIN(cmd->c_datalen, cmd->c_blklen); 465 466 if (cmd->c_datalen % blklen > 0) { 467 aprint_error_dev(wb->wb_dev, 468 "data is not a multiple of %u bytes\n", blklen); 469 cmd->c_error = EINVAL; 470 goto done; 471 } 472 473 /* setup block size registers */ 474 blklen = blklen + 2 * wb->wb_sdmmc_width; 475 wb_idx_write(wb, WB_INDEX_PBSMSB, 476 ((blklen >> 4) & 0xf0) | (wb->wb_sdmmc_width / 4)); 477 wb_idx_write(wb, WB_INDEX_PBSLSB, blklen & 0xff); 478 479 /* clear FIFO */ 480 val = wb_idx_read(wb, WB_INDEX_SETUP); 481 val |= WB_SETUP_FIFO_RST; 482 wb_idx_write(wb, WB_INDEX_SETUP, val); 483 while (wb_idx_read(wb, WB_INDEX_SETUP) & WB_SETUP_FIFO_RST) 484 ; 485 486 cmd->c_resid = cmd->c_datalen; 487 cmd->c_buf = cmd->c_data; 488 489 /* setup FIFO thresholds */ 490 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 491 wb_idx_write(wb, WB_INDEX_FIFOEN, WB_FIFOEN_FULL | 8); 492 else { 493 wb_idx_write(wb, WB_INDEX_FIFOEN, WB_FIFOEN_EMPTY | 8); 494 495 /* pre-fill the FIFO on write */ 496 error = wb_sdmmc_transfer_data(wb, cmd); 497 if (error) { 498 cmd->c_error = error; 499 goto done; 500 } 501 } 502 } 503 504 s = splsdmmc(); 505 wb->wb_sdmmc_intsts = 0; 506 wb_write(wb, WB_SD_COMMAND, cmd->c_opcode); 507 wb_write(wb, WB_SD_COMMAND, (cmd->c_arg >> 24) & 0xff); 508 wb_write(wb, WB_SD_COMMAND, (cmd->c_arg >> 16) & 0xff); 509 wb_write(wb, WB_SD_COMMAND, (cmd->c_arg >> 8) & 0xff); 510 wb_write(wb, WB_SD_COMMAND, (cmd->c_arg >> 0) & 0xff); 511 splx(s); 512 513 retry = 100000; 514 while (wb_idx_read(wb, WB_INDEX_STATUS) & WB_STATUS_CARD_TRAFFIC) { 515 if (--retry == 0) 516 break; 517 delay(1); 518 } 519 if (wb_idx_read(wb, WB_INDEX_STATUS) & WB_STATUS_CARD_TRAFFIC) { 520 REPORT(wb, 521 "command timed out, WB_INDEX_STATUS = 0x%02x\n", 522 wb_idx_read(wb, WB_INDEX_STATUS)); 523 cmd->c_error = ETIMEDOUT; 524 goto done; 525 } 526 527 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 528 if (wb->wb_sdmmc_intsts & WB_INT_TIMEOUT) { 529 cmd->c_error = ETIMEDOUT; 530 goto done; 531 } 532 533 if (ISSET(cmd->c_flags, SCF_RSP_136)) 534 wb_sdmmc_rsp_read_long(wb, cmd); 535 else 536 wb_sdmmc_rsp_read_short(wb, cmd); 537 } 538 539 if (cmd->c_error == 0 && cmd->c_datalen > 0) { 540 wb_led(wb, true); 541 while (cmd->c_resid > 0) { 542 error = wb_sdmmc_transfer_data(wb, cmd); 543 if (error) { 544 cmd->c_error = error; 545 break; 546 } 547 } 548 wb_led(wb, false); 549 } 550 551 done: 552 SET(cmd->c_flags, SCF_ITSDONE); 553 554 if (cmd->c_error) { 555 REPORT(wb, 556 "cmd error = %d, op = %d [%s] " 557 "blklen %d datalen %d resid %d\n", 558 cmd->c_error, cmd->c_opcode, 559 ISSET(cmd->c_flags, SCF_CMD_READ) ? "rd" : "wr", 560 cmd->c_blklen, cmd->c_datalen, cmd->c_resid); 561 } 562 } 563 564 static void 565 wb_sdmmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 566 { 567 REPORT(sch, "TRACE: sdmmc/card_enable_intr(wb, enable=%d)\n", enable); 568 } 569 570 static void 571 wb_sdmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 572 { 573 REPORT(sch, "TRACE: sdmmc/card_intr_ack(wb)\n"); 574 } 575 576 /* 577 * intr handler 578 */ 579 int 580 wb_sdmmc_intr(struct wb_softc *wb) 581 { 582 uint8_t val; 583 584 val = wb_read(wb, WB_SD_INTSTS); 585 if (val == 0xff || val == 0x00) 586 return 0; 587 588 if (wb->wb_sdmmc_dev == NULL) 589 return 1; 590 591 wb->wb_sdmmc_intsts |= val; 592 593 if (wb_sdmmc_debug) { 594 char buf[64]; 595 snprintb(buf, sizeof(buf), 596 "\20\1TC\2BUSYEND\3PROGEND\4TIMEOUT" 597 "\5CRC\6FIFO\7CARD\010PENDING", 598 val); 599 REPORT(wb, "WB_SD_INTSTS = %s\n", buf); 600 } 601 602 if (val & WB_INT_CARD) 603 callout_schedule(&wb->wb_sdmmc_callout, hz / 4); 604 605 return 1; 606 } 607 608 /* 609 * pmf 610 */ 611 bool 612 wb_sdmmc_suspend(struct wb_softc *wb) 613 { 614 return wb_sdmmc_disable(wb); 615 } 616 617 bool 618 wb_sdmmc_resume(struct wb_softc *wb) 619 { 620 uint8_t val; 621 622 val = wb_read(wb, WB_SD_CSR); 623 val &= ~WB_CSR_POWER_N; 624 wb_write(wb, WB_SD_CSR, val); 625 626 if (wb_sdmmc_enable(wb) == false) 627 return false; 628 629 if (wb_idx_read(wb, WB_INDEX_CLK) != wb->wb_sdmmc_clk) 630 wb_idx_write(wb, WB_INDEX_CLK, wb->wb_sdmmc_clk); 631 632 return true; 633 } 634
Indexes created Sat Sep 20 22:09:52 GMT 2025