1 /* $NetBSD: i82365_isasubr.c,v 1.50 2024/09/08 09:36:50 rillig Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1998 Bill Sommerfeld. All rights reserved. 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: i82365_isasubr.c,v 1.50 2024/09/08 09:36:50 rillig Exp $"); 36 37 #define PCICISADEBUG 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 44 #include <sys/bus.h> 45 #include <sys/intr.h> 46 47 #include <dev/isa/isareg.h> 48 #include <dev/isa/isavar.h> 49 50 #include <dev/pcmcia/pcmciareg.h> 51 #include <dev/pcmcia/pcmciavar.h> 52 #include <dev/pcmcia/pcmciachip.h> 53 54 #include <dev/ic/i82365reg.h> 55 #include <dev/ic/i82365var.h> 56 #include <dev/isa/i82365_isavar.h> 57 58 /***************************************************************************** 59 * Configurable parameters. 60 *****************************************************************************/ 61 62 #include "opt_pcic_isa_alloc_iobase.h" 63 #include "opt_pcic_isa_alloc_iosize.h" 64 #include "opt_pcic_isa_intr_alloc_mask.h" 65 66 /* 67 * Default I/O allocation range. If both are set to non-zero, these 68 * values will be used instead. Otherwise, the code attempts to probe 69 * the bus width. Systems with 10 address bits should use 0x300 and 0xff. 70 * Systems with 12 address bits (most) should use 0x400 and 0xbff. 71 */ 72 73 #ifndef PCIC_ISA_ALLOC_IOBASE 74 #define PCIC_ISA_ALLOC_IOBASE 0 75 #endif 76 77 #ifndef PCIC_ISA_ALLOC_IOSIZE 78 #define PCIC_ISA_ALLOC_IOSIZE 0 79 #endif 80 81 int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE; 82 int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE; 83 84 85 /* 86 * Default IRQ allocation bitmask. This defines the range of allowable 87 * IRQs for PCMCIA slots. Useful if order of probing would screw up other 88 * devices, or if PCIC hardware/cards have trouble with certain interrupt 89 * lines. 90 */ 91 92 #ifndef PCIC_ISA_INTR_ALLOC_MASK 93 #define PCIC_ISA_INTR_ALLOC_MASK 0xffff 94 #endif 95 96 int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK; 97 98 #ifndef PCIC_IRQ_PROBE 99 #ifdef hpcmips 100 /* 101 * The irq probing doesn't work with current vrisab implementation. 102 * The irq is just a key to find matching GPIO port to use and is fixed. 103 */ 104 #define PCIC_IRQ_PROBE 0 105 #else 106 #define PCIC_IRQ_PROBE 1 107 #endif 108 #endif 109 110 int pcic_irq_probe = PCIC_IRQ_PROBE; 111 112 /***************************************************************************** 113 * End of configurable parameters. 114 *****************************************************************************/ 115 116 #ifdef PCICISADEBUG 117 int pcicsubr_debug = 0; 118 #define DPRINTF(arg) do { if (pcicsubr_debug) printf arg ; } while (0) 119 #else 120 #define DPRINTF(arg) 121 #endif 122 123 /* 124 * count the interrupt if we have a status set 125 * just use socket 0 126 */ 127 128 void pcic_isa_probe_interrupts(struct pcic_isa_softc *, struct pcic_handle *); 129 static int pcic_isa_count_intr(void *); 130 131 static int 132 pcic_isa_count_intr(void *arg) 133 { 134 struct pcic_softc *sc; 135 struct pcic_isa_softc *isc; 136 struct pcic_handle *h; 137 int cscreg; 138 139 h = arg; 140 isc = device_private(h->ph_parent); 141 sc = &isc->sc_pcic; 142 143 cscreg = pcic_read(h, PCIC_CSC); 144 if (cscreg & PCIC_CSC_CD) { 145 if ((++sc->intr_detect % 20) == 0) 146 printf("."); 147 else 148 DPRINTF((".")); 149 return 1; 150 } 151 152 /* 153 * make sure we don't get stuck in a loop due to 154 * unhandled level interrupts 155 */ 156 if (++sc->intr_false > 40) { 157 pcic_write(h, PCIC_CSC_INTR, 0); 158 delay(10); 159 } 160 161 #ifdef PCICISADEBUG 162 if (cscreg) 163 DPRINTF(("o")); 164 else 165 DPRINTF(("X")); 166 #endif 167 return cscreg ? 1 : 0; 168 } 169 170 /* 171 * use soft interrupt card detect to find out which irqs are available 172 * for this controller 173 */ 174 void 175 pcic_isa_probe_interrupts(struct pcic_isa_softc *isc, struct pcic_handle *h) 176 { 177 struct pcic_softc *sc = &isc->sc_pcic; 178 isa_chipset_tag_t ic; 179 int i, j, mask, irq; 180 int cd, cscintr, intr, csc; 181 182 ic = isc->sc_ic; 183 184 printf("%s: controller %d detecting irqs with mask 0x%04x:", 185 device_xname(sc->dev), h->chip, sc->intr_mask[h->chip]); 186 DPRINTF(("\n")); 187 188 /* clear any current interrupt */ 189 pcic_read(h, PCIC_CSC); 190 191 /* first disable the status irq, card detect is enabled later */ 192 pcic_write(h, PCIC_CSC_INTR, 0); 193 194 /* steer the interrupt to isa and disable ring and interrupt */ 195 intr = pcic_read(h, PCIC_INTR); 196 DPRINTF(("pcic: old intr 0x%x\n", intr)); 197 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | PCIC_INTR_IRQ_MASK); 198 pcic_write(h, PCIC_INTR, intr); 199 200 201 /* clear any current interrupt */ 202 pcic_read(h, PCIC_CSC); 203 204 cd = pcic_read(h, PCIC_CARD_DETECT); 205 cd |= PCIC_CARD_DETECT_SW_INTR; 206 207 mask = 0; 208 for (i = 0; i < 16; i++) { 209 /* honor configured limitations */ 210 if ((sc->intr_mask[h->chip] & (1 << i)) == 0) 211 continue; 212 213 DPRINTF(("probing irq %d: ", i)); 214 215 /* ask for a pulse interrupt so we don't share */ 216 if (isa_intr_alloc(ic, (1 << i), IST_PULSE, &irq)) { 217 DPRINTF(("currently allocated\n")); 218 continue; 219 } 220 221 cscintr = PCIC_CSC_INTR_CD_ENABLE; 222 cscintr |= (irq << PCIC_CSC_INTR_IRQ_SHIFT); 223 pcic_write(h, PCIC_CSC_INTR, cscintr); 224 delay(10); 225 226 /* Clear any pending interrupt. */ 227 (void) pcic_read(h, PCIC_CSC); 228 229 if ((sc->ih = isa_intr_establish(ic, irq, IST_EDGE, IPL_TTY, 230 pcic_isa_count_intr, h)) == NULL) 231 panic("cant get interrupt"); 232 233 /* interrupt 40 times */ 234 sc->intr_detect = 0; 235 for (j = 0; j < 40 && sc->ih; j++) { 236 sc->intr_false = 0; 237 pcic_write(h, PCIC_CARD_DETECT, cd); 238 delay(100); 239 csc = pcic_read(h, PCIC_CSC); 240 DPRINTF(("%s", csc ? "-" : "")); 241 } 242 DPRINTF((" total %d\n", sc->intr_detect)); 243 /* allow for misses */ 244 if (sc->intr_detect > 37 && sc->intr_detect <= 40) { 245 printf("%d", i); 246 DPRINTF((" succeded\n")); 247 mask |= (1 << i); 248 } 249 250 if (sc->ih != NULL) { 251 isa_intr_disestablish(ic, sc->ih); 252 sc->ih = NULL; 253 254 pcic_write(h, PCIC_CSC_INTR, 0); 255 delay(10); 256 } 257 } 258 sc->intr_mask[h->chip] = mask; 259 260 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none"); 261 } 262 263 /* 264 * called with interrupts enabled, light up the irqs to find out 265 * which irq lines are actually hooked up to our pcic 266 */ 267 void 268 pcic_isa_config_interrupts(device_t self) 269 { 270 struct pcic_softc *sc; 271 struct pcic_isa_softc *isc; 272 struct pcic_handle *h; 273 isa_chipset_tag_t ic; 274 int s, i, chipmask, chipuniq; 275 276 isc = device_private(self); 277 sc = &isc->sc_pcic; 278 ic = isc->sc_ic; 279 280 /* probe each controller */ 281 chipmask = 0xffff; 282 for (i = 0; i < PCIC_NSLOTS; i += 2) { 283 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 284 h = &sc->handle[i]; 285 else if (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) 286 h = &sc->handle[i + 1]; 287 else 288 continue; 289 290 sc->intr_mask[h->chip] = 291 PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask; 292 293 /* the cirrus chips lack support for the soft interrupt */ 294 if (pcic_irq_probe != 0 && 295 h->vendor != PCIC_VENDOR_CIRRUS_PD67XX) 296 pcic_isa_probe_interrupts(isc, h); 297 298 chipmask &= sc->intr_mask[h->chip]; 299 } 300 /* now see if there is at least one irq per chip not shared by all */ 301 chipuniq = 1; 302 for (i = 0; i < PCIC_NSLOTS; i += 2) { 303 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 304 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 305 continue; 306 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) { 307 chipuniq = 0; 308 break; 309 } 310 } 311 /* 312 * the rest of the following code used to run at config time with 313 * no interrupts and gets unhappy if this is violated so... 314 */ 315 s = splhigh(); 316 317 /* 318 * allocate our irq. it will be used by both controllers. I could 319 * use two different interrupts, but interrupts are relatively 320 * scarce, shareable, and for PCIC controllers, very infrequent. 321 */ 322 if ((device_cfdata(self)->cf_flags & 1) == 0) { 323 if (sc->irq != ISA_UNKNOWN_IRQ) { 324 if ((chipmask & (1 << sc->irq)) == 0) 325 printf("%s: warning: configured irq %d not " 326 "detected as available\n", 327 device_xname(self), sc->irq); 328 } else if (chipmask == 0 || 329 isa_intr_alloc(ic, chipmask, IST_EDGE, &sc->irq)) { 330 aprint_error_dev(self, "no available irq; "); 331 sc->irq = ISA_UNKNOWN_IRQ; 332 } else if ((chipmask & ~(1 << sc->irq)) == 0 && chipuniq == 0) { 333 aprint_error_dev(self, "can't share irq with cards; "); 334 sc->irq = ISA_UNKNOWN_IRQ; 335 } 336 } else { 337 printf("%s: ", device_xname(self)); 338 sc->irq = ISA_UNKNOWN_IRQ; 339 } 340 341 if (sc->irq != ISA_UNKNOWN_IRQ) { 342 sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY, 343 pcic_intr, sc); 344 if (sc->ih == NULL) { 345 aprint_error_dev(self, "can't establish interrupt"); 346 sc->irq = ISA_UNKNOWN_IRQ; 347 } 348 } 349 if (sc->irq == ISA_UNKNOWN_IRQ) 350 printf("polling for socket events\n"); 351 else 352 printf("%s: using irq %d for socket events\n", 353 device_xname(self), sc->irq); 354 355 pcic_attach_sockets_finish(sc); 356 357 splx(s); 358 } 359 360 /* 361 * XXX This routine does not deal with the aliasing issue that its 362 * trying to. 363 * 364 * Any isa device may be decoding only 10 bits of address including 365 * the pcic. This routine only detects if the pcic is doing 10 bits. 366 * 367 * What should be done is detect the pcic's idea of the bus width, 368 * and then within those limits allocate a sparse map, where the 369 * each sub region is offset by 0x400. 370 */ 371 void pcic_isa_bus_width_probe(struct pcic_softc *sc, bus_space_tag_t iot, 372 bus_space_handle_t ioh, bus_addr_t base, uint32_t length) 373 { 374 bus_space_handle_t ioh_high; 375 int i, iobuswidth, tmp1, tmp2; 376 377 /* 378 * figure out how wide the isa bus is. Do this by checking if the 379 * pcic controller is mirrored 0x400 above where we expect it to be. 380 */ 381 382 iobuswidth = 12; 383 384 /* Map i/o space. */ 385 if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) { 386 aprint_error_dev(sc->dev, "can't map high i/o space\n"); 387 return; 388 } 389 390 for (i = 0; i < PCIC_NSLOTS; i++) { 391 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 392 /* 393 * read the ident flags from the normal space and 394 * from the mirror, and compare them 395 */ 396 397 bus_space_write_1(iot, ioh, PCIC_REG_INDEX, 398 sc->handle[i].sock + PCIC_IDENT); 399 tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA); 400 401 bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX, 402 sc->handle[i].sock + PCIC_IDENT); 403 tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA); 404 405 if (tmp1 == tmp2) 406 iobuswidth = 10; 407 } 408 } 409 410 bus_space_free(iot, ioh_high, length); 411 412 /* 413 * XXX some hardware doesn't seem to grok addresses in 0x400 range-- 414 * apparently missing a bit or more of address lines. (e.g. 415 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI 416 * TravelMate 5000--not clear which is at fault) 417 * 418 * Add a kludge to detect 10 bit wide buses and deal with them, 419 * and also a config file option to override the probe. 420 */ 421 422 if (iobuswidth == 10) { 423 sc->iobase = 0x300; 424 sc->iosize = 0x0ff; 425 } else { 426 sc->iobase = 0x400; 427 sc->iosize = 0xbff; 428 } 429 430 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n", 431 device_xname(sc->dev), (long) sc->iobase, 432 (long)(sc->iobase + sc->iosize))); 433 434 if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) { 435 sc->iobase = pcic_isa_alloc_iobase; 436 sc->iosize = pcic_isa_alloc_iosize; 437 438 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx " 439 "(config override)\n", device_xname(sc->dev), 440 (long) sc->iobase, (long)(sc->iobase + sc->iosize))); 441 } 442 } 443 444 void * 445 pcic_isa_chip_intr_establish(pcmcia_chipset_handle_t pch, 446 struct pcmcia_function *pf, int ipl, int (*fct)(void *), void *arg) 447 { 448 struct pcic_handle *h = (struct pcic_handle *) pch; 449 struct pcic_isa_softc *isc = device_private(h->ph_parent); 450 struct pcic_softc *sc = &isc->sc_pcic; 451 isa_chipset_tag_t ic = isc->sc_ic; 452 int irq, ist; 453 void *ih; 454 int reg; 455 456 /* 457 * PLEASE NOTE: 458 * The IRQLEVEL bit has no bearing on what happens on the host side of 459 * the PCMCIA controller. ISA interrupts are defined to be edge- 460 * triggered, and as this attachment is for ISA devices, the interrupt 461 * *must* be configured for edge-trigger. If you think you should 462 * change this to use IST_LEVEL, you are *wrong*. You should figure 463 * out what your real problem is and leave this code alone rather than 464 * breaking everyone else's systems. - mycroft 465 */ 466 if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL) 467 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 468 else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE) 469 ist = IST_PULSE; /* SEE COMMENT ABOVE */ 470 else 471 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 472 473 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq)) 474 return NULL; 475 476 h->ih_irq = irq; 477 if (h->flags & PCIC_FLAG_ENABLED) { 478 reg = pcic_read(h, PCIC_INTR); 479 reg &= ~PCIC_INTR_IRQ_MASK; 480 pcic_write(h, PCIC_INTR, reg | irq); 481 } 482 483 if ((ih = isa_intr_establish(ic, irq, ist, ipl, fct, arg)) == NULL) 484 return NULL; 485 486 printf("%s: card irq %d\n", device_xname(h->pcmcia), irq); 487 488 return ih; 489 } 490 491 void 492 pcic_isa_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 493 { 494 struct pcic_handle *h = (struct pcic_handle *) pch; 495 struct pcic_isa_softc *isc = device_private(h->ph_parent); 496 isa_chipset_tag_t ic = isc->sc_ic; 497 int reg; 498 499 isa_intr_disestablish(ic, ih); 500 501 h->ih_irq = 0; 502 if (h->flags & PCIC_FLAG_ENABLED) { 503 reg = pcic_read(h, PCIC_INTR); 504 reg &= ~PCIC_INTR_IRQ_MASK; 505 pcic_write(h, PCIC_INTR, reg); 506 } 507 } 508
Indexes created Sat Sep 20 22:09:52 GMT 2025