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i82365_isasubr.c revision 1.3.8.1
      1  1.3.8.1  wrstuden /*	$NetBSD: i82365_isasubr.c,v 1.3.8.1 1999/12/27 18:34:55 wrstuden Exp $	*/
      2      1.1  sommerfe 
      3      1.1  sommerfe #define	PCICISADEBUG
      4      1.1  sommerfe 
      5      1.1  sommerfe /*
      6      1.1  sommerfe  * Copyright (c) 1998 Bill Sommerfeld.  All rights reserved.
      7      1.1  sommerfe  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
      8      1.1  sommerfe  *
      9      1.1  sommerfe  * Redistribution and use in source and binary forms, with or without
     10      1.1  sommerfe  * modification, are permitted provided that the following conditions
     11      1.1  sommerfe  * are met:
     12      1.1  sommerfe  * 1. Redistributions of source code must retain the above copyright
     13      1.1  sommerfe  *    notice, this list of conditions and the following disclaimer.
     14      1.1  sommerfe  * 2. Redistributions in binary form must reproduce the above copyright
     15      1.1  sommerfe  *    notice, this list of conditions and the following disclaimer in the
     16      1.1  sommerfe  *    documentation and/or other materials provided with the distribution.
     17      1.1  sommerfe  * 3. All advertising materials mentioning features or use of this software
     18      1.1  sommerfe  *    must display the following acknowledgement:
     19      1.1  sommerfe  *	This product includes software developed by Marc Horowitz.
     20      1.1  sommerfe  * 4. The name of the author may not be used to endorse or promote products
     21      1.1  sommerfe  *    derived from this software without specific prior written permission.
     22      1.1  sommerfe  *
     23      1.1  sommerfe  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     24      1.1  sommerfe  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25      1.1  sommerfe  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26      1.1  sommerfe  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     27      1.1  sommerfe  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     28      1.1  sommerfe  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     29      1.1  sommerfe  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     30      1.1  sommerfe  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31      1.1  sommerfe  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     32      1.1  sommerfe  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33      1.1  sommerfe  */
     34      1.1  sommerfe 
     35      1.1  sommerfe 
     36      1.1  sommerfe #include <sys/types.h>
     37      1.1  sommerfe #include <sys/param.h>
     38      1.1  sommerfe #include <sys/systm.h>
     39      1.1  sommerfe #include <sys/device.h>
     40      1.1  sommerfe #include <sys/extent.h>
     41      1.1  sommerfe #include <sys/malloc.h>
     42      1.1  sommerfe 
     43      1.1  sommerfe #include <vm/vm.h>
     44      1.1  sommerfe 
     45      1.1  sommerfe #include <machine/bus.h>
     46      1.1  sommerfe #include <machine/intr.h>
     47      1.1  sommerfe 
     48      1.1  sommerfe #include <dev/isa/isareg.h>
     49      1.1  sommerfe #include <dev/isa/isavar.h>
     50      1.1  sommerfe 
     51      1.1  sommerfe #include <dev/pcmcia/pcmciareg.h>
     52      1.1  sommerfe #include <dev/pcmcia/pcmciavar.h>
     53      1.1  sommerfe #include <dev/pcmcia/pcmciachip.h>
     54      1.1  sommerfe 
     55      1.1  sommerfe #include <dev/ic/i82365reg.h>
     56      1.1  sommerfe #include <dev/ic/i82365var.h>
     57      1.1  sommerfe #include <dev/isa/i82365_isavar.h>
     58      1.1  sommerfe 
     59      1.1  sommerfe /*****************************************************************************
     60      1.1  sommerfe  * Configurable parameters.
     61      1.1  sommerfe  *****************************************************************************/
     62      1.1  sommerfe 
     63      1.1  sommerfe #include "opt_pcic_isa_alloc_iobase.h"
     64      1.1  sommerfe #include "opt_pcic_isa_alloc_iosize.h"
     65      1.1  sommerfe #include "opt_pcic_isa_intr_alloc_mask.h"
     66      1.1  sommerfe 
     67      1.1  sommerfe /*
     68      1.1  sommerfe  * Default I/O allocation range.  If both are set to non-zero, these
     69      1.1  sommerfe  * values will be used instead.  Otherwise, the code attempts to probe
     70      1.1  sommerfe  * the bus width.  Systems with 10 address bits should use 0x300 and 0xff.
     71      1.1  sommerfe  * Systems with 12 address bits (most) should use 0x400 and 0xbff.
     72      1.1  sommerfe  */
     73      1.1  sommerfe 
     74      1.1  sommerfe #ifndef PCIC_ISA_ALLOC_IOBASE
     75      1.1  sommerfe #define	PCIC_ISA_ALLOC_IOBASE		0
     76      1.1  sommerfe #endif
     77      1.1  sommerfe 
     78      1.1  sommerfe #ifndef PCIC_ISA_ALLOC_IOSIZE
     79      1.1  sommerfe #define	PCIC_ISA_ALLOC_IOSIZE		0
     80      1.1  sommerfe #endif
     81      1.1  sommerfe 
     82      1.1  sommerfe int	pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE;
     83      1.1  sommerfe int	pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE;
     84      1.1  sommerfe 
     85      1.1  sommerfe 
     86      1.1  sommerfe /*
     87      1.1  sommerfe  * Default IRQ allocation bitmask.  This defines the range of allowable
     88      1.1  sommerfe  * IRQs for PCMCIA slots.  Useful if order of probing would screw up other
     89      1.1  sommerfe  * devices, or if PCIC hardware/cards have trouble with certain interrupt
     90      1.1  sommerfe  * lines.
     91      1.1  sommerfe  *
     92      1.1  sommerfe  * We disable IRQ 10 by default, since some common laptops (namely, the
     93      1.1  sommerfe  * NEC Versa series) reserve IRQ 10 for the docking station SCSI interface.
     94      1.1  sommerfe  */
     95      1.1  sommerfe 
     96      1.1  sommerfe #ifndef PCIC_ISA_INTR_ALLOC_MASK
     97      1.1  sommerfe #define	PCIC_ISA_INTR_ALLOC_MASK	0xfbff
     98      1.1  sommerfe #endif
     99      1.1  sommerfe 
    100      1.1  sommerfe int	pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK;
    101      1.1  sommerfe 
    102      1.1  sommerfe /*****************************************************************************
    103      1.1  sommerfe  * End of configurable parameters.
    104      1.1  sommerfe  *****************************************************************************/
    105      1.1  sommerfe 
    106      1.1  sommerfe #ifdef PCICISADEBUG
    107      1.1  sommerfe int	pcicsubr_debug = 0 /* XXX */ ;
    108      1.1  sommerfe #define	DPRINTF(arg) if (pcicsubr_debug) printf arg;
    109      1.1  sommerfe #else
    110      1.1  sommerfe #define	DPRINTF(arg)
    111      1.1  sommerfe #endif
    112      1.1  sommerfe 
    113      1.1  sommerfe void pcic_isa_bus_width_probe (sc, iot, ioh, base, length)
    114      1.1  sommerfe 	struct pcic_softc *sc;
    115      1.1  sommerfe 	bus_space_tag_t iot;
    116      1.1  sommerfe 	bus_space_handle_t ioh;
    117      1.1  sommerfe 	bus_addr_t base;
    118      1.1  sommerfe 	u_int32_t length;
    119      1.1  sommerfe {
    120      1.1  sommerfe 	bus_space_handle_t ioh_high;
    121      1.1  sommerfe 	int i, iobuswidth, tmp1, tmp2;
    122      1.1  sommerfe 
    123      1.1  sommerfe 	/*
    124      1.1  sommerfe 	 * figure out how wide the isa bus is.  Do this by checking if the
    125      1.1  sommerfe 	 * pcic controller is mirrored 0x400 above where we expect it to be.
    126      1.1  sommerfe 	 */
    127      1.1  sommerfe 
    128      1.1  sommerfe 	iobuswidth = 12;
    129      1.1  sommerfe 
    130      1.1  sommerfe 	/* Map i/o space. */
    131      1.1  sommerfe 	if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) {
    132      1.1  sommerfe 		printf("%s: can't map high i/o space\n", sc->dev.dv_xname);
    133      1.1  sommerfe 		return;
    134      1.1  sommerfe 	}
    135      1.1  sommerfe 
    136      1.1  sommerfe 	for (i = 0; i < PCIC_NSLOTS; i++) {
    137      1.1  sommerfe 		if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) {
    138      1.1  sommerfe 			/*
    139      1.1  sommerfe 			 * read the ident flags from the normal space and
    140      1.1  sommerfe 			 * from the mirror, and compare them
    141      1.1  sommerfe 			 */
    142      1.1  sommerfe 
    143      1.1  sommerfe 			bus_space_write_1(iot, ioh, PCIC_REG_INDEX,
    144      1.1  sommerfe 			    sc->handle[i].sock + PCIC_IDENT);
    145      1.1  sommerfe 			tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
    146      1.1  sommerfe 
    147      1.1  sommerfe 			bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX,
    148      1.1  sommerfe 			    sc->handle[i].sock + PCIC_IDENT);
    149      1.1  sommerfe 			tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA);
    150      1.1  sommerfe 
    151      1.1  sommerfe 			if (tmp1 == tmp2)
    152      1.1  sommerfe 				iobuswidth = 10;
    153      1.1  sommerfe 		}
    154      1.1  sommerfe 	}
    155      1.1  sommerfe 
    156      1.1  sommerfe 	bus_space_free(iot, ioh_high, length);
    157      1.1  sommerfe 
    158      1.1  sommerfe 	/*
    159      1.1  sommerfe 	 * XXX mycroft recommends I/O space range 0x400-0xfff .  I should put
    160      1.1  sommerfe 	 * this in a header somewhere
    161      1.1  sommerfe 	 */
    162      1.1  sommerfe 
    163      1.1  sommerfe 	/*
    164      1.1  sommerfe 	 * XXX some hardware doesn't seem to grok addresses in 0x400 range--
    165      1.1  sommerfe 	 * apparently missing a bit or more of address lines. (e.g.
    166      1.1  sommerfe 	 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI
    167      1.1  sommerfe 	 * TravelMate 5000--not clear which is at fault)
    168      1.1  sommerfe 	 *
    169      1.1  sommerfe 	 * Add a kludge to detect 10 bit wide buses and deal with them,
    170      1.1  sommerfe 	 * and also a config file option to override the probe.
    171      1.1  sommerfe 	 */
    172      1.1  sommerfe 
    173      1.1  sommerfe 	if (iobuswidth == 10) {
    174      1.1  sommerfe 		sc->iobase = 0x300;
    175      1.1  sommerfe 		sc->iosize = 0x0ff;
    176      1.1  sommerfe 	} else {
    177      1.1  sommerfe #if 0
    178      1.1  sommerfe 		/*
    179      1.1  sommerfe 		 * This is what we'd like to use, but...
    180      1.1  sommerfe 		 */
    181      1.1  sommerfe 		sc->iobase = 0x400;
    182      1.1  sommerfe 		sc->iosize = 0xbff;
    183      1.1  sommerfe #else
    184      1.1  sommerfe 		/*
    185      1.1  sommerfe 		 * ...the above bus width probe doesn't always work.
    186      1.1  sommerfe 		 * So, experimentation has shown the following range
    187      1.1  sommerfe 		 * to not lose on systems that 0x300-0x3ff loses on
    188      1.1  sommerfe 		 * (e.g. the NEC Versa 6030X).
    189      1.1  sommerfe 		 */
    190      1.1  sommerfe 		sc->iobase = 0x330;
    191      1.1  sommerfe 		sc->iosize = 0x0cf;
    192      1.1  sommerfe #endif
    193      1.1  sommerfe 	}
    194      1.1  sommerfe 
    195      1.1  sommerfe 	DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n",
    196      1.1  sommerfe 	    sc->dev.dv_xname, (long) sc->iobase,
    197      1.1  sommerfe 
    198      1.1  sommerfe 	    (long) sc->iobase + sc->iosize));
    199      1.1  sommerfe 
    200      1.1  sommerfe 	if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) {
    201      1.1  sommerfe 		sc->iobase = pcic_isa_alloc_iobase;
    202      1.1  sommerfe 		sc->iosize = pcic_isa_alloc_iosize;
    203      1.1  sommerfe 
    204      1.1  sommerfe 		DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx "
    205      1.1  sommerfe 		    "(config override)\n", sc->dev.dv_xname, (long) sc->iobase,
    206      1.1  sommerfe 		    (long) sc->iobase + sc->iosize));
    207      1.1  sommerfe 	}
    208      1.1  sommerfe }
    209      1.1  sommerfe 
    210      1.1  sommerfe 
    211      1.1  sommerfe void *
    212      1.1  sommerfe pcic_isa_chip_intr_establish(pch, pf, ipl, fct, arg)
    213      1.1  sommerfe 	pcmcia_chipset_handle_t pch;
    214      1.1  sommerfe 	struct pcmcia_function *pf;
    215      1.1  sommerfe 	int ipl;
    216      1.1  sommerfe 	int (*fct) __P((void *));
    217      1.1  sommerfe 	void *arg;
    218      1.1  sommerfe {
    219      1.1  sommerfe 	struct pcic_handle *h = (struct pcic_handle *) pch;
    220  1.3.8.1  wrstuden 	struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
    221  1.3.8.1  wrstuden 	isa_chipset_tag_t ic = sc->intr_est;
    222      1.1  sommerfe 	int irq, ist;
    223      1.1  sommerfe 	void *ih;
    224      1.1  sommerfe 	int reg;
    225      1.1  sommerfe 
    226      1.1  sommerfe 	if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)
    227      1.1  sommerfe 		ist = IST_LEVEL;
    228      1.1  sommerfe 	else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE)
    229      1.1  sommerfe 		ist = IST_PULSE;
    230      1.1  sommerfe 	else
    231      1.2   mycroft 		ist = IST_EDGE;
    232      1.1  sommerfe 
    233      1.1  sommerfe 	if (isa_intr_alloc(ic,
    234      1.1  sommerfe 	    PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask, ist, &irq))
    235      1.1  sommerfe 		return (NULL);
    236      1.1  sommerfe 	if ((ih = isa_intr_establish(ic, irq, ist, ipl,
    237      1.1  sommerfe 	    fct, arg)) == NULL)
    238      1.1  sommerfe 		return (NULL);
    239      1.1  sommerfe 
    240      1.1  sommerfe 	reg = pcic_read(h, PCIC_INTR);
    241      1.3   mycroft 	reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
    242      1.3   mycroft 	reg |= irq;
    243      1.1  sommerfe 	pcic_write(h, PCIC_INTR, reg);
    244      1.1  sommerfe 
    245      1.1  sommerfe 	h->ih_irq = irq;
    246      1.1  sommerfe 
    247      1.1  sommerfe 	printf("%s: card irq %d\n", h->pcmcia->dv_xname, irq);
    248      1.1  sommerfe 
    249      1.1  sommerfe 	return (ih);
    250      1.1  sommerfe }
    251      1.1  sommerfe 
    252      1.1  sommerfe void
    253      1.1  sommerfe pcic_isa_chip_intr_disestablish(pch, ih)
    254      1.1  sommerfe 	pcmcia_chipset_handle_t pch;
    255      1.1  sommerfe 	void *ih;
    256      1.1  sommerfe {
    257      1.1  sommerfe 	struct pcic_handle *h = (struct pcic_handle *) pch;
    258  1.3.8.1  wrstuden 	struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
    259  1.3.8.1  wrstuden 	isa_chipset_tag_t ic = sc->intr_est;
    260      1.1  sommerfe 	int reg;
    261      1.1  sommerfe 
    262      1.1  sommerfe 	h->ih_irq = 0;
    263      1.1  sommerfe 
    264      1.1  sommerfe 	reg = pcic_read(h, PCIC_INTR);
    265      1.1  sommerfe 	reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
    266      1.1  sommerfe 	pcic_write(h, PCIC_INTR, reg);
    267      1.1  sommerfe 
    268      1.1  sommerfe 	isa_intr_disestablish(ic, ih);
    269      1.1  sommerfe }
    270