1 /* $NetBSD: if_ntwoc_isareg.h,v 1.1 2000/01/04 06:29:21 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1995 John Hay. 5 * Copyright (c) 1996 SDL Communications, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $Id: if_ntwoc_isareg.h,v 1.1 2000/01/04 06:29:21 chopps Exp $ 33 */ 34 #ifndef _IF_NTWOC_ISAREG_H_ 35 #define _IF_NTWOC_ISAREG_H_ 36 37 #define NTWOC_ISA_NCHAN 2 /* A HD64570 chip have 2 channels */ 38 39 #define NTWOC_BUF_SIZ 512 40 #define NTWOC_TX_BLOCKS 2 /* Sepperate sets of tx buffers */ 41 42 #define NTWOC_CRD_N2 1 43 44 /* 45 * RISCom/N2 ISA card. 46 */ 47 #define NTWOC_SRC_IOPORT_SIZE 0x08 /* also uses 0x8400 -> 0xAxxx */ 48 49 /* config flags are as follows */ 50 /* 51 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 52 * +-------------+ +-----+ +-----+ + +---+ +-+ + +---+ +-+ + 53 * tmc tdiv rdiv e1 rxs1 ts1 e0 rxs0 txs0 nports - 1 54 */ 55 #define NTWOC_FLAGS_NPORT_MASK 0x00000001 /* nports - 1 */ 56 #define NTWOC_FLAGS_CLK0_MASK 0x000000fc /* port 0 clock info mask */ 57 #define NTWOC_FLAGS_CLK1_MASK 0x0000fc00 /* port 1 clock info mask */ 58 #define NTWOC_FLAGS_RXDIV_MASK 0x000F0000 /* rx div mask */ 59 #define NTWOC_FLAGS_TXDIV_MASK 0x00F00000 /* tx div mask */ 60 #define NTWOC_FLAGS_TMC_MASK 0xFF000000 /* tmc port 0 mask */ 61 62 #define NTWOC_FLAGS_CLK1_SHIFT 8 63 64 /* these are used after you shift down to the clock byte for the resp. port */ 65 #define NTWOC_FLAGS_TXS_SHIFT 2 66 #define NTWOC_FLAGS_TXS_MASK 0x0000000c /* port 0 tx clk source mask */ 67 #define NTWOC_FLAGS_TXS_LINE 0 /* use the line clock */ 68 #define NTWOC_FLAGS_TXS_INTERNAL 1 /* use the internal clock */ 69 #define NTWOC_FLAGS_TXS_RXCLOCK 2 /* use the receive clock */ 70 71 #define NTWOC_FLAGS_RXS_SHIFT 4 72 #define NTWOC_FLAGS_RXS_MASK 0x00000070 /* port 0 rx clk source mask */ 73 #define NTWOC_FLAGS_RXS_LINE 0 /* use the line clock */ 74 #define NTWOC_FLAGS_RXS_LINE_SN 1 /* use line with noise supp. */ 75 #define NTWOC_FLAGS_RXS_INTERNAL 2 /* use internal clock */ 76 #define NTWOC_FLAGS_RXS_ADPLL_OUT 3 /* use brg out for adpll clk */ 77 #define NTWOC_FLAGS_RXS_ADPLL_IN 4 /* use line in for adpll clk */ 78 79 #define NTWOC_FLAGS_ECLOCK_SHIFT 7 /* generate external clock */ 80 #define NTWOC_FLAGS_ECLOCK_MASK 0x00000080 /* port 0 ext clk gen mask */ 81 82 /* these are used on the flags directly */ 83 #define NTWOC_FLAGS_RXDIV_SHIFT 16 84 #define NTWOC_FLAGS_TXDIV_SHIFT 20 85 #define NTWOC_FLAGS_TMC_SHIFT 24 86 87 88 #define NTWOC_PCR 0x00 /* RW, PC Control Register */ 89 #define NTWOC_BAR 0x02 /* RW, Base Address Register */ 90 #define NTWOC_PSR 0x04 /* RW, Page Scan Register */ 91 #define NTWOC_MCR 0x06 /* RW, Modem Control Register */ 92 93 #define NTWOC_PCR_SCARUN 0x01 /* !Reset */ 94 #define NTWOC_PCR_EN_VPM 0x02 /* Running above 1M */ 95 #define NTWOC_PCR_MEM_WIN 0x04 /* Open memory window */ 96 #define NTWOC_PCR_ISA16 0x08 /* 16 bit ISA mode */ 97 #define NTWOC_PCR_16M_SEL 0xF0 /* A20-A23 Addresses */ 98 99 #define NTWOC_PSR_PG_SEL 0x1F /* Page 0 - 31 select */ 100 #define NTWOC_PG_MSK 0x1F 101 #define NTWOC_PSR_WIN_SIZ 0x60 /* Window size select */ 102 #define NTWOC_PSR_WIN_16K 0x00 103 #define NTWOC_PSR_WIN_32K 0x20 104 #define NTWOC_PSR_WIN_64K 0x40 105 #define NTWOC_PSR_WIN_128K 0x60 106 #define NTWOC_PSR_EN_SCA_DMA 0x80 /* Enable the SCA DMA */ 107 108 #define NTWOC_MCR_DTR0 0x01 /* Deactivate DTR0 */ 109 #define NTWOC_MCR_DTR1 0x02 /* Deactivate DTR1 */ 110 #define NTWOC_MCR_DSR0 0x04 /* DSR0 Status */ 111 #define NTWOC_MCR_DSR1 0x08 /* DSR1 Status */ 112 #define NTWOC_MCR_TE0 0x10 /* Enable RS422 TXD */ 113 #define NTWOC_MCR_TE1 0x20 /* Enable RS422 TXD */ 114 #define NTWOC_MCR_ETC0 0x40 /* Enable Ext Clock out */ 115 #define NTWOC_MCR_ETC1 0x80 /* Enable Ext Clock out */ 116 117 #endif /* _IF_NTWOC_ISAREG_H_ */ 118
Indexes created Mon Sep 22 13:09:51 GMT 2025