1 /* $NetBSD: mvpexreg.h,v 1.3 2019/12/27 09:32:10 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _MVPEXREG_H_ 29 #define _MVPEXREG_H_ 30 31 32 /* 33 * PCI Express Interface Registers 34 */ 35 #define MVPEX_SIZE 0x2000 36 37 38 /* PCI Express BAR Control Registers */ 39 #define MVPEX_BAR1C 0x1804 /* BAR1 Control */ 40 #define MVPEX_BAR2C 0x1808 /* BAR2 Control */ 41 #define MVPEX_BARC_BAREN (1 << 0) 42 #define MVPEX_BARC_BARSIZE_MASK 0xffff0000 43 #define MVPEX_BARC_BARSIZE(s) (((s) - 1) & MVPEX_BARC_BARSIZE_MASK) 44 #define MVPEX_ERBARC 0x180c /* Expression ROM BAR Control */ 45 #define MVPEX_ERBARC_EXPROMEN (1 << 0) 46 #define MVPEX_ERBARC_EXPROMSZ_05M (0 << 19) 47 #define MVPEX_ERBARC_EXPROMSZ_1M (1 << 19) 48 #define MVPEX_ERBARC_EXPROMSZ_2M (2 << 19) 49 #define MVPEX_ERBARC_EXPROMSZ_4M (3 << 19) 50 /* PCI Express Configuration Requests Generation Registers */ 51 #define MVPEX_CA 0x18f8 /* Configuration Address */ 52 #define MVPEX_CA_CONFIGEN (1 << 31) 53 #define MVPEX_CD 0x18fc /* Configuration Data */ 54 /* PCI Express Interrupt Registers */ 55 #define MVPEX_IC 0x1900 /* Interrupt Cause */ 56 #define MVPEX_IM 0x1910 /* Interrupt Mask */ 57 #define MVPEX_I_MDIS (1 << 1) 58 #define MVPEX_I_ERRWRTOREG (1 << 3) 59 #define MVPEX_I_HITDFLTWINERR (1 << 4) /* Hit Default Win Err */ 60 #define MVPEX_I_CORERRDET (1 << 8) /* Correctable Err Detect */ 61 #define MVPEX_I_NFERRDET (1 << 9) /* Non-Fatal Err Detect */ 62 #define MVPEX_I_FERRDET (1 << 10) /* Fatal Err Detect */ 63 #define MVPEX_I_DSTATECHANGE (1 << 11) /* Dstate Change */ 64 #define MVPEX_I_BIST (1 << 12) /* PCI-e BIST activated */ 65 #define MVPEX_I_RCVERRFATAL (1 << 16) /* Rcv ERR_FATAL msg */ 66 #define MVPEX_I_RCVERRNONFATAL (1 << 17) /* Rcv ERR_NONFATAL msg */ 67 #define MVPEX_I_RCVERRCOR (1 << 18) /* Rcv ERR_COR msg */ 68 #define MVPEX_I_RCVCRS (1 << 19)/* Rcv CRS completion status */ 69 #define MVPEX_I_PEXSLVHOT (1 << 20) /* Rcv Hot Reset */ 70 #define MVPEX_I_PEXSLVDISLINK (1 << 21) /* Slave Disable Link */ 71 #define MVPEX_I_PEXSLVLB (1 << 22) /* Slave Loopback */ 72 #define MVPEX_I_PEXLINKFAIL (1 << 23) /* Link Failure */ 73 #define MVPEX_I_PIN(p) (1 << (((p) - 1) + 24)) 74 /* PCI Express Address Window Control Registers */ 75 #define MVPEX_NWINDOW 6 /* Window 4 and 5 has Remap (High) Register */ 76 #define MVPEX_W_OFFSET(w) ((w < 4) ? ((w) << 4) : ((w - 4) << 5) + 0x40) 77 #define MVPEX_WC(x) (0x1820 + MVPEX_W_OFFSET(x)) /* Win Ctrl */ 78 #define MVPEX_WC_WINEN (1 << 0) 79 #define MVPEX_WC_BARMAP_BAR1 (0 << 1) 80 #define MVPEX_WC_BARMAP_BAR2 (1 << 1) 81 #define MVPEX_WC_TARGET(t) (((t) & 0xf) << 4) 82 #define MVPEX_WC_ATTR(a) (((a) & 0xff) << 8) 83 #define MVPEX_WC_SIZE(s) (((s) - 1) & 0xffff0000) 84 #define MVPEX_WB(x) (0x1824 + MVPEX_W_OFFSET(x)) /* Win Base */ 85 #define MVPEX_WB_BASE(b) ((b) & 0xffff0000) 86 #define MVPEX_WR(x) (0x182c + MVPEX_W_OFFSET(x)) /* Win Remap */ 87 #define MVPEX_WR_REMAP_REMAPEN (1 << 0) 88 #define MVPEX_WR_REMAP(a) ((a) & 0xffff0000) 89 #define MVPEX_DWC 0x18b0 /* Default Window Control */ 90 #define MVPEX_EROMWC 0x18c0 /* Expression ROM Win Control */ 91 #define MVPEX_EROMWR 0x18c4 /* Expression ROM Win Remap */ 92 /* PCI Express Control and Status Registers */ 93 #define MVPEX_CTRL 0x1a00 /* Control */ 94 #define MVPEX_CTRL_CONFROOTCOMPLEX (1 << 1) 95 #define MVPEX_CTRL_CFGMAPTOMEMEN (1 << 2) 96 #define MVPEX_CTRL_CONFMSTRHOTRESET (1 << 24) /* Master Hot-Reset */ 97 #define MVPEX_CTRL_CONFMSTRLB (1 << 26) /* Master Loopback */ 98 #define MVPEX_CTRL_CONFMSTRDISSCRMB (1 << 27)/* Master Disable Scrambling */ 99 #define MVPEX_STAT 0x1a04 /* Status */ 100 #define MVPEX_STAT_DLDOWN (1 << 0) 101 #define MVPEX_STAT_PEXBUSNUM(s) (((s) & 0x00ff00) >> 8) 102 #define MVPEX_STAT_PEXDEVNUM(s) (((s) & 0x1f0000) >> 16) 103 #define MVPEX_STAT_PEXSLVHOTRESET (1 << 24) /* Slave Hot Reset (RO) */ 104 #define MVPEX_STAT_PEXSLVDISLINK (1 << 25) /* Slave Disable Link (RO) */ 105 #define MVPEX_STAT_PEXSLVLB (1 << 26) /* Slave Loopback (RO) */ 106 #define MVPEX_STAT_PEXSLVDISSCRMB (1 << 27) /* Slv Dis Scrambling (RO) */ 107 #define MVPEX_CT 0x1a10 /* Completion Timeout */ 108 #define MVPEX_FC 0x1a20 /* Flow Control */ 109 #define MVPEX_AT 0x1a40 /* Acknowledge Timers (1X) */ 110 #define MVPEX_TLC 0x1ab0 /* TL Control */ 111 /* PCI Express Configuration Header Registers */ 112 /* see at dev/pci/pcireg.h from 0x00 to 0x3c. */ 113 #define MVPEX_BAR0INTERNAL 0x0010 /* BAR0 Internal */ 114 #define MVPEX_BAR0INTERNAL_MASK 0xfff00000 115 #define MVPEX_BAR0INTERNALH 0x0014 /* BAR0 Internal (High) */ 116 #define MVPEX_BAR1 0x0018 /* BAR1 */ 117 #define MVPEX_BAR1H 0x001c /* BAR1 */ 118 #define MVPEX_BAR2 0x0020 /* BAR2 */ 119 #define MVPEX_BAR2H 0x0024 /* BAR2 */ 120 #define MVPEX_BAR_MASK 0xffff0000 121 #define MVPEX_PMCH 0x0040 /* Power Management Cap Header */ 122 #define MVPEX_PMCSH 0x0044 /* Control and Status */ 123 #define MVPEX_MSIMC 0x0050 /* MSI Message Control */ 124 #define MVPEX_MSIMA 0x0054 /* MSI Message Address */ 125 #define MVPEX_MSIMAH 0x0058 /* MSI Message Address (High) */ 126 #define MVPEX_MSIMD 0x005c /* MSI Message Data */ 127 #define MVPEX_CAP 0x0060 /* Capability */ 128 #define MVPEX_DC 0x0064 /* Device Capabilities */ 129 #define MVPEX_DCS 0x0068 /* Device Control Status */ 130 #define MVPEX_LC 0x006c /* Link Capabilities */ 131 #define MVPEX_LCS 0x0070 /* Link Control Status */ 132 #define MVPEX_AERH 0x0100 /* Advanced Error Report Header */ 133 #define MVPEX_UESTAT 0x0104 /* Uncorrectable Error Status */ 134 #define MVPEX_UEM 0x0108 /* Uncorrectable Error Mask */ 135 #define MVPEX_UESEVERITY 0x010c /* Uncorrectable Error Serverity */ 136 #define MVPEX_CES 0x0110 /* Correctable Error Status */ 137 #define MVPEX_CEM 0x0114 /* Correctable Error Mask */ 138 #define MVPEX_AECC 0x0118 /* Advanced Error Cap and Ctrl */ 139 #define MVPEX_HLDWORD1 0x011c /* Header Log First DWORD */ 140 #define MVPEX_HLDWORD2 0x0120 /* Header Log Second DWORD */ 141 #define MVPEX_HLDWORD3 0x0124 /* Header Log Third DWORD */ 142 #define MVPEX_HLDWORD4 0x0128 /* Header Log Fourth DWORD */ 143 144 #endif /* _MVPEXREG_H_ */ 145
Indexes created Sat Sep 20 22:09:52 GMT 2025