1 /* $NetBSD: ipgphyreg.h,v 1.3 2019/11/21 03:04:21 msaitoh Exp $ */ 2 /* $OpenBSD: ipgphyreg.h,v 1.3 2015/07/19 06:28:12 yuo Exp $ */ 3 4 /*- 5 * Copyright (c) 2006, Pyun YongHyeon 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _DEV_MII_IPGPHYREG_H_ 33 #define _DEV_MII_IPGPHYREG_H_ 34 35 /* 36 * Registers for the IC Plus IPGA internal PHY. 37 */ 38 39 /* PHY specific control & status register. IP1001 only. */ 40 #define IPGPHY_SCSR 0x10 41 #define IPGPHY_SCSR_RXPHASE_SEL 0x0001 42 #define IPGPHY_SCSR_TXPHASE_SEL 0x0002 43 #define IPGPHY_SCSR_REPEATOR_MODE 0x0004 44 #define IPGPHY_SCSR_RESERVED1_DEF 0x0008 45 #define IPGPHY_SCSR_RXCLK_DRV_MASK 0x0060 46 #define IPGPHY_SCSR_RXCLK_DRV_DEF 0x0040 47 #define IPGPHY_SCSR_RXD_DRV_MASK 0x0180 48 #define IPGPHY_SCSR_RXD_DRV_DEF 0x0100 49 #define IPGPHY_SCSR_JABBER_ENB 0x0200 50 #define IPGPHY_SCSR_HEART_BEAT_ENB 0x0400 51 #define IPGPHY_SCSR_DOWNSHIFT_ENB 0x0800 52 #define IPGPHY_SCSR_RESERVED2_DEF 0x1000 53 #define IPGPHY_SCSR_LED_DRV_4MA 0x0000 54 #define IPGPHY_SCSR_LED_DRV_8MA 0x2000 55 #define IPGPHY_SCSR_LED_MODE_MASK 0xC000 56 #define IPGPHY_SCSR_LED_MODE_DEF 0x0000 57 58 /* PHY link status register. IP1001 only. */ 59 #define IPGPHY_LSR 0x11 60 #define IPGPHY_LSR_JABBER_DET 0x0200 61 #define IPGPHY_LSR_APS_SLEEP 0x0400 62 #define IPGPHY_LSR_MDIX 0x0800 63 #define IPGPHY_LSR_FULL_DUPLEX 0x1000 64 #define IPGPHY_LSR_SPEED_10 0x0000 65 #define IPGPHY_LSR_SPEED_100 0x2000 66 #define IPGPHY_LSR_SPEED_1000 0x4000 67 #define IPGPHY_LSR_SPEED_MASK 0x6000 68 #define IPGPHY_LSR_LINKUP 0x8000 69 70 /* PHY specific control register 2. IP1001 only. */ 71 #define IPGPHY_SCR 0x14 72 #define IPGPHY_SCR_SEW_RATE_MASK 0x0003 73 #define IPGPHY_SCR_SEW_RATE_DEF 0x0003 74 #define IPGPHY_SCR_AUTO_XOVER 0x0004 75 #define IPGPHY_SCR_SPEED_10_100_ENB 0x0040 76 #define IPGPHY_SCR_FIFO_LATENCY_2 0x0000 77 #define IPGPHY_SCR_FIFO_LATENCY_3 0x0080 78 #define IPGPHY_SCR_FIFO_LATENCY_4 0x0100 79 #define IPGPHY_SCR_FIFO_LATENCY_5 0x0180 80 #define IPGPHY_SCR_MDIX_ENB 0x0200 81 #define IPGPHY_SCR_RESERVED_DEF 0x0400 82 #define IPGPHY_SCR_APS_ON 0x0800 83 84 #endif /* _DEV_MII_IPGPHYREG_H_ */ 85
Indexes created Sun Sep 28 12:09:53 GMT 2025