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ipgphyreg.h revision 1.2 
      1 /*	$OpenBSD: ipgphyreg.h,v 1.3 2015/07/19 06:28:12 yuo Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2006, Pyun YongHyeon
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice unmodified, this list of conditions, and the following
     12  *    disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  * SUCH DAMAGE.
     28  *
     29  */
     30 
     31 #ifndef _DEV_MII_IPGPHYREG_H_
     32 #define _DEV_MII_IPGPHYREG_H_
     33 
     34 /*
     35  * Registers for the IC Plus IPGA internal PHY.
     36  */
     37 
     38 /* PHY specific control & status register. IP1001 only. */
     39 #define IPGPHY_SCSR		0x10
     40 #define IPGPHY_SCSR_RXPHASE_SEL		0x0001
     41 #define IPGPHY_SCSR_TXPHASE_SEL		0x0002
     42 #define IPGPHY_SCSR_REPEATOR_MODE	0x0004
     43 #define IPGPHY_SCSR_RESERVED1_DEF	0x0008
     44 #define IPGPHY_SCSR_RXCLK_DRV_MASK	0x0060
     45 #define IPGPHY_SCSR_RXCLK_DRV_DEF	0x0040
     46 #define IPGPHY_SCSR_RXD_DRV_MASK	0x0180
     47 #define IPGPHY_SCSR_RXD_DRV_DEF		0x0100
     48 #define IPGPHY_SCSR_JABBER_ENB		0x0200
     49 #define IPGPHY_SCSR_HEART_BEAT_ENB	0x0400
     50 #define IPGPHY_SCSR_DOWNSHIFT_ENB	0x0800
     51 #define IPGPHY_SCSR_RESERVED2_DEF	0x1000
     52 #define IPGPHY_SCSR_LED_DRV_4MA		0x0000
     53 #define IPGPHY_SCSR_LED_DRV_8MA		0x2000
     54 #define IPGPHY_SCSR_LED_MODE_MASK	0xC000
     55 #define IPGPHY_SCSR_LED_MODE_DEF	0x0000
     56 
     57 /* PHY link status register. IP1001 only. */
     58 #define IPGPHY_LSR		0x11
     59 #define IPGPHY_LSR_JABBER_DET		0x0200
     60 #define IPGPHY_LSR_APS_SLEEP		0x0400
     61 #define IPGPHY_LSR_MDIX			0x0800
     62 #define IPGPHY_LSR_FULL_DUPLEX		0x1000
     63 #define IPGPHY_LSR_SPEED_10		0x0000
     64 #define IPGPHY_LSR_SPEED_100		0x2000
     65 #define IPGPHY_LSR_SPEED_1000		0x4000
     66 #define IPGPHY_LSR_SPEED_MASK		0x6000
     67 #define IPGPHY_LSR_LINKUP		0x8000
     68 
     69 /* PHY specific control register 2. IP1001 only. */
     70 #define IPGPHY_SCR		0x14
     71 #define IPGPHY_SCR_SEW_RATE_MASK	0x0003
     72 #define IPGPHY_SCR_SEW_RATE_DEF		0x0003
     73 #define IPGPHY_SCR_AUTO_XOVER		0x0004
     74 #define IPGPHY_SCR_SPEED_10_100_ENB	0x0040
     75 #define IPGPHY_SCR_FIFO_LATENCY_2	0x0000
     76 #define IPGPHY_SCR_FIFO_LATENCY_3	0x0080
     77 #define IPGPHY_SCR_FIFO_LATENCY_4	0x0100
     78 #define IPGPHY_SCR_FIFO_LATENCY_5	0x0180
     79 #define IPGPHY_SCR_MDIX_ENB		0x0200
     80 #define IPGPHY_SCR_RESERVED_DEF		0x0400
     81 #define IPGPHY_SCR_APS_ON		0x0800
     82 
     83 #endif /* _DEV_MII_IPGPHYREG_H_ */
     84