1 /* $NetBSD: jmphyreg.h,v 1.1 2019/10/30 12:06:26 msaitoh Exp $ */ 2 /* $OpenBSD: jmphyreg.h,v 1.1 2008/09/26 10:35:15 jsg Exp $ */ 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/mii/jmphyreg.h,v 1.1 2008/05/27 01:16:40 yongari Exp $ 30 * $DragonFly: src/sys/dev/netif/mii_layer/jmphyreg.h,v 1.2 2008/09/13 04:04:39 sephe Exp $ 31 */ 32 33 #ifndef _DEV_MII_JMPHYREG_H_ 34 #define _DEV_MII_JMPHYREG_H_ 35 36 /* 37 * Registers for the JMicron JMC250 Gigabit PHY. 38 */ 39 40 /* PHY specific status register. */ 41 #define JMPHY_SSR 0x11 42 #define JMPHY_SSR_SPEED_1000 0x8000 43 #define JMPHY_SSR_SPEED_100 0x4000 44 #define JMPHY_SSR_SPEED_10 0x0000 45 #define JMPHY_SSR_SPEED_MASK 0xC000 46 #define JMPHY_SSR_DUPLEX 0x2000 47 #define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800 48 #define JMPHY_SSR_LINK_UP 0x0400 49 #define JMPHY_SSR_MDI_XOVER 0x0040 50 #define JMPHY_SSR_INV_POLARITY 0x0002 51 52 /* PHY specific cable length status register. */ 53 #define JMPHY_SCL 0x17 54 #define JMPHY_SCL_CHAN_D_MASK 0xF000 55 #define JMPHY_SCL_CHAN_C_MASK 0x0F00 56 #define JMPHY_SCL_CHAN_B_MASK 0x00F0 57 #define JMPHY_SCL_CHAN_A_MASK 0x000F 58 #define JMPHY_SCL_LEN_35 0 59 #define JMPHY_SCL_LEN_40 1 60 #define JMPHY_SCL_LEN_50 2 61 #define JMPHY_SCL_LEN_60 3 62 #define JMPHY_SCL_LEN_70 4 63 #define JMPHY_SCL_LEN_80 5 64 #define JMPHY_SCL_LEN_90 6 65 #define JMPHY_SCL_LEN_100 7 66 #define JMPHY_SCL_LEN_110 8 67 #define JMPHY_SCL_LEN_120 9 68 #define JMPHY_SCL_LEN_130 10 69 #define JMPHY_SCL_LEN_140 11 70 #define JMPHY_SCL_LEN_150 12 71 #define JMPHY_SCL_LEN_160 13 72 #define JMPHY_SCL_LEN_170 14 73 #define JMPHY_SCL_RSVD 15 74 75 /* PHY specific LED control register 1. */ 76 #define JMPHY_LED_CTL1 0x18 77 #define JMPHY_LED_BLINK_42MS 0x0000 78 #define JMPHY_LED_BLINK_84MS 0x2000 79 #define JMPHY_LED_BLINK_170MS 0x4000 80 #define JMPHY_LED_BLINK_340MS 0x6000 81 #define JMPHY_LED_BLINK_670MS 0x8000 82 #define JMPHY_LED_BLINK_MASK 0xE000 83 #define JMPHY_LED_FLP_GAP_MASK 0x1F00 84 #define JMPHY_LED_FLP_GAP_DEFULT 0x1000 85 #define JMPHY_LED2_POLARITY_MASK 0x0030 86 #define JMPHY_LED1_POLARITY_MASK 0x000C 87 #define JMPHY_LED0_POLARITY_MASK 0x0003 88 #define JMPHY_LED_ON_LO_OFF_HI 0 89 #define JMPHY_LED_ON_HI_OFF_HI 1 90 #define JMPHY_LED_ON_LO_OFF_TS 2 91 #define JMPHY_LED_ON_HI_OFF_TS 3 92 93 /* PHY specific LED control register 2. */ 94 #define JMPHY_LED_CTL2 0x19 95 #define JMPHY_LED_NO_STRETCH 0x0000 96 #define JMPHY_LED_STRETCH_42MS 0x2000 97 #define JMPHY_LED_STRETCH_84MS 0x4000 98 #define JMPHY_LED_STRETCH_170MS 0x6000 99 #define JMPHY_LED_STRETCH_340MS 0x8000 100 #define JMPHY_LED_STRETCH_670MS 0xB000 101 #define JMPHY_LED_STRETCH_1300MS 0xC000 102 #define JMPHY_LED_STRETCH_2700MS 0xE000 103 #define JMPHY_LED2_MODE_MASK 0x0F00 104 #define JMPHY_LED1_MODE_MASK 0x00F0 105 #define JMPHY_LED0_MODE_MASK 0x000F 106 107 /* PHY specific test mode control register. */ 108 #define JMPHY_TMCTL 0x1A 109 #define JMPHY_TMCTL_SLEEP_ENB 0x1000 110 111 /* PHY specific configuration */ 112 #define JMPHY_CONF 0x1B 113 #define JMPHY_CONF_EXTFIFO 0x0000 /* use extended fifo */ 114 #define JMPHY_CONF_DEFFIFO 0x0004 /* use default fifo */ 115 116 #endif /* _DEV_MII_JMPHYREG_H_ */ 117
Indexes created Sat Sep 20 22:09:52 GMT 2025