1 /* $NetBSD: mvphy.c,v 1.15 2020/03/15 23:04:50 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Marvell 88E6060 10/100 5-port PHY switch. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: mvphy.c,v 1.15 2020/03/15 23:04:50 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/socket.h> 41 #include <sys/errno.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #include <dev/mii/mii.h> 47 #include <dev/mii/miivar.h> 48 #include <dev/mii/miidevs.h> 49 50 #include <dev/mii/mvphyreg.h> 51 52 #define MV_PORT(sc) ((sc)->mii_phy - 16) /* PHY # to switch port */ 53 #define MV_CPU_PORT 5 /* port # of CPU port */ 54 55 #define MV_READ(p, phy, r, v) \ 56 (*(p)->mii_pdata->mii_readreg)(device_parent((p)->mii_dev), \ 57 (phy), (r), (v)) 58 #define MV_WRITE(p, phy, r, v) \ 59 (*(p)->mii_pdata->mii_writereg)(device_parent((p)->mii_dev), \ 60 (phy), (r), (v)) 61 62 /* XXX sysctl'able */ 63 #define MV_ATUCTRL_ATU_SIZE_DEFAULT 2 /* 1024 entry database */ 64 #define MV_ATUCTRL_AGE_TIME_DEFAULT 19 /* 19 * 16 = 304 seconds */ 65 66 /* 67 * Register manipulation macros that expect bit field defines 68 * to follow the convention that an _S suffix is appended for 69 * a shift count, while the field mask has no suffix. 70 */ 71 #define SM(_v, _f) (((_v) << _f##_S) & _f) 72 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 73 74 static int mvphymatch(device_t, cfdata_t, void *); 75 static void mvphyattach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(mvphy, sizeof(struct mii_softc), 78 mvphymatch, mvphyattach, mii_phy_detach, mii_phy_activate); 79 80 static int mvphy_service(struct mii_softc *, struct mii_data *, int); 81 static void mvphy_status(struct mii_softc *); 82 static void mvphy_reset(struct mii_softc *sc); 83 84 static const struct mii_phy_funcs mvphy_funcs = { 85 mvphy_service, mvphy_status, mvphy_reset, 86 }; 87 88 static const struct mii_phydesc mvphys[] = { 89 MII_PHY_DESC(xxMARVELL, E6060), 90 MII_PHY_END, 91 }; 92 93 /* 94 * On AP30/AR5312 the switch is configured in one of two ways: 95 * as a ROUTER or as a BRIDGE. The ROUTER config sets up ports 96 * 0-3 as LAN ports, port 4 as the WAN port, and port 5 connects 97 * to the MAC in the 5312. The BRIDGE config sets up ports 98 * 0-4 as LAN ports with port 5 connected to the MAC in the 5312. 99 */ 100 struct mvPhyConfig { 101 uint16_t switchPortAddr;/* switch port associated with PHY */ 102 uint16_t vlanSetting; /* VLAN table setting for PHY */ 103 uint32_t portControl; /* switch port control setting for PHY */ 104 }; 105 static const struct mvPhyConfig dumbConfig[] = { 106 { 0x18, 0x2e, /* PHY port 0 = LAN port 0 */ 107 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 108 { 0x19, 0x2d, /* PHY port 1 = LAN port 1 */ 109 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 110 { 0x1a, 0x2b, /* PHY port 2 = LAN port 2 */ 111 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 112 { 0x1b, 0x27, /* PHY port 3 = LAN port 3 */ 113 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 114 { 0x1c, 0x25, /* PHY port 4 = LAN port 4 */ 115 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 116 { 0x1d, 0x1f, /* PHY port 5 = CPU port */ 117 MV_PORT_CONTROL_PORT_STATE_FORWARDING } 118 }; 119 #if 0 /* XXX what are these? */ 120 static const struct mvPhyConfig routerConfig[] = { 121 { 0x18, 0x2e, /* PHY port 0 = LAN port 0 */ 122 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 123 { 0x19, 0x2d, /* PHY port 1 = LAN port 1 */ 124 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 125 { 0x1a, 0x2b, /* PHY port 2 = LAN port 2 */ 126 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 127 { 0x1b, 0x27, /* PHY port 3 = LAN port 3 */ 128 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 129 { 0x1c, 0x1020, /* PHY port 4 = WAN port */ 130 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 131 /* NB: 0x0f =>'s send only to LAN ports */ 132 { 0x1d, 0x0f, /* PHY port 5 = CPU port */ 133 MV_PORT_CONTROL_PORT_STATE_FORWARDING 134 #if 0 135 | MV_PORT_CONTROL_INGRESS_TRAILER 136 | MV_PORT_CONTROL_EGRESS_MODE 137 #endif 138 } 139 }; 140 static const struct mvPhyConfig bridgeConfig[] = { 141 { 0x18, 0x3e, /* PHY port 0 = LAN port 0 */ 142 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 143 { 0x19, 0x3d, /* PHY port 1 = LAN port 1 */ 144 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 145 { 0x1a, 0x3b, /* PHY port 2 = LAN port 2 */ 146 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 147 { 0x1b, 0x37, /* PHY port 3 = LAN port 3 */ 148 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 149 { 0x1c, 0x37, /* PHY port 4 = LAN port 4 */ 150 MV_PORT_CONTROL_PORT_STATE_FORWARDING }, 151 /* NB: 0x1f =>'s send to all ports */ 152 { 0x1d, 0x1f, /* PHY port 5 = CPU port */ 153 MV_PORT_CONTROL_PORT_STATE_FORWARDING 154 #if 0 155 | MV_PORT_CONTROL_INGRESS_TRAILER 156 | MV_PORT_CONTROL_EGRESS_MODE 157 #endif 158 } 159 }; 160 #endif 161 162 static void mvphy_switchconfig(struct mii_softc *, int); 163 static void mvphy_flushatu(struct mii_softc *); 164 165 static int 166 mvphymatch(device_t parent, cfdata_t match, void *aux) 167 { 168 struct mii_attach_args *ma = aux; 169 170 if (mii_phy_match(ma, mvphys) != NULL) 171 return 10; 172 173 return 0; 174 } 175 176 static void 177 mvphyattach(device_t parent, device_t self, void *aux) 178 { 179 struct mii_softc *sc = device_private(self); 180 struct mii_attach_args *ma = aux; 181 struct mii_data *mii = ma->mii_data; 182 const struct mii_phydesc *mpd; 183 184 mpd = mii_phy_match(ma, mvphys); 185 aprint_naive(": Media interface\n"); 186 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 187 188 sc->mii_dev = self; 189 sc->mii_inst = mii->mii_instance; 190 sc->mii_phy = ma->mii_phyno; 191 sc->mii_funcs = &mvphy_funcs; 192 sc->mii_pdata = mii; 193 sc->mii_flags = ma->mii_flags; 194 195 mii_lock(mii); 196 197 if (MV_PORT(sc) == 0) { /* NB: only when attaching first PHY */ 198 /* 199 * Set the global switch settings and configure the 200 * CPU port since it does not probe as a visible PHY. 201 */ 202 MV_WRITE(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_CONTROL, 203 SM(MV_ATUCTRL_AGE_TIME_DEFAULT, MV_ATUCTRL_AGE_TIME) 204 | SM(MV_ATUCTRL_ATU_SIZE_DEFAULT, MV_ATUCTRL_ATU_SIZE)); 205 mvphy_switchconfig(sc, MV_CPU_PORT); 206 } 207 PHY_RESET(sc); 208 209 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 210 sc->mii_capabilities &= ma->mii_capmask; 211 212 mii_unlock(mii); 213 214 mii_phy_add_media(sc); 215 } 216 217 static int 218 mvphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 219 { 220 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 221 222 KASSERT(mii_locked(mii)); 223 224 switch (cmd) { 225 case MII_POLLSTAT: 226 /* If we're not polling our PHY instance, just return. */ 227 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 228 return 0; 229 break; 230 231 case MII_MEDIACHG: 232 /* 233 * If the media indicates a different PHY instance, 234 * isolate ourselves. 235 */ 236 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 237 /* XXX? */ 238 return 0; 239 } 240 241 /* If the interface is not up, don't do anything. */ 242 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 243 break; 244 245 mii_phy_setmedia(sc); 246 break; 247 248 case MII_TICK: 249 /* If we're not currently selected, just return. */ 250 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 251 return 0; 252 253 if (mii_phy_tick(sc) == EJUSTRETURN) 254 return 0; 255 break; 256 257 case MII_DOWN: 258 mii_phy_down(sc); 259 return 0; 260 } 261 262 /* Update the media status. */ 263 mii_phy_status(sc); 264 265 /* Callback if something changed. */ 266 mii_phy_update(sc, cmd); 267 return 0; 268 } 269 270 static void 271 mvphy_status(struct mii_softc *sc) 272 { 273 struct mii_data *mii = sc->mii_pdata; 274 uint16_t hwstatus; 275 276 KASSERT(mii_locked(mii)); 277 278 mii->mii_media_status = IFM_AVALID; 279 mii->mii_media_active = IFM_ETHER; 280 281 PHY_READ(sc, MII_MV_PHY_SPECIFIC_STATUS, &hwstatus); 282 if (hwstatus & MV_STATUS_REAL_TIME_LINK_UP) { 283 mii->mii_media_status |= IFM_ACTIVE; 284 if (hwstatus & MV_STATUS_RESOLVED_SPEED_100) 285 mii->mii_media_active |= IFM_100_TX; 286 else 287 mii->mii_media_active |= IFM_10_T; 288 if (hwstatus & MV_STATUS_RESOLVED_DUPLEX_FULL) 289 mii->mii_media_active |= IFM_FDX; 290 else 291 mii->mii_media_active |= IFM_HDX; 292 } else { 293 mii->mii_media_active |= IFM_NONE; 294 /* XXX flush ATU only on link down transition */ 295 mvphy_flushatu(sc); 296 } 297 } 298 299 static void 300 mvphy_reset(struct mii_softc *sc) 301 { 302 303 KASSERT(mii_locked(sc->mii_pdata)); 304 305 /* XXX handle fixed media config */ 306 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN); 307 mvphy_switchconfig(sc, MV_PORT(sc)); 308 } 309 310 /* 311 * Configure switch for the specified port. 312 */ 313 static void 314 mvphy_switchconfig(struct mii_softc *sc, int port) 315 { 316 /* XXX router vs bridge */ 317 /*const struct mvPhyConfig *conf = &routerConfig[port];*/ 318 /*const struct mvPhyConfig *conf = &bridgeConfig[port];*/ 319 const struct mvPhyConfig *conf = &dumbConfig[port]; 320 321 MV_WRITE(sc, conf->switchPortAddr, MV_PORT_BASED_VLAN_MAP, 322 conf->vlanSetting); 323 /* XXX administrative control of port enable? */ 324 MV_WRITE(sc, conf->switchPortAddr, MV_PORT_CONTROL, conf->portControl); 325 MV_WRITE(sc, conf->switchPortAddr, MV_PORT_ASSOCIATION_VECTOR, 326 1 << port); 327 } 328 329 /* 330 * Flush the Address Translation Unit (ATU). 331 */ 332 static void 333 mvphy_flushatu(struct mii_softc *sc) 334 { 335 int status; 336 uint16_t reg; 337 int i; 338 339 /* wait for any previous request to complete */ 340 /* XXX if busy defer to tick */ 341 /* XXX timeout */ 342 for (i = 0; i < 1000; i++) { 343 status = MV_READ(sc, MII_MV_SWITCH_GLOBAL_ADDR, 344 MV_ATU_OPERATION, ®); 345 if (MV_ATU_IS_BUSY(status)) 346 break; 347 } 348 if (i != 1000) { 349 MV_WRITE(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_OPERATION, 350 MV_ATU_OP_FLUSH_ALL | MV_ATU_BUSY); 351 } /*else 352 aprint_error_dev(sc->mii_dev, "timeout waiting for ATU flush\n");*/ 353 } 354
Indexes created Sat Sep 20 22:09:52 GMT 2025