1 /* $NetBSD: mvphyreg.h,v 1.1 2006/07/21 23:55:27 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Definitions for the Marvell 88E6060 Ethernet PHY. 31 */ 32 #ifndef _DEV_MII_MVPHYREG_H_ 33 #define _DEV_MII_MVPHYREG_H_ 34 35 /* 36 * PHY Registers 37 */ 38 #define MII_MV_PHY_SPECIFIC_STATUS 17 39 #define MII_MV_SWITCH_GLOBAL_ADDR 31 /* switch itself */ 40 41 /* MV_PHY_SPECIFIC_STATUS fields */ 42 #define MV_STATUS_RESOLVED_SPEED_100 0x4000 43 #define MV_STATUS_RESOLVED_DUPLEX_FULL 0x2000 44 #define MV_STATUS_RESOLVED 0x0800 45 #define MV_STATUS_REAL_TIME_LINK_UP 0x0400 46 47 /* 48 * Per-Port Switch Registers 49 */ 50 #define MV_PORT_STATUS 0 51 #define MV_SWITCH_ID 3 52 #define MV_PORT_CONTROL 4 53 #define MV_PORT_BASED_VLAN_MAP 6 54 #define MV_PORT_ASSOCIATION_VECTOR 11 55 #define MV_RX_COUNTER 16 56 #define MV_TX_COUNTER 17 57 58 /* MV_SWITCH_ID fields */ 59 #define MV_SWITCH_ID_DEV 0xfff0 60 #define MV_SWITCH_ID_DEV_S 4 61 #define MV_SWITCH_ID_REV 0x000f 62 #define MV_SWITCH_ID_REV_S 0 63 64 /* MV_PORT_CONTROL fields */ 65 #define MV_PORT_CONTROL_PORT_STATE 0x0003 66 #define MV_PORT_CONTROL_PORT_STATE_DISABLED 0x0000 67 #define MV_PORT_CONTROL_PORT_STATE_FORWARDING 0x0003 68 69 #define MV_PORT_CONTROL_EGRESS_MODE 0x0100 /* enable on rx */ 70 #define MV_PORT_CONTROL_INGRESS_TRAILER 0x4000 /* enable on tx */ 71 72 #define MV_EGRESS_TRAILER_VALID 0x80 73 #define MV_INGRESS_TRAILER_OVERRIDE 0x80 74 75 #define MV_PHY_TRAILER_SIZE 4 76 77 /* 78 * Switch Global Registers accessed via MII_MV_SWITCH_GLOBAL_ADDR. 79 */ 80 #define MV_SWITCH_GLOBAL_STATUS 0 81 #define MV_SWITCH_MAC_ADDR0 1 82 #define MV_SWITCH_MAC_ADDR2 2 83 #define MV_SWITCH_MAC_ADDR4 3 84 #define MV_SWITCH_GLOBAL_CONTROL 4 85 #define MV_ATU_CONTROL 10 86 #define MV_ATU_OPERATION 11 87 #define MV_ATU_DATA 12 88 #define MV_ATU_MAC_ADDR0 13 89 #define MV_ATU_MAC_ADDR2 14 90 #define MV_ATU_MAC_ADDR4 15 91 92 /* MV_SWITCH_GLOBAL_STATUS fields */ 93 #define MV_SWITCH_STATUS_READY 0x0800 94 95 /* MV_SWITCH_GLOBAL_CONTROL fields */ 96 #define MV_CTRMODE 0x0100 97 #define MV_CTRMODE_GOODFRAMES 0x0000 98 #define MV_CTRMODE_BADFRAMES 0x0100 99 100 /* MV_ATU_CONTROL fields */ 101 #define MV_ATUCTRL_ATU_SIZE 0x3000 102 #define MV_ATUCTRL_ATU_SIZE_S 12 103 #define MV_ATUCTRL_AGE_TIME 0x0ff0 104 #define MV_ATUCTRL_AGE_TIME_S 4 105 106 /* MV_ATU_OPERATION fields */ 107 #define MV_ATU_BUSY 0x8000 108 #define MV_ATU_OP 0x7000 109 #define MV_ATU_OP_FLUSH_ALL 0x1000 110 #define MV_ATU_OP_GET_NEXT 0x4000 111 112 #define MV_ATU_IS_BUSY(v) (((v) & MV_ATU_BUSY) != 0) 113 114 /* MV_ATU_DATA fields */ 115 #define MV_ENTRYPRI 0xc000 116 #define MV_ENTRYPRI_S 14 117 #define MV_PORTVEC 0x03f0 118 #define MV_PORTVEC_S 4 119 #define MV_ENTRYSTATE 0x000f 120 #define MV_ENTRYSTATE_S 0 121 122 #endif /* _DEV_MII_MVPHYREG_H_ */ 123
Indexes created Mon Sep 22 13:09:51 GMT 2025