1 /* $NetBSD: memc.c,v 1.11 2012/10/27 17:18:27 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Support for the MEMECC and MEMC40 memory controllers on MVME68K 34 * and MVME88K boards. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: memc.c,v 1.11 2012/10/27 17:18:27 chs Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/kernel.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #include <sys/cpu.h> 47 #include <sys/bus.h> 48 49 #include <dev/mvme/memcvar.h> 50 #include <dev/mvme/memcreg.h> 51 #include <dev/mvme/pcctwovar.h> 52 #include <dev/mvme/pcctworeg.h> 53 54 #include <dev/vme/vmevar.h> 55 #include <dev/mvme/mvmebus.h> 56 #include <dev/mvme/vme_twovar.h> 57 #include <dev/mvme/vme_tworeg.h> 58 59 60 static struct memc_softc *memc_softcs[MEMC_NDEVS]; 61 static int memc_softc_count; 62 63 static void memc040_attach(struct memc_softc *); 64 static void memecc_attach(struct memc_softc *); 65 static void memc_hook_error_intr(struct memc_softc *, int (*)(void *)); 66 67 static int memecc_err_intr(void *); 68 static void memecc_log_error(struct memc_softc *, u_int8_t, int, int); 69 70 #define MEMECC_SCRUBBER_PERIOD 86400 /* ~24 hours */ 71 72 /* 73 * The following stuff is used to decode the ECC syndrome code so 74 * that we can figure out exactly which address/bit needed to be 75 * corrected. 76 */ 77 #define MEMECC_SYN_BIT_MASK 0x0fu 78 #define MEMECC_SYN_BANK_A (0x00u << 4) 79 #define MEMECC_SYN_BANK_B (0x01u << 4) 80 #define MEMECC_SYN_BANK_C (0x02u << 4) 81 #define MEMECC_SYN_BANK_D (0x03u << 4) 82 #define MEMECC_SYN_BANK_SHIFT 4 83 #define MEMECC_SYN_BANK_MASK 0x03u 84 #define MEMECC_SYN_CHECKBIT_ERR 0x80u 85 #define MEMECC_SYN_INVALID 0xffu 86 87 static u_int8_t memc_syn_decode[256] = { 88 MEMECC_SYN_INVALID, /* 0x00 */ 89 MEMECC_SYN_CHECKBIT_ERR | 0, /* 0x01: Checkbit 0 */ 90 MEMECC_SYN_CHECKBIT_ERR | 1, /* 0x02: Checkbit 1 */ 91 MEMECC_SYN_INVALID, /* 0x03 */ 92 MEMECC_SYN_CHECKBIT_ERR | 2, /* 0x04: Checkbit 2 */ 93 MEMECC_SYN_INVALID, /* 0x05 */ 94 MEMECC_SYN_INVALID, /* 0x06 */ 95 MEMECC_SYN_BANK_C | 10, /* 0x07: Bank C 10/26 */ 96 MEMECC_SYN_CHECKBIT_ERR | 3, /* 0x08: Checkbit 3 */ 97 MEMECC_SYN_INVALID, /* 0x09 */ 98 MEMECC_SYN_INVALID, /* 0x0a */ 99 MEMECC_SYN_BANK_C | 13, /* 0x0b: Bank C 13/29 */ 100 MEMECC_SYN_INVALID, /* 0x0c */ 101 MEMECC_SYN_BANK_D | 1, /* 0x0d: Bank D 1/17 */ 102 MEMECC_SYN_BANK_D | 2, /* 0x0e: Bank D 2/18 */ 103 MEMECC_SYN_INVALID, /* 0x0f */ 104 MEMECC_SYN_CHECKBIT_ERR | 4, /* 0x10: Checkbit 4 */ 105 MEMECC_SYN_INVALID, /* 0x11 */ 106 MEMECC_SYN_INVALID, /* 0x12 */ 107 MEMECC_SYN_BANK_C | 14, /* 0x13: Bank C 14/30 */ 108 MEMECC_SYN_INVALID, /* 0x14 */ 109 MEMECC_SYN_BANK_D | 4, /* 0x15: Bank D 4/20 */ 110 MEMECC_SYN_BANK_D | 5, /* 0x16: Bank D 5/21 */ 111 MEMECC_SYN_INVALID, /* 0x17 */ 112 MEMECC_SYN_INVALID, /* 0x18 */ 113 MEMECC_SYN_BANK_D | 8, /* 0x19: Bank D 8/24 */ 114 MEMECC_SYN_BANK_D | 9, /* 0x1a: Bank D 9/25 */ 115 MEMECC_SYN_INVALID, /* 0x1b */ 116 MEMECC_SYN_BANK_D | 10, /* 0x1c: Bank D 10/26 */ 117 MEMECC_SYN_INVALID, /* 0x1d */ 118 MEMECC_SYN_INVALID, /* 0x1e */ 119 MEMECC_SYN_INVALID, /* 0x1f */ 120 MEMECC_SYN_CHECKBIT_ERR | 5, /* 0x20: Checkbit 5 */ 121 MEMECC_SYN_INVALID, /* 0x21 */ 122 MEMECC_SYN_INVALID, /* 0x22 */ 123 MEMECC_SYN_BANK_C | 0, /* 0x23: Bank C 0/16 */ 124 MEMECC_SYN_INVALID, /* 0x24 */ 125 MEMECC_SYN_BANK_D | 7, /* 0x25: Bank D 7/23 */ 126 MEMECC_SYN_BANK_D | 6, /* 0x26: Bank D 6/22 */ 127 MEMECC_SYN_INVALID, /* 0x27 */ 128 MEMECC_SYN_INVALID, /* 0x28 */ 129 MEMECC_SYN_BANK_A | 15, /* 0x29: Bank A 15/31 */ 130 MEMECC_SYN_BANK_D | 12, /* 0x2a: Bank D 12/28 */ 131 MEMECC_SYN_INVALID, /* 0x2b */ 132 MEMECC_SYN_BANK_D | 13, /* 0x2c: Bank D 13/29 */ 133 MEMECC_SYN_INVALID, /* 0x2d */ 134 MEMECC_SYN_INVALID, /* 0x2e */ 135 MEMECC_SYN_INVALID, /* 0x2f */ 136 MEMECC_SYN_INVALID, /* 0x30 */ 137 MEMECC_SYN_BANK_A | 14, /* 0x31: Bank A 14/30 */ 138 MEMECC_SYN_BANK_A | 0, /* 0x32: Bank A 0/16 */ 139 MEMECC_SYN_INVALID, /* 0x33 */ 140 MEMECC_SYN_BANK_A | 1, /* 0x34: Bank A 1/17 */ 141 MEMECC_SYN_INVALID, /* 0x35 */ 142 MEMECC_SYN_INVALID, /* 0x36 */ 143 MEMECC_SYN_INVALID, /* 0x37 */ 144 MEMECC_SYN_BANK_A | 2, /* 0x38: Bank A 2/18 */ 145 MEMECC_SYN_INVALID, /* 0x39 */ 146 MEMECC_SYN_INVALID, /* 0x3a */ 147 MEMECC_SYN_INVALID, /* 0x3b */ 148 MEMECC_SYN_INVALID, /* 0x3c */ 149 MEMECC_SYN_BANK_C | 3, /* 0x3d: Bank C 3/19 */ 150 MEMECC_SYN_INVALID, /* 0x3e */ 151 MEMECC_SYN_INVALID, /* 0x3f */ 152 MEMECC_SYN_CHECKBIT_ERR | 6, /* 0x40: Checkbit 6 */ 153 MEMECC_SYN_INVALID, /* 0x41 */ 154 MEMECC_SYN_INVALID, /* 0x42 */ 155 MEMECC_SYN_BANK_C | 1, /* 0x43: Bank C 1/17 */ 156 MEMECC_SYN_INVALID, /* 0x44 */ 157 MEMECC_SYN_BANK_C | 4, /* 0x45: Bank C 4/20 */ 158 MEMECC_SYN_BANK_C | 8, /* 0x46: Bank C 8/24 */ 159 MEMECC_SYN_INVALID, /* 0x47 */ 160 MEMECC_SYN_INVALID, /* 0x48 */ 161 MEMECC_SYN_BANK_C | 7, /* 0x49: Bank C 7/23 */ 162 MEMECC_SYN_BANK_D | 15, /* 0x4a: Bank D 15/31 */ 163 MEMECC_SYN_INVALID, /* 0x4b */ 164 MEMECC_SYN_BANK_D | 14, /* 0x4c: Bank D 14/30 */ 165 MEMECC_SYN_INVALID, /* 0x4d */ 166 MEMECC_SYN_INVALID, /* 0x4e */ 167 MEMECC_SYN_BANK_B | 3, /* 0x4f: Bank B 3/19 */ 168 MEMECC_SYN_INVALID, /* 0x50 */ 169 MEMECC_SYN_BANK_B | 4, /* 0x51: Bank B 4/20 */ 170 MEMECC_SYN_BANK_B | 7, /* 0x52: Bank B 7/23 */ 171 MEMECC_SYN_INVALID, /* 0x53 */ 172 MEMECC_SYN_BANK_A | 4, /* 0x54: Bank A 4/20 */ 173 MEMECC_SYN_INVALID, /* 0x55 */ 174 MEMECC_SYN_INVALID, /* 0x56 */ 175 MEMECC_SYN_INVALID, /* 0x57 */ 176 MEMECC_SYN_BANK_A | 5, /* 0x58: Bank A 5/21 */ 177 MEMECC_SYN_INVALID, /* 0x59 */ 178 MEMECC_SYN_INVALID, /* 0x5a */ 179 MEMECC_SYN_INVALID, /* 0x5b */ 180 MEMECC_SYN_INVALID, /* 0x5c */ 181 MEMECC_SYN_INVALID, /* 0x5d */ 182 MEMECC_SYN_INVALID, /* 0x5e */ 183 MEMECC_SYN_INVALID, /* 0x5f */ 184 MEMECC_SYN_INVALID, /* 0x60 */ 185 MEMECC_SYN_BANK_B | 5, /* 0x61: Bank B 5/21 */ 186 MEMECC_SYN_BANK_B | 6, /* 0x62: Bank B 6/22 */ 187 MEMECC_SYN_INVALID, /* 0x63 */ 188 MEMECC_SYN_BANK_A | 8, /* 0x64: Bank A 8/24 */ 189 MEMECC_SYN_INVALID, /* 0x65 */ 190 MEMECC_SYN_INVALID, /* 0x66 */ 191 MEMECC_SYN_INVALID, /* 0x67 */ 192 MEMECC_SYN_BANK_A | 9, /* 0x68: Bank A 9/25 */ 193 MEMECC_SYN_INVALID, /* 0x69 */ 194 MEMECC_SYN_INVALID, /* 0x6a */ 195 MEMECC_SYN_INVALID, /* 0x6b */ 196 MEMECC_SYN_INVALID, /* 0x6c */ 197 MEMECC_SYN_INVALID, /* 0x6d */ 198 MEMECC_SYN_INVALID, /* 0x6e */ 199 MEMECC_SYN_INVALID, /* 0x6f */ 200 MEMECC_SYN_BANK_A | 10, /* 0x70: Bank A 10/26 */ 201 MEMECC_SYN_INVALID, /* 0x71 */ 202 MEMECC_SYN_INVALID, /* 0x72 */ 203 MEMECC_SYN_INVALID, /* 0x73 */ 204 MEMECC_SYN_INVALID, /* 0x74 */ 205 MEMECC_SYN_INVALID, /* 0x75 */ 206 MEMECC_SYN_INVALID, /* 0x76 */ 207 MEMECC_SYN_INVALID, /* 0x77 */ 208 MEMECC_SYN_INVALID, /* 0x78 */ 209 MEMECC_SYN_INVALID, /* 0x79 */ 210 MEMECC_SYN_BANK_C | 11, /* 0x7a: Bank C 11/27 */ 211 MEMECC_SYN_INVALID, /* 0x7b */ 212 MEMECC_SYN_INVALID, /* 0x7c */ 213 MEMECC_SYN_INVALID, /* 0x7d */ 214 MEMECC_SYN_INVALID, /* 0x7e */ 215 MEMECC_SYN_INVALID, /* 0x7f */ 216 MEMECC_SYN_CHECKBIT_ERR | 7, /* 0x80: Checkbit 7 */ 217 MEMECC_SYN_INVALID, /* 0x81 */ 218 MEMECC_SYN_INVALID, /* 0x82 */ 219 MEMECC_SYN_BANK_C | 2, /* 0x83: Bank C 2/18 */ 220 MEMECC_SYN_INVALID, /* 0x84 */ 221 MEMECC_SYN_BANK_C | 5, /* 0x85: Bank C 5/21 */ 222 MEMECC_SYN_BANK_C | 9, /* 0x86: Bank C 9/25 */ 223 MEMECC_SYN_INVALID, /* 0x87 */ 224 MEMECC_SYN_INVALID, /* 0x88 */ 225 MEMECC_SYN_BANK_C | 6, /* 0x89: Bank C 6/22 */ 226 MEMECC_SYN_BANK_C | 12, /* 0x8a: Bank C 12/28 */ 227 MEMECC_SYN_INVALID, /* 0x8b */ 228 MEMECC_SYN_BANK_D | 0, /* 0x8c: Bank D 0/16 */ 229 MEMECC_SYN_INVALID, /* 0x8d */ 230 MEMECC_SYN_INVALID, /* 0x8e */ 231 MEMECC_SYN_INVALID, /* 0x8f */ 232 MEMECC_SYN_INVALID, /* 0x90 */ 233 MEMECC_SYN_BANK_B | 8, /* 0x91: Bank B 8/24 */ 234 MEMECC_SYN_BANK_C | 15, /* 0x92: Bank C 15/31 */ 235 MEMECC_SYN_INVALID, /* 0x93 */ 236 MEMECC_SYN_BANK_A | 7, /* 0x94: Bank A 7/23 */ 237 MEMECC_SYN_INVALID, /* 0x95 */ 238 MEMECC_SYN_INVALID, /* 0x96 */ 239 MEMECC_SYN_INVALID, /* 0x97 */ 240 MEMECC_SYN_BANK_A | 6, /* 0x98: Bank A 6/22 */ 241 MEMECC_SYN_INVALID, /* 0x99 */ 242 MEMECC_SYN_INVALID, /* 0x9a */ 243 MEMECC_SYN_INVALID, /* 0x9b */ 244 MEMECC_SYN_INVALID, /* 0x9c */ 245 MEMECC_SYN_INVALID, /* 0x9d */ 246 MEMECC_SYN_BANK_B | 11, /* 0x9e: Bank B 11/27 */ 247 MEMECC_SYN_INVALID, /* 0x9f */ 248 MEMECC_SYN_INVALID, /* 0xa0 */ 249 MEMECC_SYN_BANK_B | 9, /* 0xa1: Bank B 9/25 */ 250 MEMECC_SYN_BANK_B | 12, /* 0xa2: Bank B 12/28 */ 251 MEMECC_SYN_INVALID, /* 0xa3 */ 252 MEMECC_SYN_BANK_B | 15, /* 0xa4: Bank B 15/31 */ 253 MEMECC_SYN_INVALID, /* 0xa5 */ 254 MEMECC_SYN_INVALID, /* 0xa6 */ 255 MEMECC_SYN_BANK_A | 11, /* 0xa7: Bank A 11/27 */ 256 MEMECC_SYN_BANK_A | 12, /* 0xa8: Bank A 12/28 */ 257 MEMECC_SYN_INVALID, /* 0xa9 */ 258 MEMECC_SYN_INVALID, /* 0xaa */ 259 MEMECC_SYN_INVALID, /* 0xab */ 260 MEMECC_SYN_INVALID, /* 0xac */ 261 MEMECC_SYN_INVALID, /* 0xad */ 262 MEMECC_SYN_INVALID, /* 0xae */ 263 MEMECC_SYN_INVALID, /* 0xaf */ 264 MEMECC_SYN_BANK_A | 13, /* 0xb0: Bank A 13/29 */ 265 MEMECC_SYN_INVALID, /* 0xb1 */ 266 MEMECC_SYN_INVALID, /* 0xb2 */ 267 MEMECC_SYN_INVALID, /* 0xb3 */ 268 MEMECC_SYN_INVALID, /* 0xb4 */ 269 MEMECC_SYN_INVALID, /* 0xb5 */ 270 MEMECC_SYN_INVALID, /* 0xb6 */ 271 MEMECC_SYN_INVALID, /* 0xb7 */ 272 MEMECC_SYN_INVALID, /* 0xb8 */ 273 MEMECC_SYN_INVALID, /* 0xb9 */ 274 MEMECC_SYN_INVALID, /* 0xba */ 275 MEMECC_SYN_INVALID, /* 0xbb */ 276 MEMECC_SYN_INVALID, /* 0xbc */ 277 MEMECC_SYN_INVALID, /* 0xbd */ 278 MEMECC_SYN_INVALID, /* 0xbe */ 279 MEMECC_SYN_INVALID, /* 0xbf */ 280 MEMECC_SYN_INVALID, /* 0xc0 */ 281 MEMECC_SYN_BANK_B | 10, /* 0xc1: Bank B 10/26 */ 282 MEMECC_SYN_BANK_B | 13, /* 0xc2: Bank B 13/29 */ 283 MEMECC_SYN_INVALID, /* 0xc3 */ 284 MEMECC_SYN_BANK_B | 14, /* 0xc4: Bank B 14/30 */ 285 MEMECC_SYN_INVALID, /* 0xc5 */ 286 MEMECC_SYN_INVALID, /* 0xc6 */ 287 MEMECC_SYN_INVALID, /* 0xc7 */ 288 MEMECC_SYN_BANK_B | 0, /* 0xc8: Bank B 0/16 */ 289 MEMECC_SYN_INVALID, /* 0xc9 */ 290 MEMECC_SYN_INVALID, /* 0xca */ 291 MEMECC_SYN_INVALID, /* 0xcb */ 292 MEMECC_SYN_INVALID, /* 0xcc */ 293 MEMECC_SYN_INVALID, /* 0xcd */ 294 MEMECC_SYN_INVALID, /* 0xce */ 295 MEMECC_SYN_INVALID, /* 0xcf */ 296 MEMECC_SYN_BANK_B | 1, /* 0xd0: Bank B 1/17 */ 297 MEMECC_SYN_INVALID, /* 0xd1 */ 298 MEMECC_SYN_INVALID, /* 0xd2 */ 299 MEMECC_SYN_BANK_A | 3, /* 0xd3: Bank A 3/19 */ 300 MEMECC_SYN_INVALID, /* 0xd4 */ 301 MEMECC_SYN_INVALID, /* 0xd5 */ 302 MEMECC_SYN_INVALID, /* 0xd6 */ 303 MEMECC_SYN_INVALID, /* 0xd7 */ 304 MEMECC_SYN_INVALID, /* 0xd8 */ 305 MEMECC_SYN_INVALID, /* 0xd9 */ 306 MEMECC_SYN_INVALID, /* 0xda */ 307 MEMECC_SYN_INVALID, /* 0xdb */ 308 MEMECC_SYN_INVALID, /* 0xdc */ 309 MEMECC_SYN_INVALID, /* 0xdd */ 310 MEMECC_SYN_INVALID, /* 0xde */ 311 MEMECC_SYN_INVALID, /* 0xdf */ 312 MEMECC_SYN_BANK_B | 2, /* 0xe0: Bank B 2/18 */ 313 MEMECC_SYN_INVALID, /* 0xe1 */ 314 MEMECC_SYN_INVALID, /* 0xe2 */ 315 MEMECC_SYN_INVALID, /* 0xe3 */ 316 MEMECC_SYN_INVALID, /* 0xe4 */ 317 MEMECC_SYN_INVALID, /* 0xe5 */ 318 MEMECC_SYN_INVALID, /* 0xe6 */ 319 MEMECC_SYN_INVALID, /* 0xe7 */ 320 MEMECC_SYN_INVALID, /* 0xe8 */ 321 MEMECC_SYN_BANK_D | 11, /* 0xe9: Bank D 11/27 */ 322 MEMECC_SYN_INVALID, /* 0xea */ 323 MEMECC_SYN_INVALID, /* 0xeb */ 324 MEMECC_SYN_INVALID, /* 0xec */ 325 MEMECC_SYN_INVALID, /* 0xed */ 326 MEMECC_SYN_INVALID, /* 0xee */ 327 MEMECC_SYN_INVALID, /* 0xef */ 328 MEMECC_SYN_INVALID, /* 0xf0 */ 329 MEMECC_SYN_INVALID, /* 0xf1 */ 330 MEMECC_SYN_INVALID, /* 0xf2 */ 331 MEMECC_SYN_INVALID, /* 0xf3 */ 332 MEMECC_SYN_BANK_D | 3, /* 0xf4: Bank D 3/19 */ 333 MEMECC_SYN_INVALID, /* 0xf5 */ 334 MEMECC_SYN_INVALID, /* 0xf6 */ 335 MEMECC_SYN_INVALID, /* 0xf7 */ 336 MEMECC_SYN_INVALID, /* 0xf8 */ 337 MEMECC_SYN_INVALID, /* 0xf9 */ 338 MEMECC_SYN_INVALID, /* 0xfa */ 339 MEMECC_SYN_INVALID, /* 0xfb */ 340 MEMECC_SYN_INVALID, /* 0xfc */ 341 MEMECC_SYN_INVALID, /* 0xfd */ 342 MEMECC_SYN_INVALID, /* 0xfe */ 343 MEMECC_SYN_INVALID /* 0xff */ 344 }; 345 346 347 /* ARGSUSED */ 348 void 349 memc_init(struct memc_softc *sc) 350 { 351 u_int8_t chipid; 352 u_int8_t memcfg; 353 354 if (memc_softc_count == MEMC_NDEVS) 355 panic("memc_attach: too many memc devices!"); 356 357 memc_softcs[memc_softc_count++] = sc; 358 359 chipid = memc_reg_read(sc, MEMC_REG_CHIP_ID); 360 memcfg = memc_reg_read(sc, MEMC_REG_MEMORY_CONFIG); 361 362 printf(": %dMB %s Memory Controller Chip (Rev %d)\n", 363 MEMC_MEMORY_CONFIG_2_MB(memcfg), 364 (chipid == MEMC_CHIP_ID_MEMC040) ? "Parity" : "ECC", 365 memc_reg_read(sc, MEMC_REG_CHIP_REVISION)); 366 367 printf("%s: Base Address: 0x%x, ", device_xname(sc->sc_dev), 368 MEMC_BASE_ADDRESS(memc_reg_read(sc, MEMC_REG_BASE_ADDRESS_HI), 369 memc_reg_read(sc, MEMC_REG_BASE_ADDRESS_LO))); 370 371 printf("Fast RAM Read %sabled\n", (memc_reg_read(sc, 372 MEMC_REG_MEMORY_CONFIG) & MEMC_MEMORY_CONFIG_FSTRD) ? 373 "En" : "Dis"); 374 375 switch (chipid) { 376 case MEMC_CHIP_ID_MEMC040: 377 memc040_attach(sc); 378 break; 379 case MEMC_CHIP_ID_MEMECC: 380 memecc_attach(sc); 381 break; 382 } 383 } 384 385 static void 386 memc040_attach(struct memc_softc *sc) 387 { 388 389 /* XXX: TBD */ 390 } 391 392 static void 393 memecc_attach(struct memc_softc *sc) 394 { 395 u_int8_t rv; 396 397 /* 398 * First, disable bus-error and interrupts on ECC errors. 399 * Also switch off SWAIT to enhance performance. 400 */ 401 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL); 402 rv &= ~(MEMECC_DRAM_CONTROL_NCEBEN | 403 MEMECC_DRAM_CONTROL_NCEIEN | 404 MEMECC_DRAM_CONTROL_SWAIT); 405 rv |= MEMECC_DRAM_CONTROL_RAMEN; 406 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL, rv); 407 rv = memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL); 408 rv &= ~(MEMECC_SCRUB_CONTROL_SCRBEN | MEMECC_SCRUB_CONTROL_SBEIEN); 409 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL, rv); 410 411 /* 412 * Ensure error correction is enabled 413 */ 414 rv = memc_reg_read(sc, MEMECC_REG_DATA_CONTROL); 415 rv &= ~MEMECC_DATA_CONTROL_DERC; 416 memc_reg_write(sc, MEMECC_REG_DATA_CONTROL, rv); 417 418 /* 419 * Clear any error currently in the logs 420 */ 421 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER); 422 #ifdef DIAGNOSTIC 423 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) 424 memecc_log_error(sc, rv, 0, 0); 425 #endif 426 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER, 427 MEMECC_ERROR_LOGGER_ERRLOG); 428 429 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER + 2); 430 #ifdef DIAGNOSTIC 431 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) 432 memecc_log_error(sc, rv, 2, 0); 433 #endif 434 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER + 2, 435 MEMECC_ERROR_LOGGER_ERRLOG); 436 437 /* 438 * Now hook the ECC error interrupt 439 */ 440 if (memc_softc_count == 1) 441 memc_hook_error_intr(sc, memecc_err_intr); 442 443 /* 444 * Enable bus-error and interrupt on uncorrectable ECC 445 */ 446 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL); 447 rv |= MEMECC_DRAM_CONTROL_NCEBEN | MEMECC_DRAM_CONTROL_NCEIEN; 448 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL, rv); 449 450 /* 451 * Set up the scrubber to run roughly once every 24 hours 452 * with minimal impact on the local bus. With these on/off 453 * time settings, a scrub of a 32MB DRAM board will take 454 * roughly half a minute. 455 */ 456 memc_reg_write(sc, MEMECC_REG_SCRUB_PERIOD_HI, 457 MEMECC_SCRUB_PERIOD_HI(MEMECC_SCRUBBER_PERIOD)); 458 memc_reg_write(sc, MEMECC_REG_SCRUB_PERIOD_LO, 459 MEMECC_SCRUB_PERIOD_LO(MEMECC_SCRUBBER_PERIOD)); 460 memc_reg_write(sc, MEMECC_REG_SCRUB_TIME_ONOFF, 461 MEMECC_SCRUB_TIME_ON_1 | MEMECC_SCRUB_TIME_OFF_16); 462 463 /* 464 * Start the scrubber, and enable interrupts on Correctable errors 465 */ 466 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL, 467 memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL) | 468 MEMECC_SCRUB_CONTROL_SCRBEN | MEMECC_SCRUB_CONTROL_SBEIEN); 469 470 printf("%s: Logging ECC errors at ipl %d\n", device_xname(sc->sc_dev), 471 MEMC_IRQ_LEVEL); 472 } 473 474 static void 475 memc_hook_error_intr(struct memc_softc *sc, int (*func)(void *)) 476 { 477 478 #if 0 479 evcnt_attach_dynamic(&sc->sc_evcnt, EVCNT_TYPE_INTR, 480 (*sc->sc_isrevcnt)(sc->sc_isrcookie, MEMC_IRQ_LEVEL), 481 "memory", "ecc errors"); 482 #endif 483 484 /* 485 * On boards without a VMEChip2, the interrupt is routed 486 * via the MCChip (mvme162/mvme172). 487 */ 488 if (vmetwo_not_present) 489 pcctwointr_establish(MCCHIPV_PARITY_ERR, func, MEMC_IRQ_LEVEL, 490 sc, &sc->sc_evcnt); 491 else 492 vmetwo_local_intr_establish(MEMC_IRQ_LEVEL, 493 VME2_VEC_PARITY_ERROR, func, sc, &sc->sc_evcnt); 494 } 495 496 /* ARGSUSED */ 497 static int 498 memecc_err_intr(void *arg) 499 { 500 struct memc_softc *sc; 501 u_int8_t rv; 502 int i, j, cnt = 0; 503 504 /* 505 * For each memory controller we found ... 506 */ 507 for (i = 0; i < memc_softc_count; i++) { 508 sc = memc_softcs[i]; 509 510 /* 511 * There are two error loggers per controller, the registers of 512 * the 2nd are offset from the 1st by 2 bytes. 513 */ 514 for (j = 0; j <= 2; j += 2) { 515 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER + j); 516 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) { 517 memecc_log_error(sc, rv, j, 1); 518 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER + j, 519 MEMECC_ERROR_LOGGER_ERRLOG); 520 cnt++; 521 } 522 } 523 } 524 525 return (cnt); 526 } 527 528 /* 529 * Log an ECC error to the console. 530 * Note: Since this usually runs at an elevated ipl (above clock), we 531 * should probably schedule a soft interrupt to log the error details. 532 * (But only for errors where we would not normally panic.) 533 */ 534 static void 535 memecc_log_error(struct memc_softc *sc, u_int8_t errlog, int off, int mbepanic) 536 { 537 u_int32_t addr; 538 u_int8_t rv, syndrome; 539 const char *bm = "CPU"; 540 const char *rdwr; 541 const char *etype; 542 char syntext[32]; 543 544 /* 545 * Get the address associated with the error. 546 */ 547 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_HIHI + off); 548 addr = (u_int32_t)rv; 549 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_HI + off); 550 addr = (addr << 8) | (u_int32_t)rv; 551 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_MID + off); 552 addr = (addr << 8) | (u_int32_t)rv; 553 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_LO + off); 554 addr = (addr << 8) | (u_int32_t)rv; 555 556 /* 557 * And the Syndrome bits 558 */ 559 syndrome = memc_reg_read(sc, MEMECC_REG_ERROR_SYNDROME + off); 560 561 rdwr = ((errlog & MEMECC_ERROR_LOGGER_ERD) != 0) ? " read" : " write"; 562 563 if ((errlog & MEMECC_ERROR_LOGGER_EALT) != 0) 564 bm = "Peripheral Device"; 565 else 566 if ((errlog & MEMECC_ERROR_LOGGER_ESCRB) != 0) { 567 bm = "Scrubber"; 568 rdwr = ""; 569 } 570 571 if ((errlog & MEMECC_ERROR_LOGGER_SBE) != 0) { 572 int syncode, bank, bitnum; 573 574 etype = "Correctable"; 575 syncode = memc_syn_decode[syndrome]; 576 bitnum = (syncode & MEMECC_SYN_BIT_MASK) + (off ? 16 : 0); 577 bank = (syncode >> MEMECC_SYN_BANK_SHIFT) &MEMECC_SYN_BANK_MASK; 578 579 if (syncode == MEMECC_SYN_INVALID) 580 strcpy(syntext, "Invalid!"); 581 else 582 if ((syncode & MEMECC_SYN_CHECKBIT_ERR) != 0) 583 snprintf(syntext, sizeof(syntext), 584 "Checkbit#%d", bitnum); 585 else { 586 addr |= (u_int32_t) (bank << 2); 587 snprintf(syntext, sizeof(syntext), 588 "DRAM Bank %c, Bit#%d", 'A' + bank, bitnum); 589 } 590 } else if ((errlog & MEMECC_ERROR_LOGGER_MBE) != 0) 591 etype = "Uncorrectable"; 592 else 593 etype = "Spurious"; 594 595 printf("%s: %s error on %s%s access to 0x%08x.\n", 596 device_xname(sc->sc_dev), etype, bm, rdwr, addr); 597 598 if ((errlog & MEMECC_ERROR_LOGGER_SBE) != 0) 599 printf("%s: ECC Syndrome 0x%02x (%s)\n", device_xname(sc->sc_dev), 600 syndrome, syntext); 601 602 /* 603 * If an uncorrectable error was detected by an alternate 604 * bus master or the scrubber, panic immediately. 605 * We can't rely on the contents of memory at this point. 606 * 607 * Uncorrectable errors detected when the CPU was accessing 608 * DRAM will cause the CPU to take a bus error trap. Depending 609 * on whether the error was in kernel or user mode, the system 610 * with either panic or kill the affected process. Basically, 611 * we don't have to deal with it here. 612 * 613 * XXX: I'm not sure whether it's our responsibility to 614 * perform some dummy writes to the offending address in this 615 * case to re-generate a good ECC. Note that we'd have to write 616 * an entire block of 4 words since we can only narrow down the 617 * faulty address for correctable errors... 618 */ 619 if (mbepanic && (errlog & MEMECC_ERROR_LOGGER_MBE) && 620 (errlog & (MEMECC_ERROR_LOGGER_ESCRB|MEMECC_ERROR_LOGGER_EALT))) { 621 /* 622 * Ensure we don't get a Bus Error while panicking... 623 */ 624 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL + off); 625 rv &= ~(MEMECC_DRAM_CONTROL_NCEBEN | 626 MEMECC_DRAM_CONTROL_NCEIEN); 627 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL + off, rv); 628 rv = memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL + off); 629 rv &= ~(MEMECC_SCRUB_CONTROL_SBEIEN | 630 MEMECC_SCRUB_CONTROL_SCRBEN); 631 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL + off, rv); 632 633 panic("%s: Halting system to preserve data integrity.", 634 device_xname(sc->sc_dev)); 635 } 636 } 637
Indexes created Sat Sep 20 22:09:52 GMT 2025