memc.c revision 1.1
1 /* $NetBSD: memc.c,v 1.1 2002/02/12 20:38:46 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Support for the MEMECC and MEMC40 memory controllers on MVME68K 41 * and MVME88K boards. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/kernel.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 50 #include <machine/cpu.h> 51 #include <machine/bus.h> 52 53 #include <dev/mvme/memcvar.h> 54 #include <dev/mvme/memcreg.h> 55 #include <dev/mvme/pcctwovar.h> 56 #include <dev/mvme/pcctworeg.h> 57 58 #include <dev/vme/vmevar.h> 59 #include <dev/mvme/mvmebus.h> 60 #include <dev/mvme/vme_twovar.h> 61 #include <dev/mvme/vme_tworeg.h> 62 63 64 static struct memc_softc *memc_softcs[MEMC_NDEVS]; 65 static int memc_softc_count; 66 67 static void memc040_attach(struct memc_softc *); 68 static void memecc_attach(struct memc_softc *); 69 static void memc_hook_error_intr(struct memc_softc *, int (*)(void *)); 70 71 static int memecc_err_intr(void *); 72 static void memecc_log_error(struct memc_softc *, u_int8_t, int, int); 73 74 #define MEMECC_SCRUBBER_PERIOD 86400 /* ~24 hours */ 75 76 /* 77 * The following stuff is used to decode the ECC syndrome code so 78 * that we can figure out exactly which address/bit needed to be 79 * corrected. 80 */ 81 #define MEMECC_SYN_BIT_MASK 0x0fu 82 #define MEMECC_SYN_BANK_A (0x00u << 4) 83 #define MEMECC_SYN_BANK_B (0x01u << 4) 84 #define MEMECC_SYN_BANK_C (0x02u << 4) 85 #define MEMECC_SYN_BANK_D (0x03u << 4) 86 #define MEMECC_SYN_BANK_SHIFT 4 87 #define MEMECC_SYN_BANK_MASK 0x03u 88 #define MEMECC_SYN_CHECKBIT_ERR 0x80u 89 #define MEMECC_SYN_INVALID 0xffu 90 91 static u_int8_t memc_syn_decode[256] = { 92 MEMECC_SYN_INVALID, /* 0x00 */ 93 MEMECC_SYN_CHECKBIT_ERR | 0, /* 0x01: Checkbit 0 */ 94 MEMECC_SYN_CHECKBIT_ERR | 1, /* 0x02: Checkbit 1 */ 95 MEMECC_SYN_INVALID, /* 0x03 */ 96 MEMECC_SYN_CHECKBIT_ERR | 2, /* 0x04: Checkbit 2 */ 97 MEMECC_SYN_INVALID, /* 0x05 */ 98 MEMECC_SYN_INVALID, /* 0x06 */ 99 MEMECC_SYN_BANK_C | 10, /* 0x07: Bank C 10/26 */ 100 MEMECC_SYN_CHECKBIT_ERR | 3, /* 0x08: Checkbit 3 */ 101 MEMECC_SYN_INVALID, /* 0x09 */ 102 MEMECC_SYN_INVALID, /* 0x0a */ 103 MEMECC_SYN_BANK_C | 13, /* 0x0b: Bank C 13/29 */ 104 MEMECC_SYN_INVALID, /* 0x0c */ 105 MEMECC_SYN_BANK_D | 1, /* 0x0d: Bank D 1/17 */ 106 MEMECC_SYN_BANK_D | 2, /* 0x0e: Bank D 2/18 */ 107 MEMECC_SYN_INVALID, /* 0x0f */ 108 MEMECC_SYN_CHECKBIT_ERR | 4, /* 0x10: Checkbit 4 */ 109 MEMECC_SYN_INVALID, /* 0x11 */ 110 MEMECC_SYN_INVALID, /* 0x12 */ 111 MEMECC_SYN_BANK_C | 14, /* 0x13: Bank C 14/30 */ 112 MEMECC_SYN_INVALID, /* 0x14 */ 113 MEMECC_SYN_BANK_D | 4, /* 0x15: Bank D 4/20 */ 114 MEMECC_SYN_BANK_D | 5, /* 0x16: Bank D 5/21 */ 115 MEMECC_SYN_INVALID, /* 0x17 */ 116 MEMECC_SYN_INVALID, /* 0x18 */ 117 MEMECC_SYN_BANK_D | 8, /* 0x19: Bank D 8/24 */ 118 MEMECC_SYN_BANK_D | 9, /* 0x1a: Bank D 9/25 */ 119 MEMECC_SYN_INVALID, /* 0x1b */ 120 MEMECC_SYN_BANK_D | 10, /* 0x1c: Bank D 10/26 */ 121 MEMECC_SYN_INVALID, /* 0x1d */ 122 MEMECC_SYN_INVALID, /* 0x1e */ 123 MEMECC_SYN_INVALID, /* 0x1f */ 124 MEMECC_SYN_CHECKBIT_ERR | 5, /* 0x20: Checkbit 5 */ 125 MEMECC_SYN_INVALID, /* 0x21 */ 126 MEMECC_SYN_INVALID, /* 0x22 */ 127 MEMECC_SYN_BANK_C | 0, /* 0x23: Bank C 0/16 */ 128 MEMECC_SYN_INVALID, /* 0x24 */ 129 MEMECC_SYN_BANK_D | 7, /* 0x25: Bank D 7/23 */ 130 MEMECC_SYN_BANK_D | 6, /* 0x26: Bank D 6/22 */ 131 MEMECC_SYN_INVALID, /* 0x27 */ 132 MEMECC_SYN_INVALID, /* 0x28 */ 133 MEMECC_SYN_BANK_A | 15, /* 0x29: Bank A 15/31 */ 134 MEMECC_SYN_BANK_D | 12, /* 0x2a: Bank D 12/28 */ 135 MEMECC_SYN_INVALID, /* 0x2b */ 136 MEMECC_SYN_BANK_D | 13, /* 0x2c: Bank D 13/29 */ 137 MEMECC_SYN_INVALID, /* 0x2d */ 138 MEMECC_SYN_INVALID, /* 0x2e */ 139 MEMECC_SYN_INVALID, /* 0x2f */ 140 MEMECC_SYN_INVALID, /* 0x30 */ 141 MEMECC_SYN_BANK_A | 14, /* 0x31: Bank A 14/30 */ 142 MEMECC_SYN_BANK_A | 0, /* 0x32: Bank A 0/16 */ 143 MEMECC_SYN_INVALID, /* 0x33 */ 144 MEMECC_SYN_BANK_A | 1, /* 0x34: Bank A 1/17 */ 145 MEMECC_SYN_INVALID, /* 0x35 */ 146 MEMECC_SYN_INVALID, /* 0x36 */ 147 MEMECC_SYN_INVALID, /* 0x37 */ 148 MEMECC_SYN_BANK_A | 2, /* 0x38: Bank A 2/18 */ 149 MEMECC_SYN_INVALID, /* 0x39 */ 150 MEMECC_SYN_INVALID, /* 0x3a */ 151 MEMECC_SYN_INVALID, /* 0x3b */ 152 MEMECC_SYN_INVALID, /* 0x3c */ 153 MEMECC_SYN_BANK_C | 3, /* 0x3d: Bank C 3/19 */ 154 MEMECC_SYN_INVALID, /* 0x3e */ 155 MEMECC_SYN_INVALID, /* 0x3f */ 156 MEMECC_SYN_CHECKBIT_ERR | 6, /* 0x40: Checkbit 6 */ 157 MEMECC_SYN_INVALID, /* 0x41 */ 158 MEMECC_SYN_INVALID, /* 0x42 */ 159 MEMECC_SYN_BANK_C | 1, /* 0x43: Bank C 1/17 */ 160 MEMECC_SYN_INVALID, /* 0x44 */ 161 MEMECC_SYN_BANK_C | 4, /* 0x45: Bank C 4/20 */ 162 MEMECC_SYN_BANK_C | 8, /* 0x46: Bank C 8/24 */ 163 MEMECC_SYN_INVALID, /* 0x47 */ 164 MEMECC_SYN_INVALID, /* 0x48 */ 165 MEMECC_SYN_BANK_C | 7, /* 0x49: Bank C 7/23 */ 166 MEMECC_SYN_BANK_D | 15, /* 0x4a: Bank D 15/31 */ 167 MEMECC_SYN_INVALID, /* 0x4b */ 168 MEMECC_SYN_BANK_D | 14, /* 0x4c: Bank D 14/30 */ 169 MEMECC_SYN_INVALID, /* 0x4d */ 170 MEMECC_SYN_INVALID, /* 0x4e */ 171 MEMECC_SYN_BANK_B | 3, /* 0x4f: Bank B 3/19 */ 172 MEMECC_SYN_INVALID, /* 0x50 */ 173 MEMECC_SYN_BANK_B | 4, /* 0x51: Bank B 4/20 */ 174 MEMECC_SYN_BANK_B | 7, /* 0x52: Bank B 7/23 */ 175 MEMECC_SYN_INVALID, /* 0x53 */ 176 MEMECC_SYN_BANK_A | 4, /* 0x54: Bank A 4/20 */ 177 MEMECC_SYN_INVALID, /* 0x55 */ 178 MEMECC_SYN_INVALID, /* 0x56 */ 179 MEMECC_SYN_INVALID, /* 0x57 */ 180 MEMECC_SYN_BANK_A | 5, /* 0x58: Bank A 5/21 */ 181 MEMECC_SYN_INVALID, /* 0x59 */ 182 MEMECC_SYN_INVALID, /* 0x5a */ 183 MEMECC_SYN_INVALID, /* 0x5b */ 184 MEMECC_SYN_INVALID, /* 0x5c */ 185 MEMECC_SYN_INVALID, /* 0x5d */ 186 MEMECC_SYN_INVALID, /* 0x5e */ 187 MEMECC_SYN_INVALID, /* 0x5f */ 188 MEMECC_SYN_INVALID, /* 0x60 */ 189 MEMECC_SYN_BANK_B | 5, /* 0x61: Bank B 5/21 */ 190 MEMECC_SYN_BANK_B | 6, /* 0x62: Bank B 6/22 */ 191 MEMECC_SYN_INVALID, /* 0x63 */ 192 MEMECC_SYN_BANK_A | 8, /* 0x64: Bank A 8/24 */ 193 MEMECC_SYN_INVALID, /* 0x65 */ 194 MEMECC_SYN_INVALID, /* 0x66 */ 195 MEMECC_SYN_INVALID, /* 0x67 */ 196 MEMECC_SYN_BANK_A | 9, /* 0x68: Bank A 9/25 */ 197 MEMECC_SYN_INVALID, /* 0x69 */ 198 MEMECC_SYN_INVALID, /* 0x6a */ 199 MEMECC_SYN_INVALID, /* 0x6b */ 200 MEMECC_SYN_INVALID, /* 0x6c */ 201 MEMECC_SYN_INVALID, /* 0x6d */ 202 MEMECC_SYN_INVALID, /* 0x6e */ 203 MEMECC_SYN_INVALID, /* 0x6f */ 204 MEMECC_SYN_BANK_A | 10, /* 0x70: Bank A 10/26 */ 205 MEMECC_SYN_INVALID, /* 0x71 */ 206 MEMECC_SYN_INVALID, /* 0x72 */ 207 MEMECC_SYN_INVALID, /* 0x73 */ 208 MEMECC_SYN_INVALID, /* 0x74 */ 209 MEMECC_SYN_INVALID, /* 0x75 */ 210 MEMECC_SYN_INVALID, /* 0x76 */ 211 MEMECC_SYN_INVALID, /* 0x77 */ 212 MEMECC_SYN_INVALID, /* 0x78 */ 213 MEMECC_SYN_INVALID, /* 0x79 */ 214 MEMECC_SYN_BANK_C | 11, /* 0x7a: Bank C 11/27 */ 215 MEMECC_SYN_INVALID, /* 0x7b */ 216 MEMECC_SYN_INVALID, /* 0x7c */ 217 MEMECC_SYN_INVALID, /* 0x7d */ 218 MEMECC_SYN_INVALID, /* 0x7e */ 219 MEMECC_SYN_INVALID, /* 0x7f */ 220 MEMECC_SYN_CHECKBIT_ERR | 7, /* 0x80: Checkbit 7 */ 221 MEMECC_SYN_INVALID, /* 0x81 */ 222 MEMECC_SYN_INVALID, /* 0x82 */ 223 MEMECC_SYN_BANK_C | 2, /* 0x83: Bank C 2/18 */ 224 MEMECC_SYN_INVALID, /* 0x84 */ 225 MEMECC_SYN_BANK_C | 5, /* 0x85: Bank C 5/21 */ 226 MEMECC_SYN_BANK_C | 9, /* 0x86: Bank C 9/25 */ 227 MEMECC_SYN_INVALID, /* 0x87 */ 228 MEMECC_SYN_INVALID, /* 0x88 */ 229 MEMECC_SYN_BANK_C | 6, /* 0x89: Bank C 6/22 */ 230 MEMECC_SYN_BANK_C | 12, /* 0x8a: Bank C 12/28 */ 231 MEMECC_SYN_INVALID, /* 0x8b */ 232 MEMECC_SYN_BANK_D | 0, /* 0x8c: Bank D 0/16 */ 233 MEMECC_SYN_INVALID, /* 0x8d */ 234 MEMECC_SYN_INVALID, /* 0x8e */ 235 MEMECC_SYN_INVALID, /* 0x8f */ 236 MEMECC_SYN_INVALID, /* 0x90 */ 237 MEMECC_SYN_BANK_B | 8, /* 0x91: Bank B 8/24 */ 238 MEMECC_SYN_BANK_C | 15, /* 0x92: Bank C 15/31 */ 239 MEMECC_SYN_INVALID, /* 0x93 */ 240 MEMECC_SYN_BANK_A | 7, /* 0x94: Bank A 7/23 */ 241 MEMECC_SYN_INVALID, /* 0x95 */ 242 MEMECC_SYN_INVALID, /* 0x96 */ 243 MEMECC_SYN_INVALID, /* 0x97 */ 244 MEMECC_SYN_BANK_A | 6, /* 0x98: Bank A 6/22 */ 245 MEMECC_SYN_INVALID, /* 0x99 */ 246 MEMECC_SYN_INVALID, /* 0x9a */ 247 MEMECC_SYN_INVALID, /* 0x9b */ 248 MEMECC_SYN_INVALID, /* 0x9c */ 249 MEMECC_SYN_INVALID, /* 0x9d */ 250 MEMECC_SYN_BANK_B | 11, /* 0x9e: Bank B 11/27 */ 251 MEMECC_SYN_INVALID, /* 0x9f */ 252 MEMECC_SYN_INVALID, /* 0xa0 */ 253 MEMECC_SYN_BANK_B | 9, /* 0xa1: Bank B 9/25 */ 254 MEMECC_SYN_BANK_B | 12, /* 0xa2: Bank B 12/28 */ 255 MEMECC_SYN_INVALID, /* 0xa3 */ 256 MEMECC_SYN_BANK_B | 15, /* 0xa4: Bank B 15/31 */ 257 MEMECC_SYN_INVALID, /* 0xa5 */ 258 MEMECC_SYN_INVALID, /* 0xa6 */ 259 MEMECC_SYN_BANK_A | 11, /* 0xa7: Bank A 11/27 */ 260 MEMECC_SYN_BANK_A | 12, /* 0xa8: Bank A 12/28 */ 261 MEMECC_SYN_INVALID, /* 0xa9 */ 262 MEMECC_SYN_INVALID, /* 0xaa */ 263 MEMECC_SYN_INVALID, /* 0xab */ 264 MEMECC_SYN_INVALID, /* 0xac */ 265 MEMECC_SYN_INVALID, /* 0xad */ 266 MEMECC_SYN_INVALID, /* 0xae */ 267 MEMECC_SYN_INVALID, /* 0xaf */ 268 MEMECC_SYN_BANK_A | 13, /* 0xb0: Bank A 13/29 */ 269 MEMECC_SYN_INVALID, /* 0xb1 */ 270 MEMECC_SYN_INVALID, /* 0xb2 */ 271 MEMECC_SYN_INVALID, /* 0xb3 */ 272 MEMECC_SYN_INVALID, /* 0xb4 */ 273 MEMECC_SYN_INVALID, /* 0xb5 */ 274 MEMECC_SYN_INVALID, /* 0xb6 */ 275 MEMECC_SYN_INVALID, /* 0xb7 */ 276 MEMECC_SYN_INVALID, /* 0xb8 */ 277 MEMECC_SYN_INVALID, /* 0xb9 */ 278 MEMECC_SYN_INVALID, /* 0xba */ 279 MEMECC_SYN_INVALID, /* 0xbb */ 280 MEMECC_SYN_INVALID, /* 0xbc */ 281 MEMECC_SYN_INVALID, /* 0xbd */ 282 MEMECC_SYN_INVALID, /* 0xbe */ 283 MEMECC_SYN_INVALID, /* 0xbf */ 284 MEMECC_SYN_INVALID, /* 0xc0 */ 285 MEMECC_SYN_BANK_B | 10, /* 0xc1: Bank B 10/26 */ 286 MEMECC_SYN_BANK_B | 13, /* 0xc2: Bank B 13/29 */ 287 MEMECC_SYN_INVALID, /* 0xc3 */ 288 MEMECC_SYN_BANK_B | 14, /* 0xc4: Bank B 14/30 */ 289 MEMECC_SYN_INVALID, /* 0xc5 */ 290 MEMECC_SYN_INVALID, /* 0xc6 */ 291 MEMECC_SYN_INVALID, /* 0xc7 */ 292 MEMECC_SYN_BANK_B | 0, /* 0xc8: Bank B 0/16 */ 293 MEMECC_SYN_INVALID, /* 0xc9 */ 294 MEMECC_SYN_INVALID, /* 0xca */ 295 MEMECC_SYN_INVALID, /* 0xcb */ 296 MEMECC_SYN_INVALID, /* 0xcc */ 297 MEMECC_SYN_INVALID, /* 0xcd */ 298 MEMECC_SYN_INVALID, /* 0xce */ 299 MEMECC_SYN_INVALID, /* 0xcf */ 300 MEMECC_SYN_BANK_B | 1, /* 0xd0: Bank B 1/17 */ 301 MEMECC_SYN_INVALID, /* 0xd1 */ 302 MEMECC_SYN_INVALID, /* 0xd2 */ 303 MEMECC_SYN_BANK_A | 3, /* 0xd3: Bank A 3/19 */ 304 MEMECC_SYN_INVALID, /* 0xd4 */ 305 MEMECC_SYN_INVALID, /* 0xd5 */ 306 MEMECC_SYN_INVALID, /* 0xd6 */ 307 MEMECC_SYN_INVALID, /* 0xd7 */ 308 MEMECC_SYN_INVALID, /* 0xd8 */ 309 MEMECC_SYN_INVALID, /* 0xd9 */ 310 MEMECC_SYN_INVALID, /* 0xda */ 311 MEMECC_SYN_INVALID, /* 0xdb */ 312 MEMECC_SYN_INVALID, /* 0xdc */ 313 MEMECC_SYN_INVALID, /* 0xdd */ 314 MEMECC_SYN_INVALID, /* 0xde */ 315 MEMECC_SYN_INVALID, /* 0xdf */ 316 MEMECC_SYN_BANK_B | 2, /* 0xe0: Bank B 2/18 */ 317 MEMECC_SYN_INVALID, /* 0xe1 */ 318 MEMECC_SYN_INVALID, /* 0xe2 */ 319 MEMECC_SYN_INVALID, /* 0xe3 */ 320 MEMECC_SYN_INVALID, /* 0xe4 */ 321 MEMECC_SYN_INVALID, /* 0xe5 */ 322 MEMECC_SYN_INVALID, /* 0xe6 */ 323 MEMECC_SYN_INVALID, /* 0xe7 */ 324 MEMECC_SYN_INVALID, /* 0xe8 */ 325 MEMECC_SYN_BANK_D | 11, /* 0xe9: Bank D 11/27 */ 326 MEMECC_SYN_INVALID, /* 0xea */ 327 MEMECC_SYN_INVALID, /* 0xeb */ 328 MEMECC_SYN_INVALID, /* 0xec */ 329 MEMECC_SYN_INVALID, /* 0xed */ 330 MEMECC_SYN_INVALID, /* 0xee */ 331 MEMECC_SYN_INVALID, /* 0xef */ 332 MEMECC_SYN_INVALID, /* 0xf0 */ 333 MEMECC_SYN_INVALID, /* 0xf1 */ 334 MEMECC_SYN_INVALID, /* 0xf2 */ 335 MEMECC_SYN_INVALID, /* 0xf3 */ 336 MEMECC_SYN_BANK_D | 3, /* 0xf4: Bank D 3/19 */ 337 MEMECC_SYN_INVALID, /* 0xf5 */ 338 MEMECC_SYN_INVALID, /* 0xf6 */ 339 MEMECC_SYN_INVALID, /* 0xf7 */ 340 MEMECC_SYN_INVALID, /* 0xf8 */ 341 MEMECC_SYN_INVALID, /* 0xf9 */ 342 MEMECC_SYN_INVALID, /* 0xfa */ 343 MEMECC_SYN_INVALID, /* 0xfb */ 344 MEMECC_SYN_INVALID, /* 0xfc */ 345 MEMECC_SYN_INVALID, /* 0xfd */ 346 MEMECC_SYN_INVALID, /* 0xfe */ 347 MEMECC_SYN_INVALID /* 0xff */ 348 }; 349 350 351 /* ARGSUSED */ 352 void 353 memc_init(sc) 354 struct memc_softc *sc; 355 { 356 u_int8_t chipid; 357 u_int8_t memcfg; 358 359 if (memc_softc_count == MEMC_NDEVS) 360 panic("memc_attach: too many memc devices!"); 361 362 memc_softcs[memc_softc_count++] = sc; 363 364 chipid = memc_reg_read(sc, MEMC_REG_CHIP_ID); 365 memcfg = memc_reg_read(sc, MEMC_REG_MEMORY_CONFIG); 366 367 printf(": %dMB %s Memory Controller Chip (Rev %d)\n", 368 MEMC_MEMORY_CONFIG_2_MB(memcfg), 369 (chipid == MEMC_CHIP_ID_MEMC040) ? "Parity" : "ECC", 370 memc_reg_read(sc, MEMC_REG_CHIP_REVISION)); 371 372 printf("%s: Base Address: 0x%x, ", sc->sc_dev.dv_xname, 373 MEMC_BASE_ADDRESS(memc_reg_read(sc, MEMC_REG_BASE_ADDRESS_HI), 374 memc_reg_read(sc, MEMC_REG_BASE_ADDRESS_LO))); 375 376 printf("Fast RAM Read %sabled\n", (memc_reg_read(sc, 377 MEMC_REG_MEMORY_CONFIG) & MEMC_MEMORY_CONFIG_FSTRD) ? 378 "En" : "Dis"); 379 380 switch (chipid) { 381 case MEMC_CHIP_ID_MEMC040: 382 memc040_attach(sc); 383 break; 384 case MEMC_CHIP_ID_MEMECC: 385 memecc_attach(sc); 386 break; 387 } 388 } 389 390 static void 391 memc040_attach(struct memc_softc *sc) 392 { 393 394 /* XXX: TBD */ 395 } 396 397 static void 398 memecc_attach(struct memc_softc *sc) 399 { 400 u_int8_t rv; 401 402 /* 403 * First, disable bus-error and interrupts on ECC errors. 404 * Also switch off SWAIT to enhance performance. 405 */ 406 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL); 407 rv &= ~(MEMECC_DRAM_CONTROL_NCEBEN | 408 MEMECC_DRAM_CONTROL_NCEIEN | 409 MEMECC_DRAM_CONTROL_SWAIT); 410 rv |= MEMECC_DRAM_CONTROL_RAMEN; 411 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL, rv); 412 rv = memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL); 413 rv &= ~(MEMECC_SCRUB_CONTROL_SCRBEN | MEMECC_SCRUB_CONTROL_SBEIEN); 414 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL, rv); 415 416 /* 417 * Ensure error correction is enabled 418 */ 419 rv = memc_reg_read(sc, MEMECC_REG_DATA_CONTROL); 420 rv &= ~MEMECC_DATA_CONTROL_DERC; 421 memc_reg_write(sc, MEMECC_REG_DATA_CONTROL, rv); 422 423 /* 424 * Clear any error currently in the logs 425 */ 426 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER); 427 #ifdef DIAGNOSTIC 428 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) 429 memecc_log_error(sc, rv, 0, 0); 430 #endif 431 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER, 432 MEMECC_ERROR_LOGGER_ERRLOG); 433 434 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER + 2); 435 #ifdef DIAGNOSTIC 436 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) 437 memecc_log_error(sc, rv, 2, 0); 438 #endif 439 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER + 2, 440 MEMECC_ERROR_LOGGER_ERRLOG); 441 442 /* 443 * Now hook the ECC error interrupt 444 */ 445 if (memc_softc_count == 1) 446 memc_hook_error_intr(sc, memecc_err_intr); 447 448 /* 449 * Enable bus-error and interrupt on uncorrectable ECC 450 */ 451 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL); 452 rv |= MEMECC_DRAM_CONTROL_NCEBEN | MEMECC_DRAM_CONTROL_NCEIEN; 453 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL, rv); 454 455 /* 456 * Set up the scrubber to run roughly once every 24 hours 457 * with minimal impact on the local bus. With these on/off 458 * time settings, a scrub of a 32MB DRAM board will take 459 * roughly half a minute. 460 */ 461 memc_reg_write(sc, MEMECC_REG_SCRUB_PERIOD_HI, 462 MEMECC_SCRUB_PERIOD_HI(MEMECC_SCRUBBER_PERIOD)); 463 memc_reg_write(sc, MEMECC_REG_SCRUB_PERIOD_LO, 464 MEMECC_SCRUB_PERIOD_LO(MEMECC_SCRUBBER_PERIOD)); 465 memc_reg_write(sc, MEMECC_REG_SCRUB_TIME_ONOFF, 466 MEMECC_SCRUB_TIME_ON_1 | MEMECC_SCRUB_TIME_OFF_16); 467 468 /* 469 * Start the scrubber, and enable interrupts on Correctable errors 470 */ 471 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL, 472 memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL) | 473 MEMECC_SCRUB_CONTROL_SCRBEN | MEMECC_SCRUB_CONTROL_SBEIEN); 474 475 printf("%s: Logging ECC errors at ipl %d\n", sc->sc_dev.dv_xname, 476 MEMC_IRQ_LEVEL); 477 } 478 479 static void 480 memc_hook_error_intr(struct memc_softc *sc, int (*func)(void *)) 481 { 482 483 #if 0 484 evcnt_attach_dynamic(&sc->sc_evcnt, EVCNT_TYPE_INTR, 485 (*sc->sc_isrevcnt)(sc->sc_isrcookie, MEMC_IRQ_LEVEL), 486 "memory", "ecc errors"); 487 #endif 488 489 /* 490 * On boards without a VMEChip2, the interrupt is routed 491 * via the MCChip (mvme162/mvme172). 492 */ 493 if (vmetwo_not_present) 494 pcctwointr_establish(MCCHIPV_PARITY_ERR, func, MEMC_IRQ_LEVEL, 495 sc, &sc->sc_evcnt); 496 else 497 vmetwo_local_intr_establish(MEMC_IRQ_LEVEL, 498 VME2_VEC_PARITY_ERROR, func, sc, &sc->sc_evcnt); 499 } 500 501 /* ARGSUSED */ 502 static int 503 memecc_err_intr(void *arg) 504 { 505 struct memc_softc *sc; 506 u_int8_t rv; 507 int i, j, cnt = 0; 508 509 /* 510 * For each memory controller we found ... 511 */ 512 for (i = 0; i < memc_softc_count; i++) { 513 sc = memc_softcs[i]; 514 515 /* 516 * There are two error loggers per controller, the registers of 517 * the 2nd are offset from the 1st by 2 bytes. 518 */ 519 for (j = 0; j <= 2; j += 2) { 520 rv = memc_reg_read(sc, MEMECC_REG_ERROR_LOGGER + j); 521 if ((rv & MEMECC_ERROR_LOGGER_MASK) != 0) { 522 memecc_log_error(sc, rv, j, 1); 523 memc_reg_write(sc, MEMECC_REG_ERROR_LOGGER + j, 524 MEMECC_ERROR_LOGGER_ERRLOG); 525 cnt++; 526 } 527 } 528 } 529 530 return (cnt); 531 } 532 533 /* 534 * Log an ECC error to the console. 535 * Note: Since this usually runs at an elevated ipl (above clock), we 536 * should probably schedule a soft interrupt to log the error details. 537 * (But only for errors where we would not normally panic.) 538 */ 539 static void 540 memecc_log_error(struct memc_softc *sc, u_int8_t errlog, int off, int mbepanic) 541 { 542 u_int32_t addr; 543 u_int8_t rv, syndrome; 544 const char *bm = "CPU"; 545 const char *rdwr; 546 const char *etype; 547 char syntext[32]; 548 549 /* 550 * Get the address associated with the error. 551 */ 552 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_HIHI + off); 553 addr = (u_int32_t)rv; 554 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_HI + off); 555 addr = (addr << 8) | (u_int32_t)rv; 556 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_MID + off); 557 addr = (addr << 8) | (u_int32_t)rv; 558 rv = memc_reg_read(sc, MEMECC_REG_ERROR_ADDRESS_LO + off); 559 addr = (addr << 8) | (u_int32_t)rv; 560 561 /* 562 * And the Syndrome bits 563 */ 564 syndrome = memc_reg_read(sc, MEMECC_REG_ERROR_SYNDROME + off); 565 566 rdwr = ((errlog & MEMECC_ERROR_LOGGER_ERD) != 0) ? " read" : " write"; 567 568 if ((errlog & MEMECC_ERROR_LOGGER_EALT) != 0) 569 bm = "Peripheral Device"; 570 else 571 if ((errlog & MEMECC_ERROR_LOGGER_ESCRB) != 0) { 572 bm = "Scrubber"; 573 rdwr = ""; 574 } 575 576 if ((errlog & MEMECC_ERROR_LOGGER_SBE) != 0) { 577 int syncode, bank, bitnum; 578 579 etype = "Correctable"; 580 syncode = memc_syn_decode[syndrome]; 581 bitnum = (syncode & MEMECC_SYN_BIT_MASK) + (off ? 16 : 0); 582 bank = (syncode >> MEMECC_SYN_BANK_SHIFT) &MEMECC_SYN_BANK_MASK; 583 584 if (syncode == MEMECC_SYN_INVALID) 585 strcpy(syntext, "Invalid!"); 586 else 587 if ((syncode & MEMECC_SYN_CHECKBIT_ERR) != 0) 588 sprintf(syntext, "Checkbit#%d", bitnum); 589 else { 590 addr |= (u_int32_t) (bank << 2); 591 sprintf(syntext, "DRAM Bank %c, Bit#%d", 592 'A' + bank, bitnum); 593 } 594 } else if ((errlog & MEMECC_ERROR_LOGGER_MBE) != 0) 595 etype = "Uncorrectable"; 596 else 597 etype = "Spurious"; 598 599 printf("%s: %s error on %s%s access to 0x%08x.\n", 600 sc->sc_dev.dv_xname, etype, bm, rdwr, addr); 601 602 if ((errlog & MEMECC_ERROR_LOGGER_SBE) != 0) 603 printf("%s: ECC Syndrome 0x%02x (%s)\n", sc->sc_dev.dv_xname, 604 syndrome, syntext); 605 606 /* 607 * If an uncorrectable error was detected by an alternate 608 * bus master or the scrubber, panic immediately. 609 * We can't rely on the contents of memory at this point. 610 * 611 * Uncorrectable errors detected when the CPU was accessing 612 * DRAM will cause the CPU to take a bus error trap. Depending 613 * on whether the error was in kernel or user mode, the system 614 * with either panic or kill the affected process. Basically, 615 * we don't have to deal with it here. 616 * 617 * XXX: I'm not sure whether it's our responsibility to 618 * perform some dummy writes to the offending address in this 619 * case to re-generate a good ECC. Note that we'd have to write 620 * an entire block of 4 words since we can only narrow down the 621 * faulty address for correctable errors... 622 */ 623 if (mbepanic && (errlog & MEMECC_ERROR_LOGGER_MBE) && 624 (errlog & (MEMECC_ERROR_LOGGER_ESCRB|MEMECC_ERROR_LOGGER_EALT))) { 625 /* 626 * Ensure we don't get a Bus Error while panicing... 627 */ 628 rv = memc_reg_read(sc, MEMECC_REG_DRAM_CONTROL + off); 629 rv &= ~(MEMECC_DRAM_CONTROL_NCEBEN | 630 MEMECC_DRAM_CONTROL_NCEIEN); 631 memc_reg_write(sc, MEMECC_REG_DRAM_CONTROL + off, rv); 632 rv = memc_reg_read(sc, MEMECC_REG_SCRUB_CONTROL + off); 633 rv &= ~(MEMECC_SCRUB_CONTROL_SBEIEN | 634 MEMECC_SCRUB_CONTROL_SCRBEN); 635 memc_reg_write(sc, MEMECC_REG_SCRUB_CONTROL + off, rv); 636 637 panic("%s: Halting system to preserve data integrity.", 638 sc->sc_dev.dv_xname); 639 } 640 } 641
Indexes created Mon Sep 22 13:09:51 GMT 2025