nvmm_x86.c revision 1.1
1 /* $NetBSD: nvmm_x86.c,v 1.1 2019/02/23 12:27:00 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.1 2019/02/23 12:27:00 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/cpu.h> 39 40 #include <uvm/uvm.h> 41 #include <uvm/uvm_page.h> 42 43 #include <x86/cputypes.h> 44 #include <x86/specialreg.h> 45 #include <x86/pmap.h> 46 47 #include <dev/nvmm/nvmm.h> 48 #include <dev/nvmm/nvmm_internal.h> 49 #include <dev/nvmm/x86/nvmm_x86.h> 50 51 /* 52 * Code shared between x86-SVM and x86-VMX. 53 */ 54 55 const struct nvmm_x64_state nvmm_x86_reset_state = { 56 .segs = { 57 [NVMM_X64_SEG_CS] = { 58 .selector = 0xF000, 59 .base = 0xFFFF0000, 60 .limit = 0xFFFF, 61 .attrib = { 62 .type = SDT_MEMRWA, 63 .p = 1, 64 } 65 }, 66 [NVMM_X64_SEG_DS] = { 67 .selector = 0x0000, 68 .base = 0x00000000, 69 .limit = 0xFFFF, 70 .attrib = { 71 .type = SDT_MEMRWA, 72 .p = 1, 73 } 74 }, 75 [NVMM_X64_SEG_ES] = { 76 .selector = 0x0000, 77 .base = 0x00000000, 78 .limit = 0xFFFF, 79 .attrib = { 80 .type = SDT_MEMRWA, 81 .p = 1, 82 } 83 }, 84 [NVMM_X64_SEG_FS] = { 85 .selector = 0x0000, 86 .base = 0x00000000, 87 .limit = 0xFFFF, 88 .attrib = { 89 .type = SDT_MEMRWA, 90 .p = 1, 91 } 92 }, 93 [NVMM_X64_SEG_GS] = { 94 .selector = 0x0000, 95 .base = 0x00000000, 96 .limit = 0xFFFF, 97 .attrib = { 98 .type = SDT_MEMRWA, 99 .p = 1, 100 } 101 }, 102 [NVMM_X64_SEG_SS] = { 103 .selector = 0x0000, 104 .base = 0x00000000, 105 .limit = 0xFFFF, 106 .attrib = { 107 .type = SDT_MEMRWA, 108 .p = 1, 109 } 110 }, 111 [NVMM_X64_SEG_GDT] = { 112 .selector = 0x0000, 113 .base = 0x00000000, 114 .limit = 0xFFFF, 115 .attrib = { 116 .type = SDT_MEMRW, 117 .p = 1, 118 } 119 }, 120 [NVMM_X64_SEG_IDT] = { 121 .selector = 0x0000, 122 .base = 0x00000000, 123 .limit = 0xFFFF, 124 .attrib = { 125 .type = SDT_MEMRW, 126 .p = 1, 127 } 128 }, 129 [NVMM_X64_SEG_LDT] = { 130 .selector = 0x0000, 131 .base = 0x00000000, 132 .limit = 0xFFFF, 133 .attrib = { 134 .type = SDT_SYSLDT, 135 .p = 1, 136 } 137 }, 138 [NVMM_X64_SEG_TR] = { 139 .selector = 0x0000, 140 .base = 0x00000000, 141 .limit = 0xFFFF, 142 .attrib = { 143 .type = SDT_SYS286BSY, 144 .p = 1, 145 } 146 }, 147 }, 148 149 .gprs = { 150 [NVMM_X64_GPR_RAX] = 0x00000000, 151 [NVMM_X64_GPR_RCX] = 0x00000000, 152 [NVMM_X64_GPR_RDX] = 0x00000600, 153 [NVMM_X64_GPR_RBX] = 0x00000000, 154 [NVMM_X64_GPR_RSP] = 0x00000000, 155 [NVMM_X64_GPR_RBP] = 0x00000000, 156 [NVMM_X64_GPR_RSI] = 0x00000000, 157 [NVMM_X64_GPR_RDI] = 0x00000000, 158 [NVMM_X64_GPR_R8] = 0x00000000, 159 [NVMM_X64_GPR_R9] = 0x00000000, 160 [NVMM_X64_GPR_R10] = 0x00000000, 161 [NVMM_X64_GPR_R11] = 0x00000000, 162 [NVMM_X64_GPR_R12] = 0x00000000, 163 [NVMM_X64_GPR_R13] = 0x00000000, 164 [NVMM_X64_GPR_R14] = 0x00000000, 165 [NVMM_X64_GPR_R15] = 0x00000000, 166 [NVMM_X64_GPR_RIP] = 0x0000FFF0, 167 [NVMM_X64_GPR_RFLAGS] = 0x00000002, 168 }, 169 170 .crs = { 171 [NVMM_X64_CR_CR0] = 0x60000010, 172 [NVMM_X64_CR_CR2] = 0x00000000, 173 [NVMM_X64_CR_CR3] = 0x00000000, 174 [NVMM_X64_CR_CR4] = 0x00000000, 175 [NVMM_X64_CR_CR8] = 0x00000000, 176 [NVMM_X64_CR_XCR0] = 0x00000001, 177 }, 178 179 .drs = { 180 [NVMM_X64_DR_DR0] = 0x00000000, 181 [NVMM_X64_DR_DR1] = 0x00000000, 182 [NVMM_X64_DR_DR2] = 0x00000000, 183 [NVMM_X64_DR_DR3] = 0x00000000, 184 [NVMM_X64_DR_DR6] = 0xFFFF0FF0, 185 [NVMM_X64_DR_DR7] = 0x00000400, 186 }, 187 188 .msrs = { 189 [NVMM_X64_MSR_EFER] = 0x00000000, 190 [NVMM_X64_MSR_STAR] = 0x00000000, 191 [NVMM_X64_MSR_LSTAR] = 0x00000000, 192 [NVMM_X64_MSR_CSTAR] = 0x00000000, 193 [NVMM_X64_MSR_SFMASK] = 0x00000000, 194 [NVMM_X64_MSR_KERNELGSBASE] = 0x00000000, 195 [NVMM_X64_MSR_SYSENTER_CS] = 0x00000000, 196 [NVMM_X64_MSR_SYSENTER_ESP] = 0x00000000, 197 [NVMM_X64_MSR_SYSENTER_EIP] = 0x00000000, 198 [NVMM_X64_MSR_PAT] = 199 PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WT) | 200 PATENTRY(2, PAT_UCMINUS) | PATENTRY(3, PAT_UC) | 201 PATENTRY(4, PAT_WB) | PATENTRY(5, PAT_WT) | 202 PATENTRY(6, PAT_UCMINUS) | PATENTRY(7, PAT_UC), 203 }, 204 205 .misc = { 206 [NVMM_X64_MISC_INT_SHADOW] = 0, 207 [NVMM_X64_MISC_INT_WINDOW_EXIT] = 0, 208 [NVMM_X64_MISC_NMI_WINDOW_EXIT] = 0, 209 }, 210 211 .fpu = { 212 .fx_cw = 0x0040, 213 .fx_sw = 0x0000, 214 .fx_tw = 0x55, 215 .fx_zero = 0x55, 216 .fx_mxcsr = 0x1F80, 217 } 218 }; 219
Indexes created Tue Sep 30 06:09:59 GMT 2025