| History log of /src/sys/dev/nvmm/x86/nvmm_x86.c |
| Revision | | Date | Author | Comments |
| 1.23 |
| 06-Oct-2022 |
msaitoh | Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
|
| 1.22 |
| 20-Aug-2022 |
riastradh | x86: Move page attribute table bits to x86/pat.h.
|
| 1.21 |
| 08-Sep-2020 |
maxv | nvmm: cosmetic changes
- Style.
- Explicitly include ioccom.h.
|
| 1.20 |
| 06-Sep-2020 |
riastradh | Fix fallout from previous uvm.h cleanup.
- pmap(9) needs uvm/uvm_extern.h.
- x86/pmap.h is not usable on its own; it is only usable if included
via uvm/uvm_extern.h (-> uvm/uvm_pmap.h -> machine/pmap.h).
- Make nvmm.h and nvmm_internal.h standalone.
|
| 1.19 |
| 05-Sep-2020 |
riastradh | Round of uvm.h cleanup.
The poorly named uvm.h is generally supposed to be for uvm-internal
users only.
- Narrow it to files that actually need it -- mostly files that need
to query whether curlwp is the pagedaemon, which should maybe be
exposed by an external header.
- Use uvm_extern.h where feasible and uvm_*.h for things not exposed
by it. We should split up uvm_extern.h but this will serve for now
to reduce the uvm.h dependencies.
- Use uvm_stat.h and #ifdef UVMHIST uvm.h for files that use
UVMHIST(ubchist), since ubchist is declared in uvm.h but the
reference evaporates if UVMHIST is not defined, so we reduce header
file dependencies.
- Make uvm_device.h and uvm_swap.h independently includable while
here.
ok chs@
|
| 1.18 |
| 05-Sep-2020 |
maxv | x86: fix several CPUID flags
- Rename: CPUID_PN -> CPUID_PSN
CPUID_CFLUSH -> CPUID_CLFSH
CPUID_SBF -> CPUID_PBE
CPUID_LZCNT -> CPUID_ABM
CPUID_P1GB -> CPUID_PAGE1GB
CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
CPUID2_CID -> CPUID2_CNXTID
CPUID2_xTPR -> CPUID2_XTPR
CPUID2_AES -> CPUID2_AESNI
To match the x86 specification and the other OSes.
- Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
|
| 1.17 |
| 05-Sep-2020 |
maxv | nvmm: update copyright headers
|
| 1.16 |
| 04-Sep-2020 |
maxv | nvmm-x86: improve the CPUID emulation
- Mask DTES64, DS_CPL, CID, SDBG, xTPR, PN.
- B10, B20 and IA64 do not exist, so just remove them.
|
| 1.15 |
| 22-Aug-2020 |
maxv | nvmm-x86: hide more CPUID flags, mostly related to perf monitors
|
| 1.14 |
| 20-Aug-2020 |
maxv | nvmm-x86: improve the CPUID emulation
- x86-svm: explicitly handle 0x80000007 and 0x80000008. The latter
contains extended features we must filter out. Apply the same in
x86-vmx for symmetry.
- x86-svm: explicitly handle extended leaves until 0x8000001F, and
truncate to it.
|
| 1.13 |
| 20-Aug-2020 |
maxv | nvmm-x86: advertise the SERIALIZE instruction, available on future CPUs
|
| 1.12 |
| 11-Aug-2020 |
maxv | Hide OSPKE. NFC since the host never uses PKU, but still.
|
| 1.11 |
| 05-Aug-2020 |
maxv | Improve the CPUID emulation:
- Hide SGX*, PKU, WAITPKG, and SKINIT, because they are not supported.
- Hide HLE and RTM, part of TSX. Because TSX is just too buggy and we
cannot guarantee that it remains enabled in the guest (if for example
the host disables TSX while the guest is running). Nobody wants this
crap anyway, so bye-bye.
- Advertise FSREP_MOV, because no reason to hide it.
|
| 1.10 |
| 05-Aug-2020 |
maxv | Make it easier to understand what's going on, no functional change.
|
| 1.9 |
| 09-May-2020 |
maxv | Improve the CPUID emulation of basic leaves:
- Hide DCA and PQM, they cannot be used in guests.
- On Intel, explicitly handle each basic leaf until 0x16.
- On AMD, explicitly handle each basic leaf until 0x0D.
|
| 1.8 |
| 16-Nov-2019 |
maxv | Don't report MWAITX by default.
|
| 1.7 |
| 15-May-2019 |
maxv | branches: 1.7.2; 1.7.4;
NVMM: Expose MD_CLEAR to the guests.
|
| 1.6 |
| 06-Apr-2019 |
maxv | Replace the misc[] state by a new compressed nvmm_x64_state_intr structure,
which describes the interruptibility state of the guest.
Add evt_pending, read-only, that allows the virtualizer to know if an event
is pending.
|
| 1.5 |
| 03-Apr-2019 |
maxv | VMX: if PAT is not valid, #GP on WRMSR, rather than crashing the guest.
|
| 1.4 |
| 03-Apr-2019 |
maxv | Add MSR_TSC.
|
| 1.3 |
| 03-Mar-2019 |
maxv | Choose which CPUID bits to allow, rather than which bits to disallow. This
is clearer, and also forward compatible with future CPUs.
While here be more consistent when allowing the bits, and sync between
nvmm-amd and nvmm-intel. Also make sure to disallow AVX, because the guest
state we provide is only x86+SSE. Fixes a CentOS panic when booting on
NVMM, reported by Jared McNeill, thanks.
|
| 1.2 |
| 26-Feb-2019 |
maxv | Change the layout of the SEG state:
- Reorder it, to match the CPU encoding. This is the universal order,
also used by Qemu. Drop the seg_to_nvmm[] tables.
- Compress it. This divides its size by two.
- Rename some of its fields, to better match the x86 spec. Also, take S
out of Type, this was a NetBSD-ism that was likely confusing to other
people.
|
| 1.1 |
| 23-Feb-2019 |
maxv | Install the x86 RESET state at VCPU creation time, for convenience, so
that the libnvmm users can expect a functional VCPU right away.
|
| 1.7.4.8 |
| 15-Oct-2022 |
martin | Pull up following revision(s) (requested by msaitoh in ticket #1542):
sys/arch/x86/include/specialreg.h: revision 1.189
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.23
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192
s/shareing/sharing/. No functional change.
Add top-down slots event bit of architectural performance monitoring leaf.
Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>
Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
|
| 1.7.4.7 |
| 08-Dec-2021 |
martin | Pull up the following revisions, requested by msaitoh in ticket #1391:
sys/arch/x86/include/specialreg.h 1.171, 1.173-1.178
sys/arch/x86/x86/identcpu.c 1.106, 1.117,
1.122 via patch
sys/dev/nvmm/x86/nvmm_x86.c 1.18
sys/external/bsd/drm2/drm/drm_cache.c 1.14
sys/external/bsd/drm2/include/asm/cpufeature.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.114-1.117
- Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN
and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
and Jasper Lake.
- Add comment.
- KNF. Whitespace fix.
|
| 1.7.4.6 |
| 13-Sep-2020 |
martin | Pull up following revision(s) (requested by maxv in ticket #1077):
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.68
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.74
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.16
Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NO
bits. Initially they were the only ones there, but Intel then added other
bits we aren't interested in, and they must be filtered out.
nvmm-x86-svm: improve the handling of MSR_EFER
Intercept reads of it as well, just to mask EFER_SVME, which the guest
doesn't need to see.
nvmm-x86: improve the CPUID emulation
- Mask DTES64, DS_CPL, CID, SDBG, xTPR, PN.
- B10, B20 and IA64 do not exist, so just remove them.
|
| 1.7.4.5 |
| 29-Aug-2020 |
martin | Pull up following revision(s) (requested by maxv in ticket #1068):
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.71
sys/dev/nvmm/nvmm.c: revision 1.34
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.72
sys/dev/nvmm/nvmm.c: revision 1.35
sys/dev/nvmm/nvmm.c: revision 1.36
sys/dev/nvmm/x86/nvmm_x86_svmfunc.S: revision 1.5
sys/dev/nvmm/nvmm.c: revision 1.37
sys/dev/nvmm/x86/nvmm_x86_vmxfunc.S: revision 1.5
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.70
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.68
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.15
sys/dev/nvmm/nvmm_ioctl.h: revision 1.10
Micro-optimize: use pushq instead of pushw. To avoid LCP stalls and
unaligned stack accesses.
nvmm-x86: also flush the guest TLB when CR4.{PCIDE,SMEP} changes
nvmm: localify a variable that doesn't need to be global
nvmm: use relaxed atomics to read nmachines
nvmm-x86-svm: dedup code
nvmm-x86: hide more CPUID flags, mostly related to perf monitors
nvmm: misc improvements
- use mach->ncpus to get the number of vcpus, now that we have it
- don't forget to decrement mach->ncpus when a machine gets killed
- add more __predict_false()
nvmm-x86-svm: don't forget to intercept INVD
INVD executed in the guest can be dangerous for the host, due to CPU
caches being flushed without write-back.
nvmm: slightly clarify
nvmm: explicitly include atomic.h
|
| 1.7.4.4 |
| 26-Aug-2020 |
martin | Pull up following revision(s) (requested by maxv in ticket #1058):
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.70
sys/dev/nvmm/x86/nvmm_x86.h: revision 1.19
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.69
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.71
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.69
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.11
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.12
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.13
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.14
Improve the CPUID emulation:
- Hide SGX*, PKU, WAITPKG, and SKINIT, because they are not supported.
- Hide HLE and RTM, part of TSX. Because TSX is just too buggy and we
cannot guarantee that it remains enabled in the guest (if for example
the host disables TSX while the guest is running). Nobody wants this
crap anyway, so bye-bye.
- Advertise FSREP_MOV, because no reason to hide it.
Hide OSPKE. NFC since the host never uses PKU, but still.
Improve the CPUID emulation on nvmm-intel:
- Limit the highest extended leaf.
- Limit 0x00000007 to ECX=0, for future-proofness.
nvmm-x86-svm: improve the CPUID emulation
Limit the hypervisor range, and properly handle each basic leaf until 0xD.
nvmm-x86: advertise the SERIALIZE instruction, available on future CPUs
nvmm-x86: improve the CPUID emulation
- x86-svm: explicitly handle 0x80000007 and 0x80000008. The latter
contains extended features we must filter out. Apply the same in
x86-vmx for symmetry.
- x86-svm: explicitly handle extended leaves until 0x8000001F, and
truncate to it.
|
| 1.7.4.3 |
| 18-Aug-2020 |
martin | Pull up following revision(s) (requested by maxv in ticket #1055):
sys/dev/nvmm/nvmm.h: revision 1.13
sys/dev/nvmm/nvmm.h: revision 1.14
sys/dev/nvmm/nvmm.c: revision 1.33
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.67
sys/dev/nvmm/nvmm_internal.h: revision 1.17
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.67
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.10
Put the few x86-specific structures under #ifdef __x86_64__, for clarity.
Make it easier to understand what's going on, no functional change.
Add new field definitions.
Add new field definitions, and intercept everything, for future-proofness.
Add CTASSERT.
|
| 1.7.4.2 |
| 21-May-2020 |
martin | Pull up following revision(s) (requested by maxv in ticket #919):
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.9
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.60
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.61
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.56
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.57
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.58
sys/dev/nvmm/nvmm.c: revision 1.29
Improve the CPUID emulation of basic leaves:
- Hide DCA and PQM, they cannot be used in guests.
- On Intel, explicitly handle each basic leaf until 0x16.
- On AMD, explicitly handle each basic leaf until 0x0D.
Respect the convention for the hypervisor information: return the highest
hypervisor leaf in 0x40000000.EAX.
Improve the CPUID emulation on nvmm-intel: limit the highest basic and
hypervisor leaves.
Complete rev1.26: reset nvmm_impl to NULL in nvmm_fini().
|
| 1.7.4.1 |
| 16-Nov-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #434):
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.8
Don't report MWAITX by default.
|
| 1.7.2.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.7.2.2 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.7.2.1 |
| 15-May-2019 |
christos | file nvmm_x86.c was added on branch phil-wifi on 2019-06-10 22:07:14 +0000
|
