nvmm_x86.c revision 1.20
1 /* $NetBSD: nvmm_x86.c,v 1.20 2020/09/06 02:18:53 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net 5 * All rights reserved. 6 * 7 * This code is part of the NVMM hypervisor. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.20 2020/09/06 02:18:53 riastradh Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/cpu.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <x86/cputypes.h> 42 #include <x86/specialreg.h> 43 44 #include <dev/nvmm/nvmm.h> 45 #include <dev/nvmm/nvmm_internal.h> 46 #include <dev/nvmm/x86/nvmm_x86.h> 47 48 /* 49 * Code shared between x86-SVM and x86-VMX. 50 */ 51 52 const struct nvmm_x64_state nvmm_x86_reset_state = { 53 .segs = { 54 [NVMM_X64_SEG_ES] = { 55 .selector = 0x0000, 56 .base = 0x00000000, 57 .limit = 0xFFFF, 58 .attrib = { 59 .type = 3, 60 .s = 1, 61 .p = 1, 62 } 63 }, 64 [NVMM_X64_SEG_CS] = { 65 .selector = 0xF000, 66 .base = 0xFFFF0000, 67 .limit = 0xFFFF, 68 .attrib = { 69 .type = 3, 70 .s = 1, 71 .p = 1, 72 } 73 }, 74 [NVMM_X64_SEG_SS] = { 75 .selector = 0x0000, 76 .base = 0x00000000, 77 .limit = 0xFFFF, 78 .attrib = { 79 .type = 3, 80 .s = 1, 81 .p = 1, 82 } 83 }, 84 [NVMM_X64_SEG_DS] = { 85 .selector = 0x0000, 86 .base = 0x00000000, 87 .limit = 0xFFFF, 88 .attrib = { 89 .type = 3, 90 .s = 1, 91 .p = 1, 92 } 93 }, 94 [NVMM_X64_SEG_FS] = { 95 .selector = 0x0000, 96 .base = 0x00000000, 97 .limit = 0xFFFF, 98 .attrib = { 99 .type = 3, 100 .s = 1, 101 .p = 1, 102 } 103 }, 104 [NVMM_X64_SEG_GS] = { 105 .selector = 0x0000, 106 .base = 0x00000000, 107 .limit = 0xFFFF, 108 .attrib = { 109 .type = 3, 110 .s = 1, 111 .p = 1, 112 } 113 }, 114 [NVMM_X64_SEG_GDT] = { 115 .selector = 0x0000, 116 .base = 0x00000000, 117 .limit = 0xFFFF, 118 .attrib = { 119 .type = 2, 120 .s = 1, 121 .p = 1, 122 } 123 }, 124 [NVMM_X64_SEG_IDT] = { 125 .selector = 0x0000, 126 .base = 0x00000000, 127 .limit = 0xFFFF, 128 .attrib = { 129 .type = 2, 130 .s = 1, 131 .p = 1, 132 } 133 }, 134 [NVMM_X64_SEG_LDT] = { 135 .selector = 0x0000, 136 .base = 0x00000000, 137 .limit = 0xFFFF, 138 .attrib = { 139 .type = SDT_SYSLDT, 140 .s = 0, 141 .p = 1, 142 } 143 }, 144 [NVMM_X64_SEG_TR] = { 145 .selector = 0x0000, 146 .base = 0x00000000, 147 .limit = 0xFFFF, 148 .attrib = { 149 .type = SDT_SYS286BSY, 150 .s = 0, 151 .p = 1, 152 } 153 }, 154 }, 155 156 .gprs = { 157 [NVMM_X64_GPR_RAX] = 0x00000000, 158 [NVMM_X64_GPR_RCX] = 0x00000000, 159 [NVMM_X64_GPR_RDX] = 0x00000600, 160 [NVMM_X64_GPR_RBX] = 0x00000000, 161 [NVMM_X64_GPR_RSP] = 0x00000000, 162 [NVMM_X64_GPR_RBP] = 0x00000000, 163 [NVMM_X64_GPR_RSI] = 0x00000000, 164 [NVMM_X64_GPR_RDI] = 0x00000000, 165 [NVMM_X64_GPR_R8] = 0x00000000, 166 [NVMM_X64_GPR_R9] = 0x00000000, 167 [NVMM_X64_GPR_R10] = 0x00000000, 168 [NVMM_X64_GPR_R11] = 0x00000000, 169 [NVMM_X64_GPR_R12] = 0x00000000, 170 [NVMM_X64_GPR_R13] = 0x00000000, 171 [NVMM_X64_GPR_R14] = 0x00000000, 172 [NVMM_X64_GPR_R15] = 0x00000000, 173 [NVMM_X64_GPR_RIP] = 0x0000FFF0, 174 [NVMM_X64_GPR_RFLAGS] = 0x00000002, 175 }, 176 177 .crs = { 178 [NVMM_X64_CR_CR0] = 0x60000010, 179 [NVMM_X64_CR_CR2] = 0x00000000, 180 [NVMM_X64_CR_CR3] = 0x00000000, 181 [NVMM_X64_CR_CR4] = 0x00000000, 182 [NVMM_X64_CR_CR8] = 0x00000000, 183 [NVMM_X64_CR_XCR0] = 0x00000001, 184 }, 185 186 .drs = { 187 [NVMM_X64_DR_DR0] = 0x00000000, 188 [NVMM_X64_DR_DR1] = 0x00000000, 189 [NVMM_X64_DR_DR2] = 0x00000000, 190 [NVMM_X64_DR_DR3] = 0x00000000, 191 [NVMM_X64_DR_DR6] = 0xFFFF0FF0, 192 [NVMM_X64_DR_DR7] = 0x00000400, 193 }, 194 195 .msrs = { 196 [NVMM_X64_MSR_EFER] = 0x00000000, 197 [NVMM_X64_MSR_STAR] = 0x00000000, 198 [NVMM_X64_MSR_LSTAR] = 0x00000000, 199 [NVMM_X64_MSR_CSTAR] = 0x00000000, 200 [NVMM_X64_MSR_SFMASK] = 0x00000000, 201 [NVMM_X64_MSR_KERNELGSBASE] = 0x00000000, 202 [NVMM_X64_MSR_SYSENTER_CS] = 0x00000000, 203 [NVMM_X64_MSR_SYSENTER_ESP] = 0x00000000, 204 [NVMM_X64_MSR_SYSENTER_EIP] = 0x00000000, 205 [NVMM_X64_MSR_PAT] = 206 PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WT) | 207 PATENTRY(2, PAT_UCMINUS) | PATENTRY(3, PAT_UC) | 208 PATENTRY(4, PAT_WB) | PATENTRY(5, PAT_WT) | 209 PATENTRY(6, PAT_UCMINUS) | PATENTRY(7, PAT_UC), 210 [NVMM_X64_MSR_TSC] = 0, 211 }, 212 213 .intr = { 214 .int_shadow = 0, 215 .int_window_exiting = 0, 216 .nmi_window_exiting = 0, 217 .evt_pending = 0, 218 }, 219 220 .fpu = { 221 .fx_cw = 0x0040, 222 .fx_sw = 0x0000, 223 .fx_tw = 0x55, 224 .fx_zero = 0x55, 225 .fx_mxcsr = 0x1F80, 226 } 227 }; 228 229 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001 = { 230 .eax = ~0, 231 .ebx = ~0, 232 .ecx = 233 CPUID2_SSE3 | 234 CPUID2_PCLMULQDQ | 235 /* CPUID2_DTES64 excluded */ 236 /* CPUID2_MONITOR excluded */ 237 /* CPUID2_DS_CPL excluded */ 238 /* CPUID2_VMX excluded */ 239 /* CPUID2_SMX excluded */ 240 /* CPUID2_EST excluded */ 241 /* CPUID2_TM2 excluded */ 242 CPUID2_SSSE3 | 243 /* CPUID2_CNXTID excluded */ 244 /* CPUID2_SDBG excluded */ 245 CPUID2_FMA | 246 CPUID2_CX16 | 247 /* CPUID2_XTPR excluded */ 248 /* CPUID2_PDCM excluded */ 249 /* CPUID2_PCID excluded, but re-included in VMX */ 250 /* CPUID2_DCA excluded */ 251 CPUID2_SSE41 | 252 CPUID2_SSE42 | 253 /* CPUID2_X2APIC excluded */ 254 CPUID2_MOVBE | 255 CPUID2_POPCNT | 256 /* CPUID2_DEADLINE excluded */ 257 CPUID2_AESNI | 258 CPUID2_XSAVE | 259 CPUID2_OSXSAVE | 260 /* CPUID2_AVX excluded */ 261 CPUID2_F16C | 262 CPUID2_RDRAND, 263 /* CPUID2_RAZ excluded */ 264 .edx = 265 CPUID_FPU | 266 CPUID_VME | 267 CPUID_DE | 268 CPUID_PSE | 269 CPUID_TSC | 270 CPUID_MSR | 271 CPUID_PAE | 272 /* CPUID_MCE excluded */ 273 CPUID_CX8 | 274 CPUID_APIC | 275 CPUID_SEP | 276 /* CPUID_MTRR excluded */ 277 CPUID_PGE | 278 /* CPUID_MCA excluded */ 279 CPUID_CMOV | 280 CPUID_PAT | 281 CPUID_PSE36 | 282 /* CPUID_PSN excluded */ 283 CPUID_CLFSH | 284 /* CPUID_DS excluded */ 285 /* CPUID_ACPI excluded */ 286 CPUID_MMX | 287 CPUID_FXSR | 288 CPUID_SSE | 289 CPUID_SSE2 | 290 CPUID_SS | 291 CPUID_HTT | 292 /* CPUID_TM excluded */ 293 CPUID_PBE 294 }; 295 296 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = { 297 .eax = ~0, 298 .ebx = 299 CPUID_SEF_FSGSBASE | 300 /* CPUID_SEF_TSC_ADJUST excluded */ 301 /* CPUID_SEF_SGX excluded */ 302 CPUID_SEF_BMI1 | 303 /* CPUID_SEF_HLE excluded */ 304 /* CPUID_SEF_AVX2 excluded */ 305 CPUID_SEF_FDPEXONLY | 306 CPUID_SEF_SMEP | 307 CPUID_SEF_BMI2 | 308 CPUID_SEF_ERMS | 309 /* CPUID_SEF_INVPCID excluded, but re-included in VMX */ 310 /* CPUID_SEF_RTM excluded */ 311 /* CPUID_SEF_QM excluded */ 312 CPUID_SEF_FPUCSDS | 313 /* CPUID_SEF_MPX excluded */ 314 CPUID_SEF_PQE | 315 /* CPUID_SEF_AVX512F excluded */ 316 /* CPUID_SEF_AVX512DQ excluded */ 317 CPUID_SEF_RDSEED | 318 CPUID_SEF_ADX | 319 CPUID_SEF_SMAP | 320 /* CPUID_SEF_AVX512_IFMA excluded */ 321 CPUID_SEF_CLFLUSHOPT | 322 CPUID_SEF_CLWB, 323 /* CPUID_SEF_PT excluded */ 324 /* CPUID_SEF_AVX512PF excluded */ 325 /* CPUID_SEF_AVX512ER excluded */ 326 /* CPUID_SEF_AVX512CD excluded */ 327 /* CPUID_SEF_SHA excluded */ 328 /* CPUID_SEF_AVX512BW excluded */ 329 /* CPUID_SEF_AVX512VL excluded */ 330 .ecx = 331 CPUID_SEF_PREFETCHWT1 | 332 /* CPUID_SEF_AVX512_VBMI excluded */ 333 CPUID_SEF_UMIP | 334 /* CPUID_SEF_PKU excluded */ 335 /* CPUID_SEF_OSPKE excluded */ 336 /* CPUID_SEF_WAITPKG excluded */ 337 /* CPUID_SEF_AVX512_VBMI2 excluded */ 338 /* CPUID_SEF_CET_SS excluded */ 339 CPUID_SEF_GFNI | 340 CPUID_SEF_VAES | 341 CPUID_SEF_VPCLMULQDQ | 342 /* CPUID_SEF_AVX512_VNNI excluded */ 343 /* CPUID_SEF_AVX512_BITALG excluded */ 344 /* CPUID_SEF_AVX512_VPOPCNTDQ excluded */ 345 /* CPUID_SEF_MAWAU excluded */ 346 /* CPUID_SEF_RDPID excluded */ 347 CPUID_SEF_CLDEMOTE | 348 CPUID_SEF_MOVDIRI | 349 CPUID_SEF_MOVDIR64B, 350 /* CPUID_SEF_SGXLC excluded */ 351 /* CPUID_SEF_PKS excluded */ 352 .edx = 353 /* CPUID_SEF_AVX512_4VNNIW excluded */ 354 /* CPUID_SEF_AVX512_4FMAPS excluded */ 355 CPUID_SEF_FSREP_MOV | 356 /* CPUID_SEF_AVX512_VP2INTERSECT excluded */ 357 /* CPUID_SEF_SRBDS_CTRL excluded */ 358 CPUID_SEF_MD_CLEAR | 359 /* CPUID_SEF_TSX_FORCE_ABORT excluded */ 360 CPUID_SEF_SERIALIZE | 361 /* CPUID_SEF_HYBRID excluded */ 362 /* CPUID_SEF_TSXLDTRK excluded */ 363 /* CPUID_SEF_CET_IBT excluded */ 364 /* CPUID_SEF_IBRS excluded */ 365 /* CPUID_SEF_STIBP excluded */ 366 /* CPUID_SEF_L1D_FLUSH excluded */ 367 CPUID_SEF_ARCH_CAP 368 /* CPUID_SEF_CORE_CAP excluded */ 369 /* CPUID_SEF_SSBD excluded */ 370 }; 371 372 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001 = { 373 .eax = ~0, 374 .ebx = ~0, 375 .ecx = 376 CPUID_LAHF | 377 CPUID_CMPLEGACY | 378 /* CPUID_SVM excluded */ 379 /* CPUID_EAPIC excluded */ 380 CPUID_ALTMOVCR0 | 381 CPUID_ABM | 382 CPUID_SSE4A | 383 CPUID_MISALIGNSSE | 384 CPUID_3DNOWPF | 385 /* CPUID_OSVW excluded */ 386 /* CPUID_IBS excluded */ 387 CPUID_XOP | 388 /* CPUID_SKINIT excluded */ 389 /* CPUID_WDT excluded */ 390 /* CPUID_LWP excluded */ 391 CPUID_FMA4 | 392 CPUID_TCE | 393 /* CPUID_NODEID excluded */ 394 CPUID_TBM | 395 CPUID_TOPOEXT, 396 /* CPUID_PCEC excluded */ 397 /* CPUID_PCENB excluded */ 398 /* CPUID_SPM excluded */ 399 /* CPUID_DBE excluded */ 400 /* CPUID_PTSC excluded */ 401 /* CPUID_L2IPERFC excluded */ 402 /* CPUID_MWAITX excluded */ 403 .edx = 404 CPUID_SYSCALL | 405 CPUID_MPC | 406 CPUID_XD | 407 CPUID_MMXX | 408 CPUID_MMX | 409 CPUID_FXSR | 410 CPUID_FFXSR | 411 CPUID_PAGE1GB | 412 /* CPUID_RDTSCP excluded */ 413 CPUID_EM64T | 414 CPUID_3DNOW2 | 415 CPUID_3DNOW 416 }; 417 418 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007 = { 419 .eax = 0, 420 .ebx = 0, 421 .ecx = 0, 422 .edx = CPUID_APM_ITSC 423 }; 424 425 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008 = { 426 .eax = ~0, 427 .ebx = 428 CPUID_CAPEX_CLZERO | 429 /* CPUID_CAPEX_IRPERF excluded */ 430 CPUID_CAPEX_XSAVEERPTR | 431 /* CPUID_CAPEX_RDPRU excluded */ 432 /* CPUID_CAPEX_MCOMMIT excluded */ 433 CPUID_CAPEX_WBNOINVD, 434 .ecx = ~0, /* TODO? */ 435 .edx = 0 436 }; 437 438 bool 439 nvmm_x86_pat_validate(uint64_t val) 440 { 441 uint8_t *pat = (uint8_t *)&val; 442 size_t i; 443 444 for (i = 0; i < 8; i++) { 445 if (__predict_false(pat[i] & ~__BITS(2,0))) 446 return false; 447 if (__predict_false(pat[i] == 2 || pat[i] == 3)) 448 return false; 449 } 450 451 return true; 452 } 453
Indexes created Tue Sep 30 11:09:46 GMT 2025