nvmm_x86.c revision 1.6
1 /* $NetBSD: nvmm_x86.c,v 1.6 2019/04/06 11:49:53 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.6 2019/04/06 11:49:53 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/cpu.h> 39 40 #include <uvm/uvm.h> 41 #include <uvm/uvm_page.h> 42 43 #include <x86/cputypes.h> 44 #include <x86/specialreg.h> 45 #include <x86/pmap.h> 46 47 #include <dev/nvmm/nvmm.h> 48 #include <dev/nvmm/nvmm_internal.h> 49 #include <dev/nvmm/x86/nvmm_x86.h> 50 51 /* 52 * Code shared between x86-SVM and x86-VMX. 53 */ 54 55 const struct nvmm_x64_state nvmm_x86_reset_state = { 56 .segs = { 57 [NVMM_X64_SEG_ES] = { 58 .selector = 0x0000, 59 .base = 0x00000000, 60 .limit = 0xFFFF, 61 .attrib = { 62 .type = 3, 63 .s = 1, 64 .p = 1, 65 } 66 }, 67 [NVMM_X64_SEG_CS] = { 68 .selector = 0xF000, 69 .base = 0xFFFF0000, 70 .limit = 0xFFFF, 71 .attrib = { 72 .type = 3, 73 .s = 1, 74 .p = 1, 75 } 76 }, 77 [NVMM_X64_SEG_SS] = { 78 .selector = 0x0000, 79 .base = 0x00000000, 80 .limit = 0xFFFF, 81 .attrib = { 82 .type = 3, 83 .s = 1, 84 .p = 1, 85 } 86 }, 87 [NVMM_X64_SEG_DS] = { 88 .selector = 0x0000, 89 .base = 0x00000000, 90 .limit = 0xFFFF, 91 .attrib = { 92 .type = 3, 93 .s = 1, 94 .p = 1, 95 } 96 }, 97 [NVMM_X64_SEG_FS] = { 98 .selector = 0x0000, 99 .base = 0x00000000, 100 .limit = 0xFFFF, 101 .attrib = { 102 .type = 3, 103 .s = 1, 104 .p = 1, 105 } 106 }, 107 [NVMM_X64_SEG_GS] = { 108 .selector = 0x0000, 109 .base = 0x00000000, 110 .limit = 0xFFFF, 111 .attrib = { 112 .type = 3, 113 .s = 1, 114 .p = 1, 115 } 116 }, 117 [NVMM_X64_SEG_GDT] = { 118 .selector = 0x0000, 119 .base = 0x00000000, 120 .limit = 0xFFFF, 121 .attrib = { 122 .type = 2, 123 .s = 1, 124 .p = 1, 125 } 126 }, 127 [NVMM_X64_SEG_IDT] = { 128 .selector = 0x0000, 129 .base = 0x00000000, 130 .limit = 0xFFFF, 131 .attrib = { 132 .type = 2, 133 .s = 1, 134 .p = 1, 135 } 136 }, 137 [NVMM_X64_SEG_LDT] = { 138 .selector = 0x0000, 139 .base = 0x00000000, 140 .limit = 0xFFFF, 141 .attrib = { 142 .type = SDT_SYSLDT, 143 .s = 0, 144 .p = 1, 145 } 146 }, 147 [NVMM_X64_SEG_TR] = { 148 .selector = 0x0000, 149 .base = 0x00000000, 150 .limit = 0xFFFF, 151 .attrib = { 152 .type = SDT_SYS286BSY, 153 .s = 0, 154 .p = 1, 155 } 156 }, 157 }, 158 159 .gprs = { 160 [NVMM_X64_GPR_RAX] = 0x00000000, 161 [NVMM_X64_GPR_RCX] = 0x00000000, 162 [NVMM_X64_GPR_RDX] = 0x00000600, 163 [NVMM_X64_GPR_RBX] = 0x00000000, 164 [NVMM_X64_GPR_RSP] = 0x00000000, 165 [NVMM_X64_GPR_RBP] = 0x00000000, 166 [NVMM_X64_GPR_RSI] = 0x00000000, 167 [NVMM_X64_GPR_RDI] = 0x00000000, 168 [NVMM_X64_GPR_R8] = 0x00000000, 169 [NVMM_X64_GPR_R9] = 0x00000000, 170 [NVMM_X64_GPR_R10] = 0x00000000, 171 [NVMM_X64_GPR_R11] = 0x00000000, 172 [NVMM_X64_GPR_R12] = 0x00000000, 173 [NVMM_X64_GPR_R13] = 0x00000000, 174 [NVMM_X64_GPR_R14] = 0x00000000, 175 [NVMM_X64_GPR_R15] = 0x00000000, 176 [NVMM_X64_GPR_RIP] = 0x0000FFF0, 177 [NVMM_X64_GPR_RFLAGS] = 0x00000002, 178 }, 179 180 .crs = { 181 [NVMM_X64_CR_CR0] = 0x60000010, 182 [NVMM_X64_CR_CR2] = 0x00000000, 183 [NVMM_X64_CR_CR3] = 0x00000000, 184 [NVMM_X64_CR_CR4] = 0x00000000, 185 [NVMM_X64_CR_CR8] = 0x00000000, 186 [NVMM_X64_CR_XCR0] = 0x00000001, 187 }, 188 189 .drs = { 190 [NVMM_X64_DR_DR0] = 0x00000000, 191 [NVMM_X64_DR_DR1] = 0x00000000, 192 [NVMM_X64_DR_DR2] = 0x00000000, 193 [NVMM_X64_DR_DR3] = 0x00000000, 194 [NVMM_X64_DR_DR6] = 0xFFFF0FF0, 195 [NVMM_X64_DR_DR7] = 0x00000400, 196 }, 197 198 .msrs = { 199 [NVMM_X64_MSR_EFER] = 0x00000000, 200 [NVMM_X64_MSR_STAR] = 0x00000000, 201 [NVMM_X64_MSR_LSTAR] = 0x00000000, 202 [NVMM_X64_MSR_CSTAR] = 0x00000000, 203 [NVMM_X64_MSR_SFMASK] = 0x00000000, 204 [NVMM_X64_MSR_KERNELGSBASE] = 0x00000000, 205 [NVMM_X64_MSR_SYSENTER_CS] = 0x00000000, 206 [NVMM_X64_MSR_SYSENTER_ESP] = 0x00000000, 207 [NVMM_X64_MSR_SYSENTER_EIP] = 0x00000000, 208 [NVMM_X64_MSR_PAT] = 209 PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WT) | 210 PATENTRY(2, PAT_UCMINUS) | PATENTRY(3, PAT_UC) | 211 PATENTRY(4, PAT_WB) | PATENTRY(5, PAT_WT) | 212 PATENTRY(6, PAT_UCMINUS) | PATENTRY(7, PAT_UC), 213 [NVMM_X64_MSR_TSC] = 0, 214 }, 215 216 .intr = { 217 .int_shadow = 0, 218 .int_window_exiting = 0, 219 .nmi_window_exiting = 0, 220 .evt_pending = 0, 221 }, 222 223 .fpu = { 224 .fx_cw = 0x0040, 225 .fx_sw = 0x0000, 226 .fx_tw = 0x55, 227 .fx_zero = 0x55, 228 .fx_mxcsr = 0x1F80, 229 } 230 }; 231 232 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001 = { 233 .eax = ~0, 234 .ebx = ~0, 235 .ecx = 236 /* Excluded: MONITOR, VMX, SMX, EST, TM2, PDCM, PCID, X2APIC, 237 * DEADLINE, RAZ. */ 238 CPUID2_SSE3 | CPUID2_PCLMUL | 239 CPUID2_DTES64 | CPUID2_DS_CPL | 240 CPUID2_SSSE3 | CPUID2_CID | 241 CPUID2_SDBG | CPUID2_FMA | 242 CPUID2_CX16 | CPUID2_xTPR | 243 CPUID2_DCA | CPUID2_SSE41 | 244 CPUID2_SSE42 | CPUID2_MOVBE | 245 CPUID2_POPCNT | CPUID2_AES | 246 CPUID2_XSAVE | CPUID2_OSXSAVE | 247 CPUID2_F16C | CPUID2_RDRAND, 248 .edx = 249 /* Excluded: MCE, MTRR, MCA, DS, ACPI, TM. */ 250 CPUID_FPU | CPUID_VME | 251 CPUID_DE | CPUID_PSE | 252 CPUID_TSC | CPUID_MSR | 253 CPUID_PAE | CPUID_CX8 | 254 CPUID_APIC | CPUID_B10 | 255 CPUID_SEP | CPUID_PGE | 256 CPUID_CMOV | CPUID_PAT | 257 CPUID_PSE36 | CPUID_PN | 258 CPUID_CFLUSH | CPUID_B20 | 259 CPUID_MMX | CPUID_FXSR | 260 CPUID_SSE | CPUID_SSE2 | 261 CPUID_SS | CPUID_HTT | 262 CPUID_IA64 | CPUID_SBF 263 }; 264 265 const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = { 266 .eax = ~0, 267 .ebx = 268 /* Excluded: TSC_ADJUST, AVX2, INVPCID, AVX512*, PT, SHA. */ 269 CPUID_SEF_FSGSBASE | 270 CPUID_SEF_SGX | CPUID_SEF_BMI1 | 271 CPUID_SEF_HLE | CPUID_SEF_FDPEXONLY | 272 CPUID_SEF_SMEP | CPUID_SEF_BMI2 | 273 CPUID_SEF_ERMS | CPUID_SEF_RTM | 274 CPUID_SEF_QM | CPUID_SEF_FPUCSDS | 275 CPUID_SEF_PQE | CPUID_SEF_RDSEED | 276 CPUID_SEF_ADX | CPUID_SEF_SMAP | 277 CPUID_SEF_CLFLUSHOPT | CPUID_SEF_CLWB, 278 .ecx = 279 /* Excluded: AVX512*, MAWAU, RDPID. */ 280 CPUID_SEF_PREFETCHWT1 | CPUID_SEF_UMIP | 281 CPUID_SEF_PKU | CPUID_SEF_OSPKE | 282 CPUID_SEF_WAITPKG | CPUID_SEF_GFNI | 283 CPUID_SEF_VAES | CPUID_SEF_VPCLMULQDQ | 284 CPUID_SEF_CLDEMOTE | CPUID_SEF_MOVDIRI | 285 CPUID_SEF_MOVDIR64B | CPUID_SEF_SGXLC, 286 .edx = 287 /* Excluded: all except CAP. */ 288 CPUID_SEF_ARCH_CAP 289 }; 290 291 const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001 = { 292 .eax = ~0, 293 .ebx = ~0, 294 .ecx = 295 /* Excluded: SVM, EAPIC, OSVW. */ 296 CPUID_LAHF | CPUID_CMPLEGACY | 297 CPUID_ALTMOVCR0 | CPUID_LZCNT | 298 CPUID_SSE4A | CPUID_MISALIGNSSE | 299 CPUID_3DNOWPF | CPUID_IBS | 300 CPUID_XOP | CPUID_SKINIT | 301 CPUID_WDT | CPUID_LWP | 302 CPUID_FMA4 | CPUID_TCE | 303 CPUID_NODEID | CPUID_TBM | 304 CPUID_TOPOEXT | CPUID_PCEC | 305 CPUID_PCENB | CPUID_SPM | 306 CPUID_DBE | CPUID_PTSC | 307 CPUID_L2IPERFC | CPUID_MWAITX, 308 .edx = 309 /* Excluded: RDTSCP. */ 310 CPUID_SYSCALL | CPUID_MPC | 311 CPUID_XD | CPUID_MMXX | 312 CPUID_MMX | CPUID_FXSR | 313 CPUID_FFXSR | CPUID_P1GB | 314 CPUID_EM64T | CPUID_3DNOW2 | 315 CPUID_3DNOW 316 }; 317 318 bool 319 nvmm_x86_pat_validate(uint64_t val) 320 { 321 uint8_t *pat = (uint8_t *)&val; 322 size_t i; 323 324 for (i = 0; i < 8; i++) { 325 if (__predict_false(pat[i] & ~__BITS(2,0))) 326 return false; 327 if (__predict_false(pat[i] == 2 || pat[i] == 3)) 328 return false; 329 } 330 331 return true; 332 } 333
Indexes created Mon Sep 29 21:09:56 GMT 2025