1 /* $NetBSD: ds28e17iic.c,v 1.2 2025/09/15 13:23:03 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2025 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 20 /* Driver for the DS28E17 1-Wire to I2C bridge chip */ 21 22 /* https://www.analog.com/en/products/DS28E17.html */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ds28e17iic.c,v 1.2 2025/09/15 13:23:03 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/proc.h> 32 #include <sys/module.h> 33 #include <sys/sysctl.h> 34 35 #include <dev/onewire/onewiredevs.h> 36 #include <dev/onewire/onewirereg.h> 37 #include <dev/onewire/onewirevar.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <dev/onewire/ds28e17iicreg.h> 42 #include <dev/onewire/ds28e17iicvar.h> 43 44 static int ds28e17iic_match(device_t, cfdata_t, void *); 45 static void ds28e17iic_attach(device_t, device_t, void *); 46 static int ds28e17iic_detach(device_t, int); 47 static int ds28e17iic_activate(device_t, enum devact); 48 static int ds28e17iic_verify_sysctl(SYSCTLFN_ARGS); 49 50 #define DS28E17IIC_DEBUG 51 #ifdef DS28E17IIC_DEBUG 52 #define DPRINTF(s, l, x) \ 53 do { \ 54 if (l <= s->sc_ds28e17iicdebug) \ 55 printf x; \ 56 } while (/*CONSTCOND*/0) 57 #else 58 #define DPRINTF(s, l, x) 59 #endif 60 61 CFATTACH_DECL_NEW(ds28e17iic, sizeof(struct ds28e17iic_softc), 62 ds28e17iic_match, ds28e17iic_attach, ds28e17iic_detach, ds28e17iic_activate); 63 64 extern struct cfdriver ds28e17iic_cd; 65 66 static const struct onewire_matchfam ds28e17iic_fams[] = { 67 { ONEWIRE_FAMILY_DS28E17 }, 68 }; 69 70 71 #define READY_DELAY(d) if (d > 0) delay(d) 72 73 /* The chip uses a 16 bit CRC on the 1-Wire bus when doing any I2C transaction. 74 * But it has some strangness to it.. the CRC can be made up from a number of 75 * parts of the 1-Wire transaction, some of which are only used for some 76 * transactions. Then the result must be inverted and placed in the proper 77 * order. 78 */ 79 80 static uint16_t 81 ds28e17iic_crc16_bit(uint16_t icrc) 82 { 83 for (size_t i = 0; i < 8; i++) { 84 if (icrc & 0x01) { 85 icrc >>= 1; 86 icrc ^= 0xA001; 87 } else { 88 icrc >>= 1; 89 } 90 } 91 92 return(icrc); 93 } 94 95 static void 96 ds28e17iic_crc16(uint8_t crc16[], uint8_t cmd, uint8_t i2c_addr, uint8_t len, uint8_t *data, uint8_t len2) 97 { 98 uint16_t crc = 0; 99 100 crc ^= cmd; 101 crc = ds28e17iic_crc16_bit(crc); 102 103 /* This is a magic value which means that it should not be considered. 104 * The address will never be 0xff, but could, in theory, be 0x00, so 105 * don't use that. 106 */ 107 108 if (i2c_addr != 0xff) { 109 crc ^= i2c_addr; 110 crc = ds28e17iic_crc16_bit(crc); 111 } 112 113 crc ^= len; 114 crc = ds28e17iic_crc16_bit(crc); 115 116 if (data != NULL) { 117 for (size_t j = 0; j < len; j++) { 118 crc ^= data[j]; 119 crc = ds28e17iic_crc16_bit(crc); 120 } 121 } 122 123 if (len2 > 0) { 124 crc ^= len2; 125 crc = ds28e17iic_crc16_bit(crc); 126 } 127 128 crc = crc ^ 0xffff; 129 130 crc16[1] = crc >> 8; 131 crc16[0] = crc & 0xff; 132 } 133 134 int 135 ds28e17iic_verify_sysctl(SYSCTLFN_ARGS) 136 { 137 int error, t; 138 struct sysctlnode node; 139 140 node = *rnode; 141 t = *(int *)rnode->sysctl_data; 142 node.sysctl_data = &t; 143 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 144 if (error || newp == NULL) 145 return error; 146 147 if (t < 0) 148 return EINVAL; 149 150 *(int *)rnode->sysctl_data = t; 151 152 return 0; 153 } 154 155 /* There isn't much required to acquire or release the I2C bus, but the man 156 * pages says these are needed 157 */ 158 159 static int 160 ds28e17iic_acquire_bus(void *v, int flags) 161 { 162 return(0); 163 } 164 165 static void 166 ds28e17iic_release_bus(void *v, int flags) 167 { 168 return; 169 } 170 171 /* Perform most of a I2C transaction. Sometimes there there will be 172 * more to read from the 1-Wire bus. That is device command dependent. 173 */ 174 175 static int 176 ds28e17iic_ow_i2c_transaction(struct ds28e17iic_softc *sc, const char *what, uint8_t device_cmd, 177 uint8_t i2c_addr, uint8_t len1, uint8_t *buf1, uint8_t len2, 178 uint8_t crc16[2], uint8_t *i2c_status) 179 { 180 int err = 0; 181 int readycount; 182 uint8_t ready; 183 184 if (onewire_reset(sc->sc_onewire) != 0) { 185 err = EIO; 186 } else { 187 ds28e17iic_crc16(crc16,device_cmd,i2c_addr,len1,buf1,len2); 188 onewire_matchrom(sc->sc_onewire, sc->sc_rom); 189 onewire_write_byte(sc->sc_onewire,device_cmd); 190 if (i2c_addr != 0xff) 191 onewire_write_byte(sc->sc_onewire,i2c_addr); 192 onewire_write_byte(sc->sc_onewire,len1); 193 if (buf1 != NULL) 194 onewire_write_block(sc->sc_onewire,buf1,len1); 195 if (len2 > 0) 196 onewire_write_byte(sc->sc_onewire,len2); 197 onewire_write_block(sc->sc_onewire,crc16,2); 198 readycount=0; 199 do { 200 READY_DELAY(sc->sc_readydelay); 201 ready = onewire_read_bit(sc->sc_onewire); 202 readycount++; 203 if (readycount > sc->sc_readycount) 204 err = EAGAIN; 205 } while (ready != 0 && !err); 206 DPRINTF(sc, 3, ("%s: readycount=%d, err=%d\n", 207 what, readycount, err)); 208 *i2c_status = onewire_read_byte(sc->sc_onewire); 209 } 210 211 return(err); 212 } 213 214 /* This needs to determine what sort of write is going on. We will may make use 215 * of the fact that the chip can start a write transaction with one command and 216 * add data to it with a second command. 217 */ 218 219 static int 220 ds28e17iic_i2c_write(struct ds28e17iic_softc *sc, i2c_op_t op, i2c_addr_t addr, 221 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int flags) 222 { 223 uint8_t crc16[2]; 224 uint8_t dcmd; 225 uint8_t i2c_status; 226 uint8_t i2c_write_status; 227 uint8_t *buf; 228 size_t len; 229 uint8_t maddr; 230 int err = 0; 231 232 if (sc->sc_dying) 233 return(EIO); 234 235 /* It would be possible to support more than 256 bytes in a transfer by 236 * breaking it up and using the chip's ability to add data to a write, 237 * but that isn't currently done. 238 */ 239 240 if (cmdbuf != NULL && 241 cmdlen > 256) 242 return(ENOTSUP); 243 244 if (databuf != NULL && 245 datalen > 256) 246 return(ENOTSUP); 247 248 /* Just null out any attempt to not actually do anything, might save us 249 * a panic */ 250 251 if (cmdbuf == NULL && 252 databuf == NULL) 253 return(err); 254 255 maddr = addr << 1; 256 257 onewire_lock(sc->sc_onewire); 258 259 /* Consider two ways to do a basic write. One is where there is a 260 * cmdbuf and databuf which can use the chip's ability to add to a 261 * ongoing transaction and the other case where there is just the 262 * cmdbuf or the databuf, in which case, just figure out if a stop 263 * is needed. 264 */ 265 266 if (cmdbuf != NULL && 267 databuf != NULL) { 268 /* This chip considers a zero length write an error */ 269 if (cmdlen == 0 || 270 datalen == 0) { 271 if (sc->sc_reportzerolen) 272 device_printf(sc->sc_dv,"ds28e17iic_i2c_write: ************ called with zero length read: cmdlen: %zu, datalen: %zu ***************\n", 273 cmdlen, datalen); 274 } 275 276 /* In this case, always start out with a write without stop. */ 277 278 err = ds28e17iic_ow_i2c_transaction(sc, "ds28e17iic_i2c_write cmd and data 1", 279 DS28E17IIC_DC_WD, maddr, cmdlen, __UNCONST(cmdbuf), 0, crc16, &i2c_status); 280 if (! err) { 281 i2c_write_status = onewire_read_byte(sc->sc_onewire); 282 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: both cmd and data 1: i2c_status=%02x, i2c_write_status=%02x\n", 283 i2c_status, i2c_write_status)); 284 if (i2c_status == 0 && 285 i2c_write_status == 0) { 286 /* Add data to the transaction and maybe do a stop as well */ 287 if (I2C_OP_STOP_P(op)) 288 dcmd = DS28E17IIC_DC_WD_ONLY_WITH_STOP; 289 else 290 dcmd = DS28E17IIC_DC_WD_ONLY; 291 292 err = ds28e17iic_ow_i2c_transaction(sc, "ds28e17iic_i2c_write cmd and data 2", 293 dcmd, 0xff, datalen, databuf, 0, crc16, &i2c_status); 294 if (! err) { 295 i2c_write_status = onewire_read_byte(sc->sc_onewire); 296 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: both cmd and data 2: dcmd=%02x, i2c_status=%02x, i2c_write_status=%02x\n", 297 dcmd, i2c_status, i2c_write_status)); 298 if (i2c_status != 0 || 299 i2c_write_status != 0) 300 err = EIO; 301 } else { 302 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: cmd and data 2: err=%d\n", err)); 303 } 304 } else { 305 err = EIO; 306 } 307 } else { 308 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: cmd and data 1: err=%d\n", err)); 309 } 310 } else { 311 /* Either the cmdbuf or databuf has something, figure out which 312 * and maybe perform a stop after the write. 313 */ 314 if (cmdbuf != NULL) { 315 buf = __UNCONST(cmdbuf); 316 len = cmdlen; 317 } else { 318 buf = databuf; 319 len = datalen; 320 } 321 322 if (I2C_OP_STOP_P(op)) 323 dcmd = DS28E17IIC_DC_WD_WITH_STOP; 324 else 325 dcmd = DS28E17IIC_DC_WD; 326 327 if (len == 0) { 328 if (sc->sc_reportzerolen) 329 device_printf(sc->sc_dv,"ds28e17iic_i2c_write: ************ called with zero length read ***************\n"); 330 } 331 332 err = ds28e17iic_ow_i2c_transaction(sc, "ds28e17iic_i2c_write cmd or data", 333 dcmd, maddr, len, buf, 0, crc16, &i2c_status); 334 if (! err) { 335 i2c_write_status = onewire_read_byte(sc->sc_onewire); 336 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: cmd or data: dcmd=%02x, i2c_status=%02x, i2c_write_status=%02x\n", 337 dcmd, i2c_status, i2c_write_status)); 338 if (i2c_status != 0 || 339 i2c_write_status != 0) 340 err = EIO; 341 } else { 342 DPRINTF(sc, 2, ("ds28e17iic_i2c_write: cmd or data: err=%d\n", err)); 343 } 344 } 345 346 onewire_unlock(sc->sc_onewire); 347 348 return(err); 349 } 350 351 /* This deals with the situation where the desire is just to read from 352 * the device. The chip does not support Read without Stop, so turn 353 * that into a Read with Stop and hope for the best. 354 */ 355 356 static int 357 ds28e17iic_i2c_read(struct ds28e17iic_softc *sc, i2c_op_t op, i2c_addr_t addr, 358 void *databuf, size_t datalen, int flags) 359 { 360 uint8_t crc16[2]; 361 uint8_t i2c_status; 362 uint8_t maddr; 363 int err = 0; 364 365 if (sc->sc_dying) 366 return(EIO); 367 368 /* It does not appear that it is possible to read more than 256 bytes */ 369 370 if (databuf != NULL && 371 datalen > 256) 372 return(ENOTSUP); 373 374 /* Just null out the attempt to not really read anything */ 375 376 if (databuf == NULL) 377 return(err); 378 379 maddr = (addr << 1) | 0x01; 380 381 onewire_lock(sc->sc_onewire); 382 383 /* Same thing as a write, a zero length read is considered an error */ 384 385 if (datalen == 0) 386 if (sc->sc_reportzerolen) 387 device_printf(sc->sc_dv,"ds28e17iic_i2c_read: ************ called with zero length read ***************\n"); 388 389 if (!I2C_OP_STOP_P(op) && 390 sc->sc_reportreadnostop) 391 device_printf(sc->sc_dv,"ds28e17iic_i2c_read: ************ called with READ without STOP ***************\n"); 392 393 err = ds28e17iic_ow_i2c_transaction(sc, "ds28e17iic_i2c_read", 394 DS28E17IIC_DC_RD_WITH_STOP, maddr, datalen, 395 NULL, 0, crc16, &i2c_status); 396 if (! err) { 397 DPRINTF(sc, 2, ("ds28e17iic_i2c_read: i2c_status=%02x\n", i2c_status)); 398 if (i2c_status == 0) { 399 onewire_read_block(sc->sc_onewire, databuf, datalen); 400 } else { 401 err = EIO; 402 } 403 } else { 404 DPRINTF(sc, 2, ("ds28e17iic_i2c_read: err=%d\n", err)); 405 } 406 407 onewire_unlock(sc->sc_onewire); 408 409 return(err); 410 } 411 412 /* This deals with the situation where the desire is to write something to 413 * the device and then read some stuff back. The chip does not support Read 414 * without Stop, so turn that into a Read with Stop and hope for the best. 415 */ 416 417 static int 418 ds28e17iic_i2c_write_read(struct ds28e17iic_softc *sc, i2c_op_t op, i2c_addr_t addr, 419 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int flags) 420 { 421 uint8_t crc16[2]; 422 uint8_t i2c_status; 423 uint8_t i2c_write_status; 424 uint8_t maddr; 425 int err = 0; 426 427 if (sc->sc_dying) 428 return(EIO); 429 430 /* When using the write+read command of the chip, it does not appear to be 431 * possible to read more than 256 bytes, or write more than 256 bytes in a 432 * transaction. 433 */ 434 435 if (cmdbuf != NULL && 436 cmdlen > 256) 437 return(ENOTSUP); 438 439 if (databuf != NULL && 440 datalen > 256) 441 return(ENOTSUP); 442 443 /* Just return if asked to not actually do anything */ 444 445 if (cmdbuf == NULL && 446 databuf == NULL) 447 return(err); 448 449 maddr = addr << 1; 450 451 /* Same as a single read or write, a zero length anything here is 452 * considered an error. 453 */ 454 455 if (cmdlen == 0 || 456 datalen == 0) { 457 if (sc->sc_reportzerolen) 458 device_printf(sc->sc_dv,"ds28e17iic_i2c_write_read: ************ called with zero length read: cmdlen: %zu, datalen: %zu ***************\n", 459 cmdlen, datalen); 460 } 461 462 if (!I2C_OP_STOP_P(op) && 463 sc->sc_reportreadnostop) 464 device_printf(sc->sc_dv,"ds28e17iic_i2c_write_read: ************ called with READ without STOP ***************\n"); 465 466 onewire_lock(sc->sc_onewire); 467 468 err = ds28e17iic_ow_i2c_transaction(sc, "ds28e17iic_i2c_write_read", 469 DS28E17IIC_DC_WD_RD_WITH_STOP, maddr, cmdlen, 470 __UNCONST(cmdbuf), datalen, crc16, &i2c_status); 471 if (! err) { 472 /* Like with the normal write, even if the i2c_status is not zero, 473 * we have to read the write status too. It will end up being 474 * the value 0xff. */ 475 i2c_write_status = onewire_read_byte(sc->sc_onewire); 476 DPRINTF(sc, 2, ("ds28e17iic_i2c_write_read: i2c_status=%02x, i2c_write_status=%02x\n", 477 i2c_status, i2c_write_status)); 478 /* However, don't bother trying to read the data block if there was an error */ 479 if (i2c_status == 0 && 480 i2c_write_status == 0) { 481 onewire_read_block(sc->sc_onewire, databuf, datalen); 482 } else { 483 err = EIO; 484 } 485 } else { 486 DPRINTF(sc, 2, ("ds28e17iic_i2c_write_read: err=%d\n", err)); 487 } 488 489 onewire_unlock(sc->sc_onewire); 490 491 return(err); 492 } 493 494 /* This needs to figure out what sort of thing is being sent to the end device. 495 * The chip will help out with some of this. 496 */ 497 498 static int 499 ds28e17iic_i2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 500 size_t cmdlen, void *databuf, size_t datalen, int flags) 501 { 502 struct ds28e17iic_softc *sc = v; 503 int err = 0; 504 505 if (sc->sc_dying) 506 return(EIO); 507 508 /* The chip only supports 7 bit addressing */ 509 510 if (addr > 0x7f) 511 return (ENOTSUP); 512 513 /* XXX - this driver could support setting the speed for this I2C 514 * transaction as that information is in the flags, but nothing really 515 * asks to do that, so just ignore that for now. 516 * 517 * If it did support setting speed, do it here. 518 * 519 */ 520 521 if (I2C_OP_WRITE_P(op)) { 522 /* A write may include the cmdbuf and/or the databuf */ 523 err = ds28e17iic_i2c_write(sc, op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 524 525 DPRINTF(sc, 2, ("ds28e17iic_exec: I2C WRITE: addr=%02x, err=%d\n", addr, err)); 526 } else { 527 /* If a read includes a cmdbuf, then this is a write+read operation */ 528 if (cmdbuf != NULL) 529 err = ds28e17iic_i2c_write_read(sc, op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 530 else 531 err = ds28e17iic_i2c_read(sc, op, addr, databuf, datalen, flags); 532 533 DPRINTF(sc, 2, ("ds28e17iic_exec: I2C %s addr=%02x, err=%d\n", 534 cmdbuf != NULL ? "WRITE-READ" : "READ", addr, err)); 535 } 536 537 return(err); 538 } 539 540 static int 541 ds28e17iic_sysctl_init(struct ds28e17iic_softc *sc) 542 { 543 int error; 544 const struct sysctlnode *cnode; 545 int sysctlroot_num; 546 547 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 548 0, CTLTYPE_NODE, device_xname(sc->sc_dv), 549 SYSCTL_DESCR("DS28E17IIC controls"), NULL, 0, NULL, 0, CTL_HW, 550 CTL_CREATE, CTL_EOL)) != 0) 551 return error; 552 553 sysctlroot_num = cnode->sysctl_num; 554 555 #ifdef DS28E17IIC_DEBUG 556 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 557 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 558 SYSCTL_DESCR("Debug level"), ds28e17iic_verify_sysctl, 0, 559 &sc->sc_ds28e17iicdebug, 0, CTL_HW, sysctlroot_num, CTL_CREATE, 560 CTL_EOL)) != 0) 561 return error; 562 #endif 563 564 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 565 CTLFLAG_READWRITE, CTLTYPE_INT, "readycount", 566 SYSCTL_DESCR("How many times to wait for the I2C transaction to finish"), ds28e17iic_verify_sysctl, 0, 567 &sc->sc_readycount, 0, CTL_HW, sysctlroot_num, CTL_CREATE, 568 CTL_EOL)) != 0) 569 return error; 570 571 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 572 CTLFLAG_READWRITE, CTLTYPE_INT, "readydelay", 573 SYSCTL_DESCR("Delay in microseconds before checking the I2C transaction"), ds28e17iic_verify_sysctl, 0, 574 &sc->sc_readydelay, 0, CTL_HW, sysctlroot_num, CTL_CREATE, 575 CTL_EOL)) != 0) 576 return error; 577 578 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 579 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportreadnostop", 580 SYSCTL_DESCR("Report that a READ without STOP was attempted by a device"), 581 NULL, 0, &sc->sc_reportreadnostop, 0, CTL_HW, sysctlroot_num, 582 CTL_CREATE, CTL_EOL)) != 0) 583 return error; 584 585 if ((error = sysctl_createv(&sc->sc_ds28e17iiclog, 0, NULL, &cnode, 586 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportzerolen", 587 SYSCTL_DESCR("Report that an attempt to read or write zero length was attempted"), 588 NULL, 0, &sc->sc_reportzerolen, 0, CTL_HW, sysctlroot_num, 589 CTL_CREATE, CTL_EOL)) != 0) 590 return error; 591 592 return 0; 593 } 594 595 static int 596 ds28e17iic_match(device_t parent, cfdata_t match, void *aux) 597 { 598 return (onewire_matchbyfam(aux, ds28e17iic_fams, 599 __arraycount(ds28e17iic_fams))); 600 } 601 602 static void 603 ds28e17iic_attach(device_t parent, device_t self, void *aux) 604 { 605 struct ds28e17iic_softc *sc = device_private(self); 606 struct onewire_attach_args *oa = aux; 607 uint8_t hardware_rev; 608 uint8_t i2c_speed[2]; 609 int err = 0; 610 611 aprint_normal("\n"); 612 613 sc->sc_dv = self; 614 sc->sc_onewire = oa->oa_onewire; 615 sc->sc_rom = oa->oa_rom; 616 sc->sc_reportreadnostop = true; 617 sc->sc_reportzerolen = true; 618 sc->sc_ds28e17iicdebug = 0; 619 sc->sc_readycount=20; 620 sc->sc_readydelay = 10; 621 622 if ((err = ds28e17iic_sysctl_init(sc)) != 0) { 623 aprint_error_dev(self, "Can't setup sysctl tree (%d)\n", err); 624 return; 625 } 626 627 onewire_lock(sc->sc_onewire); 628 629 if (onewire_reset(sc->sc_onewire) != 0) { 630 aprint_error_dev(sc->sc_dv, "Could not reset the onewire bus for hardware version\n"); 631 onewire_unlock(sc->sc_onewire); 632 return; 633 } 634 onewire_matchrom(sc->sc_onewire, sc->sc_rom); 635 onewire_write_byte(sc->sc_onewire, DS28E17IIC_DC_DEV_REVISION); 636 hardware_rev = onewire_read_byte(sc->sc_onewire); 637 638 aprint_normal_dev(sc->sc_dv, "Hardware revision: %d\n", 639 hardware_rev); 640 641 /* The default for the chip is 400Khz, but some devices may not be able 642 * to deal with that, so set the speed to 100Khz which is standard I2C 643 * speed. 644 */ 645 646 if (onewire_reset(sc->sc_onewire) != 0) { 647 aprint_error_dev(sc->sc_dv, "Could not reset the onewire bus to set I2C speed\n"); 648 onewire_unlock(sc->sc_onewire); 649 return; 650 } 651 onewire_matchrom(sc->sc_onewire, sc->sc_rom); 652 i2c_speed[0] = DS28E17IIC_DC_WRITE_CONFIG; 653 i2c_speed[1] = DS28E17IIC_SPEED_100KHZ; 654 onewire_write_block(sc->sc_onewire, i2c_speed, 2); 655 656 onewire_unlock(sc->sc_onewire); 657 658 iic_tag_init(&sc->sc_i2c_tag); 659 sc->sc_i2c_tag.ic_cookie = sc; 660 sc->sc_i2c_tag.ic_acquire_bus = ds28e17iic_acquire_bus; 661 sc->sc_i2c_tag.ic_release_bus = ds28e17iic_release_bus; 662 sc->sc_i2c_tag.ic_exec = ds28e17iic_i2c_exec; 663 664 sc->sc_i2c_dev = iicbus_attach(self, &sc->sc_i2c_tag); 665 } 666 667 static int 668 ds28e17iic_detach(device_t self, int flags) 669 { 670 struct ds28e17iic_softc *sc = device_private(self); 671 int err = 0; 672 673 sc->sc_dying = 1; 674 675 err = config_detach_children(self, flags); 676 if (err) 677 return err; 678 679 sysctl_teardown(&sc->sc_ds28e17iiclog); 680 681 return 0; 682 } 683 684 static int 685 ds28e17iic_activate(device_t self, enum devact act) 686 { 687 struct ds28e17iic_softc *sc = device_private(self); 688 689 switch (act) { 690 case DVACT_DEACTIVATE: 691 sc->sc_dying = 1; 692 return 0; 693 default: 694 return EOPNOTSUPP; 695 } 696 } 697 698 699 MODULE(MODULE_CLASS_DRIVER, ds28e17iic, "onewire,iic"); 700 701 #ifdef _MODULE 702 #include "ioconf.c" 703 #endif 704 705 static int 706 ds28e17iic_modcmd(modcmd_t cmd, void *opaque) 707 { 708 int error; 709 710 error = 0; 711 switch (cmd) { 712 case MODULE_CMD_INIT: 713 #ifdef _MODULE 714 error = config_init_component(cfdriver_ioconf_ds28e17iic, 715 cfattach_ioconf_ds28e17iic, cfdata_ioconf_ds28e17iic); 716 if (error) 717 aprint_error("%s: unable to init component\n", 718 ds28e17iic_cd.cd_name); 719 #endif 720 break; 721 case MODULE_CMD_FINI: 722 #ifdef _MODULE 723 config_fini_component(cfdriver_ioconf_ds28e17iic, 724 cfattach_ioconf_ds28e17iic, cfdata_ioconf_ds28e17iic); 725 #endif 726 break; 727 default: 728 error = ENOTTY; 729 } 730 return error; 731 } 732
Indexes created Sat Sep 20 22:09:52 GMT 2025