ahcisata_pci.c revision 1.14 1 1.14 dholland /* $NetBSD: ahcisata_pci.c,v 1.14 2009/03/27 06:36:49 dholland Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2006 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer.
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer *
31 1.1 bouyer */
32 1.1 bouyer
33 1.1 bouyer #include <sys/cdefs.h>
34 1.14 dholland __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.14 2009/03/27 06:36:49 dholland Exp $");
35 1.1 bouyer
36 1.1 bouyer #include <sys/types.h>
37 1.1 bouyer #include <sys/malloc.h>
38 1.1 bouyer #include <sys/param.h>
39 1.1 bouyer #include <sys/kernel.h>
40 1.1 bouyer #include <sys/systm.h>
41 1.1 bouyer #include <sys/disklabel.h>
42 1.2 jmcneill #include <sys/pmf.h>
43 1.1 bouyer
44 1.1 bouyer #include <uvm/uvm_extern.h>
45 1.1 bouyer
46 1.1 bouyer #include <dev/pci/pcivar.h>
47 1.1 bouyer #include <dev/pci/pcidevs.h>
48 1.1 bouyer #include <dev/pci/pciidereg.h>
49 1.1 bouyer #include <dev/pci/pciidevar.h>
50 1.1 bouyer #include <dev/ic/ahcisatavar.h>
51 1.1 bouyer
52 1.12 dillo #define AHCI_PCI_QUIRK_FORCE 1 /* force attach */
53 1.12 dillo
54 1.12 dillo static const struct pci_quirkdata ahci_pci_quirks[] = {
55 1.12 dillo { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
56 1.12 dillo AHCI_PCI_QUIRK_FORCE },
57 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
58 1.14 dholland AHCI_PCI_QUIRK_FORCE },
59 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
60 1.14 dholland AHCI_PCI_QUIRK_FORCE },
61 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
62 1.14 dholland AHCI_PCI_QUIRK_FORCE },
63 1.12 dillo { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
64 1.12 dillo AHCI_PCI_QUIRK_FORCE },
65 1.13 tron { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
66 1.13 tron AHCI_PCI_QUIRK_FORCE },
67 1.12 dillo };
68 1.12 dillo
69 1.2 jmcneill struct ahci_pci_softc {
70 1.9 cube struct ahci_softc ah_sc;
71 1.2 jmcneill pci_chipset_tag_t sc_pc;
72 1.2 jmcneill pcitag_t sc_pcitag;
73 1.2 jmcneill };
74 1.2 jmcneill
75 1.2 jmcneill
76 1.9 cube static int ahci_pci_match(device_t, cfdata_t, void *);
77 1.9 cube static void ahci_pci_attach(device_t, device_t, void *);
78 1.12 dillo const struct pci_quirkdata *ahci_pci_lookup_quirkdata(pci_vendor_id_t,
79 1.12 dillo pci_product_id_t);
80 1.8 dyoung static bool ahci_pci_resume(device_t PMF_FN_PROTO);
81 1.2 jmcneill
82 1.1 bouyer
83 1.9 cube CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
84 1.1 bouyer ahci_pci_match, ahci_pci_attach, NULL, NULL);
85 1.1 bouyer
86 1.1 bouyer static int
87 1.9 cube ahci_pci_match(device_t parent, cfdata_t match, void *aux)
88 1.1 bouyer {
89 1.1 bouyer struct pci_attach_args *pa = aux;
90 1.1 bouyer bus_space_tag_t regt;
91 1.1 bouyer bus_space_handle_t regh;
92 1.1 bouyer bus_size_t size;
93 1.1 bouyer int ret = 0;
94 1.12 dillo const struct pci_quirkdata *quirks;
95 1.12 dillo
96 1.12 dillo quirks = ahci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
97 1.12 dillo PCI_PRODUCT(pa->pa_id));
98 1.1 bouyer
99 1.12 dillo /* if wrong class and not forced by quirks, don't match */
100 1.12 dillo if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
101 1.12 dillo ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
102 1.12 dillo PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
103 1.12 dillo PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
104 1.12 dillo (quirks == NULL || (quirks->quirks & AHCI_PCI_QUIRK_FORCE) == 0))
105 1.12 dillo return 0;
106 1.12 dillo
107 1.12 dillo if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
108 1.12 dillo PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
109 1.12 dillo ®t, ®h, NULL, &size) != 0)
110 1.12 dillo return 0;
111 1.12 dillo
112 1.12 dillo if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
113 1.3 xtraeme PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
114 1.12 dillo (quirks && quirks->quirks & AHCI_PCI_QUIRK_FORCE) ||
115 1.12 dillo (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE))
116 1.12 dillo ret = 3;
117 1.1 bouyer
118 1.12 dillo bus_space_unmap(regt, regh, size);
119 1.5 jnemeth return ret;
120 1.1 bouyer }
121 1.1 bouyer
122 1.1 bouyer static void
123 1.9 cube ahci_pci_attach(device_t parent, device_t self, void *aux)
124 1.1 bouyer {
125 1.1 bouyer struct pci_attach_args *pa = aux;
126 1.9 cube struct ahci_pci_softc *psc = device_private(self);
127 1.2 jmcneill struct ahci_softc *sc = &psc->ah_sc;
128 1.1 bouyer bus_size_t size;
129 1.1 bouyer char devinfo[256];
130 1.1 bouyer const char *intrstr;
131 1.1 bouyer pci_intr_handle_t intrhandle;
132 1.1 bouyer void *ih;
133 1.1 bouyer
134 1.11 cube sc->sc_atac.atac_dev = self;
135 1.10 cube
136 1.1 bouyer if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
137 1.1 bouyer PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
138 1.1 bouyer &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) {
139 1.9 cube aprint_error_dev(self, "can't map ahci registers\n");
140 1.1 bouyer return;
141 1.1 bouyer }
142 1.2 jmcneill psc->sc_pc = pa->pa_pc;
143 1.2 jmcneill psc->sc_pcitag = pa->pa_tag;
144 1.2 jmcneill
145 1.1 bouyer pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
146 1.1 bouyer aprint_naive(": AHCI disk controller\n");
147 1.1 bouyer aprint_normal(": %s\n", devinfo);
148 1.1 bouyer
149 1.1 bouyer if (pci_intr_map(pa, &intrhandle) != 0) {
150 1.1 bouyer aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc));
151 1.1 bouyer return;
152 1.1 bouyer }
153 1.1 bouyer intrstr = pci_intr_string(pa->pa_pc, intrhandle);
154 1.1 bouyer ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc);
155 1.1 bouyer if (ih == NULL) {
156 1.1 bouyer aprint_error("%s: couldn't establish interrupt", AHCINAME(sc));
157 1.1 bouyer return;
158 1.1 bouyer }
159 1.1 bouyer aprint_normal("%s: interrupting at %s\n", AHCINAME(sc),
160 1.1 bouyer intrstr ? intrstr : "unknown interrupt");
161 1.1 bouyer sc->sc_dmat = pa->pa_dmat;
162 1.3 xtraeme
163 1.6 mlelstv if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
164 1.7 mlelstv AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
165 1.3 xtraeme sc->sc_atac_capflags = ATAC_CAP_RAID;
166 1.6 mlelstv } else {
167 1.7 mlelstv AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
168 1.6 mlelstv }
169 1.3 xtraeme
170 1.1 bouyer ahci_attach(sc);
171 1.2 jmcneill
172 1.2 jmcneill if (!pmf_device_register(self, NULL, ahci_pci_resume))
173 1.2 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
174 1.2 jmcneill }
175 1.2 jmcneill
176 1.2 jmcneill static bool
177 1.8 dyoung ahci_pci_resume(device_t dv PMF_FN_ARGS)
178 1.2 jmcneill {
179 1.2 jmcneill struct ahci_pci_softc *psc = device_private(dv);
180 1.2 jmcneill struct ahci_softc *sc = &psc->ah_sc;
181 1.2 jmcneill int s;
182 1.2 jmcneill
183 1.2 jmcneill s = splbio();
184 1.2 jmcneill ahci_reset(sc);
185 1.2 jmcneill ahci_setup_ports(sc);
186 1.2 jmcneill ahci_reprobe_drives(sc);
187 1.2 jmcneill ahci_enable_intrs(sc);
188 1.2 jmcneill splx(s);
189 1.2 jmcneill
190 1.2 jmcneill return true;
191 1.1 bouyer }
192 1.12 dillo
193 1.12 dillo const struct pci_quirkdata *
194 1.12 dillo ahci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
195 1.12 dillo {
196 1.12 dillo int i;
197 1.12 dillo
198 1.12 dillo for (i = 0; i < (sizeof ahci_pci_quirks / sizeof ahci_pci_quirks[0]);
199 1.12 dillo i++)
200 1.12 dillo if (vendor == ahci_pci_quirks[i].vendor &&
201 1.12 dillo product == ahci_pci_quirks[i].product)
202 1.12 dillo return (&ahci_pci_quirks[i]);
203 1.12 dillo return (NULL);
204 1.12 dillo }
205