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History log of /src/sys/dev/pci/ahcisata_pci.c
RevisionDateAuthorComments
 1.72  20-Apr-2025  andvar viaide(4): Improve VT8251 integrated SATA controller support in IDE/RAID modes.

Use via_chip_map() to attach this controller in IDE and RAID modes, similarly
to VX800. This allows drives to be identified and attached successfully on all
four ports (two channels with master/slave ports).

Switch channel setup to sata_setup_channel(), replacing via_setup_channel().
This avoids writes to the 0x50 register, which is only relevant for IDE
controllers. Writes to SATA controller registers caused drives on the IDE
controller (0x0571) to fail to attach. Apply this fix also to VX900 and VT8261.

Rename VT8237R_SATA to VT8251_SATA (0x3349 is not used for VT8237R, AFAIK).
This PCI ID is used in RAID mode on newer (CE) chipset revision and in all
modes (IDE/RAID/AHCI) on older revision.
Add the 0x5287 PCI ID, used in IDE mode on newer (CE) chipset revision.
Rename VT8251_SATA to VT8251_AHCI (0x6287 is used only in AHCI mode).
Add VT8251_AHCI to the ahcisata(4) quirk list, same as VT8251_SATA.

For more details, see the tech-kern thread:
https://mail-index.netbsd.org/tech-kern/2025/04/13/msg030365.html

Should fix and close PR kern/37517.

Tested on Asus A8V-VM (CD) and MSI MS-7318 (CE) motherboards.

Reviewed by bad.
 1.71  10-Oct-2023  abs branches: 1.71.6;
Add support for ASMEDIA 0x0624

... an AHCI SATA adaptor which identifies itself as an IDE storage device
 1.70  10-Sep-2023  abs Rework AHCISATA_EXTRA_DELAY for kern/56737

- Remove AHCI_QUIRK_EXTRA_DELAY as issue appears to be drive and
not controller related
- Replace AHCISATA_EXTRA_DELAY with AHCISATA_REMOVE_EXTRA_DELAY,
so defaulting to enabling the extra delay, as the downside of
slower probing on systems which do not need it is less than having
other systems intermittently fail to probe and attach drives
- Also allow disabling extra delay with AHCISATA_EXTRA_DELAY_MS = 0

We should return to this code to work out which of the extra delays
are needed, and how long they need to be. It may be that faster
systems are more likely to trigger the issue (I've only seen it on
a 13th gen i7-13700, though only tested on a limited set)

XXX pullup -10
 1.69  31-Jul-2023  tnn ahcisata: ASM106x needs EXTRA_DELAY quirk
 1.68  12-Oct-2022  macallan branches: 1.68.2;
set AHCI_QUIRK_EXTRA_DELAY for ASMedia ASM1061 - now it reliably attaches old
1.5GBit/s only disks
 1.67  02-Oct-2022  martin Add extra delay quirk for AMD FCH SATA Controller D.
 1.66  02-Oct-2022  martin regen (AMD FCH SATA D added)
 1.65  31-May-2022  andvar fix various typos in comments, documentation and messages.
 1.64  29-May-2022  rin Apply extra delay quirk for

- Intel 7 Series (mobile) SATA Controller (AHCI):
rev. 0x04 sometimes fails to probe Seagate ST500LT012.

Reported by RVP. Thanks!
 1.63  29-May-2022  rin Apply extra delay quirk for followings:

- Intel Braswell AHCI: rev. 0x35 fails for Seagate ST2000LX001.

- Intel 8 Series (desktop) SATA Controller (AHCI): rev. 0x04 fails for
Seagate ST1000LX015 and WD WD10JPVX, whereas it works without the
quirk for some SSD models...

Reported by Matthias Petermann. Thanks!
 1.62  14-May-2022  rin Apply extra-delay quirk to "Intel 9 Series SATA Controller (AHCI)";
without the quirk, the controller fails to probe some HDD models,
at least "Seagate ST2000DM008".

Info and patch provided by Tiago Seco, thanks!
 1.61  19-Nov-2021  rin ahcisata(4): Introduce AHCI_QUIRK_EXTRA_DELAY quirk for devices that
need extra delays as done by AHCISATA_EXTRA_DELAY option.

Enable this quirk for "C600/X79 AHCI". Also add commented out quirk
entries for "Bay Trail SATA (AHCI)" and "Mobile AHCI SATA Controller",
for which non-reproducible failures worked around by extra delays have
been reported.

500 ms of delays inserted by these option/quirk may be too much. Add
AHCISATA_EXTRA_DELAY_MS option to adjust number of delays in ms, like:

----
options AHCISATA_EXTRA_DELAY_MS=200
----

Thanks prlw1@ and jun@ for testing!
 1.60  12-Nov-2021  skrll Fix the conditional for failed interrupt establishment
 1.59  08-Nov-2021  rin Group quirks by vendors. No functional changes.
 1.58  28-Dec-2020  jmcneill Remove duplicate opt_ahcisata_pci.h include
 1.57  18-Jan-2020  simonb branches: 1.57.6;
Add new AHCI_QUIRK_BADNCQ quick for controllers that have issues with
NCQ on (some) drives. Enable this quirk for ATI (AMD) SB600/SB700
controllers. Alternate fix for kern/54790 and kern/54855.

ok jdolecek@, tested on my SB700 chipset and tsutsui's SB600 chipset.
 1.56  18-Oct-2019  tnn branches: 1.56.2;
ahcisata: make sure bus mastering and memory space are actually enabled

This makes the "ROCKPro64 PCI-e to Dual SATA-II Interface Card" work.
 1.55  27-Jan-2019  pgoyette branches: 1.55.4;
Merge the [pgoyette-compat] branch
 1.54  22-Jan-2019  jdolecek fix pasto; still PR kern/53307
 1.53  22-Jan-2019  jdolecek add BADPMP quirk also for AMD Hudson AHCI SATA Controller, seems in some
configurations/BIOS versions the PMP reset works, in others not; it's better
to have the common configuration working

related to PR kern/53307
 1.52  22-Jan-2019  jdolecek add BADPMP quirk for Intel 82801JI SATA Controller (AHCI mode), which
apparently has problem with the PMP reset

part of PR kern/53307 - Christos machine
 1.51  14-Jan-2019  jdolecek nothing handles AHCI_QUIRK_BADPMPRESET quirk, remove and change all entries
using it (ATI SB600/SB700) to instead use AHCI_QUIRK_BADPMP
 1.50  08-Dec-2018  jdolecek support multi-vector MSI-X

tested and confirmed working by Masanobu SAITOH on C3000
 1.49  04-Dec-2018  jdolecek disable MSI-X for time being since it's not working; allow only MSI
and INTx which both are confirmed working
 1.48  30-Nov-2018  jdolecek simplify intr establish code - rely on pci_intr_alloc() to allow
also MSI-X, and to return interrupt types which are possible for
pci_intr_establish(); remove fallbacks to retry with MSI/MSI-X
explicitly disabled

discussed on tech-kern@

https://mail-index.netbsd.org/tech-kern/2018/11/27/msg024240.html
 1.47  26-Nov-2018  jdolecek add AHCI_PCI_QUIRK_FORCE for apu2 to be recognized; patch by Mike Pumford
on current-users@
 1.46  24-Nov-2018  skrll Handle Cavium AHCI/RAID controller BAR weirdness.

Support 64bit BARs as well.
 1.45  20-Nov-2018  prlw1 Trivial build fix
 1.44  20-Nov-2018  skrll Add support for MSI/MSI-X to ahcisata at pci.

The options AHCISATA_DISABLE_MSI and AHCISATA_DISABLE_MSIX are available
if required.
 1.43  18-Nov-2018  skrll Trailing whitespace
 1.42  25-Oct-2018  jdolecek release intr if pci_intr_establish_xname() fails
 1.41  24-Oct-2018  jdolecek detach the controller itself on shutdown; adjust to not detach already
detached atabus/channel
 1.40  22-Oct-2018  jdolecek first disestablish interrupt, then release
 1.39  22-Oct-2018  jdolecek enable MSI support where available
 1.38  13-Oct-2016  jdolecek branches: 1.38.8; 1.38.14; 1.38.16;
provide intr xname
 1.37  23-Aug-2016  msaitoh Sync with pcidevs rev. 1.1263. No functional change.
 1.36  29-Mar-2014  christos branches: 1.36.6; 1.36.10;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.
 1.35  21-Jan-2014  msaitoh Rename 88SE91XX.
 1.34  10-Jan-2014  msaitoh Sync with pcidev's change. Rename PCI_PRODUCT_MARVELL2_88SE9128 to
PCI_PRODUCT_MARVELL2_88SE912Z. No functional change.
 1.33  09-Jan-2014  christos revert unintended changes
 1.32  09-Jan-2014  htodd Fix build. Only compile tested.
 1.31  21-Oct-2012  matt branches: 1.31.2;
Add FORCE quirks for ASMEDIA ASM1061
 1.30  20-Aug-2012  bouyer branches: 1.30.2;
Fix typo, pointed out by Markus W Kilbinger
 1.29  10-Aug-2012  bouyer Remove leftover comment.
 1.28  10-Aug-2012  bouyer Work around some SATA PMP issues in some AHCI controllers by either
disabling PMP entirely, or special handling in the reset function.
Controller list from linux and FreeBSD.
 1.27  30-Jan-2012  drochner branches: 1.27.2; 1.27.4;
Use pci_aprint_devinfo(9) instead of pci_devinfo+aprint_{normal,naive}
where it looks straightforward, and pci_aprint_devinfo_fancy in a few
others where drivers want to supply their own device names instead
of the pcidevs generated one. More complicated cases, where names
are composed at runtime, are left alone for now. It certainly makes
sense to simplify the drivers here rather than inventing a catch-all API.
This should serve as as example for new drivers, and also ensure
consistent output in the AB_QUIET ("boot -q") case. Also, it avoids
excessive stack usage where drivers attach child devices because the
buffer for the device name is not kept on the local stack anymore.
 1.26  06-Aug-2011  jakllsch branches: 1.26.2; 1.26.6;
Marvell 88SE9128 needs AHCI_PCI_QUIRK_FORCE.
 1.25  27-May-2011  matt Add quirk for ALI M5228
 1.24  03-Apr-2011  dyoung Deregister in ahci_pci_detach() the PMF hooks registered in
ahci_pci_attach().
 1.23  13-Nov-2010  uebayasi branches: 1.23.2;
Don't pull in the whole uvm(9) API to access only PAGE_SIZE and
some other constants. These are provided by sys/param.h now.
 1.22  07-Aug-2010  jmcneill Add NVIDIA MCP77 to the quirk table, so ahcisata will attach when the
BIOS is set to 'RAID' mode.
 1.21  27-Jul-2010  jakllsch Use use 64-bit DMA tag (where available and supported) for ahcisata.
Avoid the possible ATI SB600 64-bit DMA problem.
 1.20  27-Jul-2010  jakllsch Support detachment of ahcisata(4).
Use use 64-bit DMA tag (where available) for ahcisata(4) at jmide(4).
Beginnings of detach/resume support for jmide(4).
Sprinkle static. Misc. little changes.
 1.19  24-Feb-2010  dyoung branches: 1.19.2;
A pointer typedef entails trading too much flexibility to declare const
and non-const types, and the kernel uses both const and non-const
PMF qualifiers and device suspensors, so change the pmf_qual_t and
device_suspensor_t typedefs from "pointers to const" to non-pointer,
non-const types.
 1.18  08-Jan-2010  dyoung branches: 1.18.2;
Expand PMF_FN_* macros.
 1.17  19-Oct-2009  bouyer Remove closes 3 & 4 from my licence. Lots of thanks to Soren Jacobsen
for the booring work !
 1.16  19-Aug-2009  pgoyette Use __arraycount() for readability
 1.15  11-Jun-2009  cegger Attach Marvel 88SE6121 SATA II controller on ahci.
W/o this, it attaches on pciide.
 1.14  27-Mar-2009  dholland Add the other three PCI ids for the nvidia MCP65 SATA controller to
the quirk table. This way they attach as ahcisata and work, instead of
attaching as viaide and failing miserably.

Fixes PR kern/37826.

XXX: There are a bunch of additional MCP67 and MCP73 PCI ids that
XXX: should probably be added also, but I don't want to do that without
XXX: further investigation and testing.
 1.13  08-Dec-2008  tron branches: 1.13.2;
Force the nVidia nForce 630i MCP73 to attach to ahcisata(4) as well.
It would otherwise attach to pciide(4) and use PIO mode.

Patch submitted by Bernhard Moellemann in PR kern/40134.
 1.12  01-Aug-2008  dillo branches: 1.12.2; 1.12.4;
Force ahcisata to attach to NVIDIA MCP65 and MCP67, as they don't
work with viaide.

Reviewed by bouyer.
 1.11  20-Mar-2008  cube branches: 1.11.4; 1.11.6; 1.11.10;
Fix previous. *Sigh*
 1.10  20-Mar-2008  cube Don't forget to se the device_t back pointer in the softc.
 1.9  18-Mar-2008  cube Split device_t and softc for ATA devices, as well as wd(4). Other
cosmetic changes where appropriate.
 1.8  29-Feb-2008  dyoung Use PMF_FN_ARGS, PMF_FN_PROTO.
 1.7  23-Feb-2008  mlelstv make this less verbose
 1.6  23-Feb-2008  mlelstv Always attach AHCI_SATA devices, even when not configured for AHCI mode.
Fixes PR kern/38081.
 1.5  19-Feb-2008  jnemeth branches: 1.5.2; 1.5.6;
KNF
 1.4  19-Feb-2008  jnemeth PR/38056 - Simon Burge -- In ahci_pci_match, return the correct
value so that we only match SATA RAID controllers in AHCI mode.

Tested by: simonb@
Approved by: bouyer@
 1.3  11-Feb-2008  xtraeme Attach ahcisata(4) to any RAID controller that supports AHCI, and make it
pass the ATAC_CAP_RAID capability for them. ok'ed by bouyer@.
 1.2  09-Dec-2007  jmcneill Merge jmcneill-pm branch.
 1.1  12-May-2007  bouyer branches: 1.1.2; 1.1.4; 1.1.6; 1.1.12; 1.1.14; 1.1.16; 1.1.18; 1.1.20; 1.1.26; 1.1.28; 1.1.30;
Split the ahcisata driver in pci front-end and bus-independant back-end.
 1.1.30.1  11-Dec-2007  yamt sync with head.
 1.1.28.1  26-Dec-2007  ad Sync with head.
 1.1.26.1  18-Feb-2008  mjf Sync with HEAD.
 1.1.20.7  24-Mar-2008  yamt sync with head.
 1.1.20.6  17-Mar-2008  yamt sync with head.
 1.1.20.5  27-Feb-2008  yamt sync with head.
 1.1.20.4  11-Feb-2008  yamt sync with head.
 1.1.20.3  21-Jan-2008  yamt sync with head
 1.1.20.2  03-Sep-2007  yamt sync with head.
 1.1.20.1  12-May-2007  yamt file ahcisata_pci.c was added on branch yamt-lazymbuf on 2007-09-03 14:36:20 +0000
 1.1.18.2  03-Sep-2007  wrstuden Sync w/ NetBSD-4-RC_1
 1.1.18.1  12-May-2007  wrstuden file ahcisata_pci.c was added on branch wrstuden-fixsa on 2007-09-03 07:04:27 +0000
 1.1.16.2  31-Aug-2007  pavel Pull up following revision(s) (requested by bouyer in ticket #678):
distrib/sets/lists/man/mi: revision 1.1001
doc/CHANGES: revision 1.853 via patch
share/man/man4/Makefile: revision 1.428
share/man/man4/jmide.4: revision 1.1
sys/arch/amd64/conf/GENERIC: revision 1.143
sys/arch/amd64/conf/INSTALL: revision 1.69
sys/arch/i386/conf/GENERIC: revision 1.827
sys/arch/i386/conf/INSTALL_LARGE: revision 1.2 via patch
sys/arch/i386/conf/XEN2_DOM0: revision 1.26
sys/conf/files: revision 1.844 via patch
sys/dev/ic/ahcisata_core.c: revision 1.1 via patch
sys/dev/ic/ahcisata_core.c: revision 1.3
sys/dev/ic/ahcisatareg.h: revision 1.1
sys/dev/ic/ahcisatavar.h: revision 1.1
sys/dev/pci/ahcisata.c: delete
sys/dev/pci/ahcisatareg.h: delete
sys/dev/pci/ahcisata_pci.c: revision 1.1
sys/dev/pci/files.pci: revision 1.287-1.288
sys/dev/pci/jmide.c: revision 1.1-1.2
sys/dev/pci/jmide_reg.h: revision 1.1
sys/dev/pci/pcidevs: revision 1.878
Add JMicron Technology vendor ID, and their current PCIe SATA/PATA
controllers.

Split the ahcisata driver in pci front-end and bus-independant back-end.
add jmide(4), a driver for the JMicron Technology JMB36x PCIe to SATA II/PATA
controllers. These controllers can be found on add-on PCIe cards, or
on some motherboards to provide the PATA connectivity (e.g. some intel
ICH8-based motherboards).
Thanks to JMicron Technology for providing me documentation and
different sample boards for this work.

Move mapping of AHCI register so that jmide knows if it fails, and avoids
calling ahci_intr() (which would cause a panic).
Try to use the pciide function for SATA drives if attaching ahci fails (this
doesn't seems to work though, it may be BIOS dependant).
Thanks to Gary Duzan for testing multiple pacthes.

We're not ready to handle ATAPI yet so just claim there's no drive to the
upper layer. This should work around a NULL pointer dereference when
an ATAPI device is detected on a AHCI device.
 1.1.16.1  12-May-2007  pavel file ahcisata_pci.c was added on branch netbsd-4 on 2007-08-31 20:09:25 +0000
 1.1.14.2  23-Mar-2008  matt sync with HEAD
 1.1.14.1  09-Jan-2008  matt sync with HEAD
 1.1.12.4  08-Dec-2007  jmcneill Rename pnp(9) -> pmf(9), as requested by many.
 1.1.12.3  06-Nov-2007  joerg Refactor PNP API:
- Make suspend/resume directly a device functionality. It consists of
three layers (class logic, device logic, bus logic), all of them being
optional. This replaces D0/D3 transitions.
- device_is_active returns true if the device was not disabled and was
not suspended (even partially), device_is_enabled returns true if the
device was enabled.
- Change pnp_global_transition into pnp_system_suspend and
pnp_system_resume. Before running any suspend/resume handlers, check
that all currently attached devices support power management and bail
out otherwise. The latter is not done for the shutdown/panic case.
- Make the former bus-specific generic network handlers a class handler.
- Make PNP message like volume up/down/toogle PNP events. Each device
can register what events they are interested in and whether the handler
should be global or not.
- Introduce device_active API for devices to mark themselve in use from
either the system or the device. Use this to implement the idle handling
for audio and input devices. This is intended to replace most ad-hoc
watchdogs as well.
- Fix somes situations in which audio resume would lose mixer settings.
- Make USB host controllers better deal with suspend in the light of
shared interrupts.
- Flush filesystem cache on suspend.
- Flush disk caches on suspend. Put ATA disks into standby on suspend as
well.
- Adopt drivers to use the new PNP API.
- Fix a critical bug in the generic cardbus layer that made D0->D3
break.
- Fix ral(4) to set if_stop.
- Convert cbb(4) to the new PNP API.
- Apply the PCI Express SCI fix on resume again.
 1.1.12.2  01-Oct-2007  joerg Extend device API by device_power_private and device_power_set_private.
The latter is a temporary mean until the pnp_register API itself is
overhault. This functions allow a generic power handler to store its
state independent of the driver.

Use this and revamp the PCI power handling. Pretty much all PCI devices
had power handlers that did the same thing, generalize this in
pci_generic_power_register/deregister and the handler. This interface
offers callbacks for the drivers to save and restore state on
transistions. After a long discussion with jmcneill@ it was considered
to be powerful enough until evidence is shown that devices can handle
D1/D2 with less code and higher speed than without the full
save/restore. The generic code is carefully written to handle device
without PCI-PM support and ensure that the correct registers are written
to when D3 loses all state.

Reimplement the generic PCI network device handling on
top of PCI generic power handling.

Introduce pci_disable_retry as used and implemented locally at least by
ath(4) and iwi(4). Use it in this drivers to restore behaviour from
before the introduction of generic PCI network handling.

Convert all PCI drivers that were using pnp_register to the new
framework. The only exception is vga(4) as it is commonly used as
console device. Add a note therein that this should be fixed later.
 1.1.12.1  04-Aug-2007  he Factor out the hardware initialization code in ahcisata_core.c,
and provide them to the pci frontend, which has now grown its own
softc and a power management handler.

There may be one too many re-initializations done on resume (witness
the multiple kernel messages from ahcisata), but at least this is
sufficient to get the Lenovo T60 to come out of resume with a
working disk controller and disk.
 1.1.6.2  11-Jul-2007  mjf Sync with head.
 1.1.6.1  12-May-2007  mjf file ahcisata_pci.c was added on branch mjf-ufs-trans on 2007-07-11 20:06:58 +0000
 1.1.4.2  09-Jun-2007  ad Sync with head.
 1.1.4.1  12-May-2007  ad file ahcisata_pci.c was added on branch vmlocking on 2007-06-09 21:37:23 +0000
 1.1.2.2  17-May-2007  yamt sync with head.
 1.1.2.1  12-May-2007  yamt file ahcisata_pci.c was added on branch yamt-idlelwp on 2007-05-17 13:41:29 +0000
 1.5.6.3  17-Jan-2009  mjf Sync with HEAD.
 1.5.6.2  28-Sep-2008  mjf Sync with HEAD.
 1.5.6.1  03-Apr-2008  mjf Sync with HEAD.
 1.5.2.1  24-Mar-2008  keiichi sync with head.
 1.11.10.2  13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.11.10.1  19-Oct-2008  haad Sync with HEAD.
 1.11.6.1  18-Sep-2008  wrstuden Sync with wrstuden-revivesa-base-2.
 1.11.4.5  11-Aug-2010  yamt sync with head.
 1.11.4.4  11-Mar-2010  yamt sync with head
 1.11.4.3  16-Sep-2009  yamt sync with head
 1.11.4.2  20-Jun-2009  yamt sync with head
 1.11.4.1  04-May-2009  yamt sync with head.
 1.12.4.3  21-Nov-2010  riz branches: 1.12.4.3.2;
Pull up following revision(s) (requested by jmcneill in ticket #1437):
sys/dev/pci/ahcisata_pci.c: revision 1.22
Add NVIDIA MCP77 to the quirk table, so ahcisata will attach when the
BIOS is set to 'RAID' mode.
 1.12.4.2  30-Mar-2009  snj branches: 1.12.4.2.4;
Pull up following revision(s) (requested by dholland in ticket #616):
sys/dev/pci/ahcisata_pci.c: revision 1.14
Add the other three PCI ids for the nvidia MCP65 SATA controller to
the quirk table. This way they attach as ahcisata and work, instead of
attaching as viaide and failing miserably.
Fixes PR kern/37826.
XXX: There are a bunch of additional MCP67 and MCP73 PCI ids that
XXX: should probably be added also, but I don't want to do that without
XXX: further investigation and testing.
 1.12.4.1  10-Dec-2008  snj Pull up following revision(s) (requested by tron in ticket #170):
sys/dev/pci/ahcisata_pci.c: revision 1.13
Force the nVidia nForce 630i MCP73 to attach to ahcisata(4) as well.
It would otherwise attach to pciide(4) and use PIO mode.
Patch submitted by Bernhard Moellemann in PR kern/40134.
 1.12.4.3.2.1  14-Oct-2011  matt revision 1.25
date: 2011/05/27 15:11:59; author: matt; state: Exp; lines: +4 -2
Add quirk for ALI M5228
 1.12.4.2.4.2  26-Mar-2014  matt Use ahci_resume
 1.12.4.2.4.1  05-Nov-2013  matt Support a 64-bit BAR for AHCI
 1.12.2.2  28-Apr-2009  skrll Sync with HEAD.
 1.12.2.1  19-Jan-2009  skrll Sync with HEAD.
 1.13.2.2  23-Jul-2009  jym Sync with HEAD.
 1.13.2.1  13-May-2009  jym Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.
 1.18.2.2  17-Aug-2010  uebayasi Sync with HEAD.
 1.18.2.1  30-Apr-2010  uebayasi Sync with HEAD.
 1.19.2.3  31-May-2011  rmind sync with head
 1.19.2.2  21-Apr-2011  rmind sync with head
 1.19.2.1  05-Mar-2011  rmind sync with head
 1.23.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.26.6.1  18-Feb-2012  mrg merge to -current.
 1.26.2.3  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.26.2.2  30-Oct-2012  yamt sync with head
 1.26.2.1  17-Apr-2012  yamt sync with head
 1.27.4.1  18-Nov-2012  matt Merge tickets 658 and 659.
 1.27.2.1  18-Nov-2012  msaitoh Pull up following revision(s) (requested by matt in ticket #659):
sys/dev/pci/ahcisata_pci.c: revision 1.31
Add FORCE quirks for ASMEDIA ASM1061
 1.30.2.4  03-Dec-2017  jdolecek update from HEAD
 1.30.2.3  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.30.2.2  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.30.2.1  09-Oct-2012  bouyer Support transfers of up to MACHINE_MAXPHYS in all pciide variants, and ahci.
wd(4) limits its maxphys depending on the drives's capability (64k sectors
for LBA48, 256 sectors for LBA and 128 sectors for older devices).

I assumed all pciide controllers could do MACHINE_MAXPHYS transfers, but
this may not be true. The capabilities of each controller variants should be
looked at more closely.
 1.31.2.1  18-May-2014  rmind sync with head
 1.36.10.1  04-Nov-2016  pgoyette Sync with HEAD
 1.36.6.2  05-Dec-2016  skrll Sync with HEAD
 1.36.6.1  05-Oct-2016  skrll Sync with HEAD
 1.38.16.3  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.38.16.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.38.16.1  10-Jun-2019  christos Sync with HEAD
 1.38.14.4  26-Jan-2019  pgoyette Sync with HEAD
 1.38.14.3  18-Jan-2019  pgoyette Synch with HEAD
 1.38.14.2  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.38.14.1  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.38.8.2  13-Oct-2023  martin Pull up following revision(s) (requested by abs in ticket #1911):

sys/dev/pci/ahcisata_pci.c: revision 1.71

Add support for ASMEDIA 0x0624
... an AHCI SATA adaptor which identifies itself as an IDE storage device
 1.38.8.1  18-Dec-2018  martin Pull up following revision(s) (requested by is in ticket #1139):

sys/dev/pci/ahcisata_pci.c: revision 1.47

add AHCI_PCI_QUIRK_FORCE for apu2 to be recognized; patch by Mike Pumford
on current-users@
 1.55.4.4  09-May-2025  martin Pull up following revision(s) (requested by andvar in ticket #1944):

sys/dev/pci/viaide.c: revision 1.90
sys/dev/pci/ahcisata_pci.c: revision 1.72
sys/dev/pci/pciide_apollo_reg.h: revision 1.21
sys/dev/pci/viaide.c: revision 1.91
sys/dev/pci/viaide.c: revision 1.92
sys/dev/pci/viaide.c: revision 1.93
sys/dev/pci/viaide.c: revision 1.94
sys/dev/pci/viaide.c: revision 1.96
sys/dev/pci/viaide.c: revision 1.97
sys/dev/pci/viaide.c: revision 1.98
share/man/man4/viaide.4: revision 1.11
share/man/man4/viaide.4: revision 1.12

Use the chipset name to describe the IDE controller in order to avoid confusion.
VT800->VX800 and VT855->VX855.
Add VIA VT8261 southbridge SATA controller IDs and PCIB.
viaide(4): use via_chip_map() instead of via_sata_chip_map_new() to attach
CX700/VX800 IDE/SATA RAID controllers and set interface flags the same way as
the VT6410_RAID case for native interrupts required by RAID mode.
Device descriptions were moved to pciide_via_products and updated to cascade
VT6410_RAID and CX700_IDE options.
via_sata_chip_map_new previously worked more by "accident," as it did not
return early on failure to map SATA registers and defaulted to the generic
drive probe function. However, it failed to attach PATA drives (endless
timeouts) and incorrectly detected "three" channels as VT6421, despite the
controller having only two.
Fixes PR kern/59010.
Reviewed and approved by jakllsch@.

Update CX700_IDE and CX700M2_IDE descriptions to better reflect their actual
purpose.
These are not separate IDE controllers for CX700 and CX700M2 but rather the
IDE and RAID modes of the same controller in these chipsets (and few more).
viaide(4): check and add ATA RAID capability in via_sata_chip_map_new() used
by VT6241(A) RAID controller.
This is required for ataraid(4) to attach on this controller if RAID was
configured using its firwmare.
The conditions may be redundant for this controller, but it is uncertain what
variations exist in the wild.

viaide(4): add IDE controller identification by the VT8237S ISA bridge.
The controller's PATA interface uses PCI ID 0x0571, which is shared among
many VIA southbridges. The ISA bridge is used to identify capabilities,
including for the VT8237S.
Unknown PATA controllers disable UDMA by default. This change ensures PATA
drives attach at full speed.

viaide(4): Add support for VIA VT8261 IDE/SATA integrated controller.

The VT8261 southbridge, paired with the VN1000 chipset, is obscure and hard to
find. Besides some evaluation boards surfacing after Centaurs demise, at least
one rare production motherboard is known to exist.

Despite its rarity, the VT8261 is very similar to the VT8251. It uses separate
PCI IDs for PATA and SATA (IDE/RAID modes) with 4 SATA ports in total, 2 ports
sharing one channel, and maps registers through BAR5. This similarity made
adding basic support relatively simple (sharing same issues too).

Tested briefly on VIA VT8591B eval board.


viaide(4): Add RAID mode support for VIA VX900/VX11 SATA controllers.
The BIOS option to enable RAID is uncommon on systems using these chipsets;
however, at least two motherboards mention it in their manuals. The RAID
firmware does not provide management features, but it can recognize and boot
from preconfigured VIA RAID arrays.
Tested on ECS VX900-I.
Also add the VX11 chipset to the controller name, as it shares the same PCI ID.
viaide(4): Improve VT8251 integrated SATA controller support in IDE/RAID modes.
Use via_chip_map() to attach this controller in IDE and RAID modes, similarly
to VX800. This allows drives to be identified and attached successfully on all
four ports (two channels with master/slave ports).
Switch channel setup to sata_setup_channel(), replacing via_setup_channel().
This avoids writes to the 0x50 register, which is only relevant for IDE
controllers. Writes to SATA controller registers caused drives on the IDE
controller (0x0571) to fail to attach. Apply this fix also to VX900 and VT8261.
Rename VT8237R_SATA to VT8251_SATA (0x3349 is not used for VT8237R, AFAIK).
This PCI ID is used in RAID mode on newer (CE) chipset revision and in all
modes (IDE/RAID/AHCI) on older revision.
Add the 0x5287 PCI ID, used in IDE mode on newer (CE) chipset revision.
Rename VT8251_SATA to VT8251_AHCI (0x6287 is used only in AHCI mode).
Add VT8251_AHCI to the ahcisata(4) quirk list, same as VT8251_SATA.
For more details, see the tech-kern thread:
https://mail-index.netbsd.org/tech-kern/2025/04/13/msg030365.html
Should fix and close PR kern/37517.
Tested on Asus A8V-VM (CD) and MSI MS-7318 (CE) motherboards.
Reviewed by bad.
viaide(4): check if chip enable register returns 0 before emulating enable
bits.
At least some VT6410 controllers have register exposed. In fact, some
motherboards allow to control IDE channels (enable/disable them).
viaide(4): update the list of supported VIA controllers.
viaide(4): remove notes section about VT6421, it is not currently required to
setup RAID/JBOD sets to access drives.
 1.55.4.3  13-Oct-2023  martin Pull up following revision(s) (requested by abs in ticket #1748):

sys/dev/pci/ahcisata_pci.c: revision 1.71

Add support for ASMEDIA 0x0624
... an AHCI SATA adaptor which identifies itself as an IDE storage device
 1.55.4.2  21-Jan-2020  martin Pull up following revision(s) (requested by simonb in ticket #630):

sys/dev/ic/ahcisatavar.h: revision 1.24
sys/dev/pci/ahcisata_pci.c: revision 1.57
sys/dev/ic/ahcisata_core.c: revision 1.81

Add new AHCI_QUIRK_BADNCQ quick for controllers that have issues with
NCQ on (some) drives. Enable this quirk for ATI (AMD) SB600/SB700
controllers. Alternate fix for kern/54790 and kern/54855.
ok jdolecek@, tested on my SB700 chipset and tsutsui's SB600 chipset.
 1.55.4.1  23-Oct-2019  martin Pull up following revision(s) (requested by tnn in ticket #358):

sys/dev/pci/ahcisata_pci.c: revision 1.56

ahcisata: make sure bus mastering and memory space are actually enabled
This makes the "ROCKPro64 PCI-e to Dual SATA-II Interface Card" work.
 1.56.2.1  25-Jan-2020  ad Sync with head.
 1.57.6.1  03-Jan-2021  thorpej Sync w/ HEAD.
 1.68.2.4  09-May-2025  martin Pull up following revision(s) (requested by andvar in ticket #1101):

sys/dev/pci/viaide.c: revision 1.90
sys/dev/pci/ahcisata_pci.c: revision 1.72
sys/dev/pci/pciide_apollo_reg.h: revision 1.21
sys/dev/pci/viaide.c: revision 1.91
sys/dev/pci/viaide.c: revision 1.92
sys/dev/pci/viaide.c: revision 1.93
sys/dev/pci/viaide.c: revision 1.94
sys/dev/pci/viaide.c: revision 1.96
sys/dev/pci/viaide.c: revision 1.97
sys/dev/pci/viaide.c: revision 1.98
share/man/man4/viaide.4: revision 1.11
share/man/man4/viaide.4: revision 1.12

Use the chipset name to describe the IDE controller in order to avoid confusion.
VT800->VX800 and VT855->VX855.
Add VIA VT8261 southbridge SATA controller IDs and PCIB.
viaide(4): use via_chip_map() instead of via_sata_chip_map_new() to attach
CX700/VX800 IDE/SATA RAID controllers and set interface flags the same way as
the VT6410_RAID case for native interrupts required by RAID mode.
Device descriptions were moved to pciide_via_products and updated to cascade
VT6410_RAID and CX700_IDE options.
via_sata_chip_map_new previously worked more by "accident," as it did not
return early on failure to map SATA registers and defaulted to the generic
drive probe function. However, it failed to attach PATA drives (endless
timeouts) and incorrectly detected "three" channels as VT6421, despite the
controller having only two.
Fixes PR kern/59010.
Reviewed and approved by jakllsch@.

Update CX700_IDE and CX700M2_IDE descriptions to better reflect their actual
purpose.
These are not separate IDE controllers for CX700 and CX700M2 but rather the
IDE and RAID modes of the same controller in these chipsets (and few more).
viaide(4): check and add ATA RAID capability in via_sata_chip_map_new() used
by VT6241(A) RAID controller.
This is required for ataraid(4) to attach on this controller if RAID was
configured using its firwmare.
The conditions may be redundant for this controller, but it is uncertain what
variations exist in the wild.

viaide(4): add IDE controller identification by the VT8237S ISA bridge.
The controller's PATA interface uses PCI ID 0x0571, which is shared among
many VIA southbridges. The ISA bridge is used to identify capabilities,
including for the VT8237S.
Unknown PATA controllers disable UDMA by default. This change ensures PATA
drives attach at full speed.

viaide(4): Add support for VIA VT8261 IDE/SATA integrated controller.

The VT8261 southbridge, paired with the VN1000 chipset, is obscure and hard to
find. Besides some evaluation boards surfacing after Centaurs demise, at least
one rare production motherboard is known to exist.

Despite its rarity, the VT8261 is very similar to the VT8251. It uses separate
PCI IDs for PATA and SATA (IDE/RAID modes) with 4 SATA ports in total, 2 ports
sharing one channel, and maps registers through BAR5. This similarity made
adding basic support relatively simple (sharing same issues too).

Tested briefly on VIA VT8591B eval board.


viaide(4): Add RAID mode support for VIA VX900/VX11 SATA controllers.
The BIOS option to enable RAID is uncommon on systems using these chipsets;
however, at least two motherboards mention it in their manuals. The RAID
firmware does not provide management features, but it can recognize and boot
from preconfigured VIA RAID arrays.
Tested on ECS VX900-I.
Also add the VX11 chipset to the controller name, as it shares the same PCI ID.
viaide(4): Improve VT8251 integrated SATA controller support in IDE/RAID modes.
Use via_chip_map() to attach this controller in IDE and RAID modes, similarly
to VX800. This allows drives to be identified and attached successfully on all
four ports (two channels with master/slave ports).
Switch channel setup to sata_setup_channel(), replacing via_setup_channel().
This avoids writes to the 0x50 register, which is only relevant for IDE
controllers. Writes to SATA controller registers caused drives on the IDE
controller (0x0571) to fail to attach. Apply this fix also to VX900 and VT8261.
Rename VT8237R_SATA to VT8251_SATA (0x3349 is not used for VT8237R, AFAIK).
This PCI ID is used in RAID mode on newer (CE) chipset revision and in all
modes (IDE/RAID/AHCI) on older revision.
Add the 0x5287 PCI ID, used in IDE mode on newer (CE) chipset revision.
Rename VT8251_SATA to VT8251_AHCI (0x6287 is used only in AHCI mode).
Add VT8251_AHCI to the ahcisata(4) quirk list, same as VT8251_SATA.
For more details, see the tech-kern thread:
https://mail-index.netbsd.org/tech-kern/2025/04/13/msg030365.html
Should fix and close PR kern/37517.
Tested on Asus A8V-VM (CD) and MSI MS-7318 (CE) motherboards.
Reviewed by bad.
viaide(4): check if chip enable register returns 0 before emulating enable
bits.
At least some VT6410 controllers have register exposed. In fact, some
motherboards allow to control IDE channels (enable/disable them).
viaide(4): update the list of supported VIA controllers.
viaide(4): remove notes section about VT6421, it is not currently required to
setup RAID/JBOD sets to access drives.
 1.68.2.3  13-Oct-2023  martin Pull up following revision(s) (requested by abs in ticket #403):

sys/dev/pci/ahcisata_pci.c: revision 1.71

Add support for ASMEDIA 0x0624
... an AHCI SATA adaptor which identifies itself as an IDE storage device
 1.68.2.2  11-Sep-2023  martin Pull up following revision(s) (requested by abs in ticket #366):

sys/dev/pci/ahcisata_pci.c: revision 1.70
sys/dev/ic/ahcisata_core.c: revision 1.108
sys/dev/ic/ahcisatavar.h: revision 1.28
sys/conf/files: revision 1.1309

Rework AHCISATA_EXTRA_DELAY for kern/56737
- Remove AHCI_QUIRK_EXTRA_DELAY as issue appears to be drive and
not controller related
- Replace AHCISATA_EXTRA_DELAY with AHCISATA_REMOVE_EXTRA_DELAY,
so defaulting to enabling the extra delay, as the downside of
slower probing on systems which do not need it is less than having
other systems intermittently fail to probe and attach drives
- Also allow disabling extra delay with AHCISATA_EXTRA_DELAY_MS = 0

We should return to this code to work out which of the extra delays
are needed, and how long they need to be. It may be that faster
systems are more likely to trigger the issue (I've only seen it on
a 13th gen i7-13700, though only tested on a limited set)
 1.68.2.1  22-Aug-2023  martin Pull up following revision(s) (requested by tnn in ticket #334):

sys/dev/pci/ahcisata_pci.c: revision 1.69

ahcisata: ASM106x needs EXTRA_DELAY quirk
 1.71.6.1  02-Aug-2025  perseant Sync with HEAD

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