ahcisata_pci.c revision 1.36 1 1.36 christos /* $NetBSD: ahcisata_pci.c,v 1.36 2014/03/29 19:28:24 christos Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2006 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer *
15 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 1.1 bouyer *
26 1.1 bouyer */
27 1.1 bouyer
28 1.1 bouyer #include <sys/cdefs.h>
29 1.36 christos __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.36 2014/03/29 19:28:24 christos Exp $");
30 1.1 bouyer
31 1.1 bouyer #include <sys/types.h>
32 1.1 bouyer #include <sys/malloc.h>
33 1.1 bouyer #include <sys/param.h>
34 1.1 bouyer #include <sys/kernel.h>
35 1.1 bouyer #include <sys/systm.h>
36 1.1 bouyer #include <sys/disklabel.h>
37 1.2 jmcneill #include <sys/pmf.h>
38 1.1 bouyer
39 1.1 bouyer #include <dev/pci/pcivar.h>
40 1.1 bouyer #include <dev/pci/pcidevs.h>
41 1.1 bouyer #include <dev/pci/pciidereg.h>
42 1.1 bouyer #include <dev/pci/pciidevar.h>
43 1.1 bouyer #include <dev/ic/ahcisatavar.h>
44 1.1 bouyer
45 1.20 jakllsch struct ahci_pci_quirk {
46 1.20 jakllsch pci_vendor_id_t vendor; /* Vendor ID */
47 1.20 jakllsch pci_product_id_t product; /* Product ID */
48 1.30 bouyer int quirks; /* quirks; same as sc_ahci_quirks */
49 1.20 jakllsch };
50 1.20 jakllsch
51 1.20 jakllsch static const struct ahci_pci_quirk ahci_pci_quirks[] = {
52 1.12 dillo { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
53 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
54 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
55 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
56 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
57 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
58 1.14 dholland { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
59 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
60 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
61 1.28 bouyer AHCI_QUIRK_BADPMP },
62 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
63 1.28 bouyer AHCI_QUIRK_BADPMP },
64 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
65 1.28 bouyer AHCI_QUIRK_BADPMP },
66 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
67 1.28 bouyer AHCI_QUIRK_BADPMP },
68 1.12 dillo { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
69 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
70 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
71 1.28 bouyer AHCI_QUIRK_BADPMP },
72 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
73 1.28 bouyer AHCI_QUIRK_BADPMP },
74 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
75 1.28 bouyer AHCI_QUIRK_BADPMP },
76 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
77 1.28 bouyer AHCI_QUIRK_BADPMP },
78 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
79 1.28 bouyer AHCI_QUIRK_BADPMP },
80 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
81 1.28 bouyer AHCI_QUIRK_BADPMP },
82 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
83 1.28 bouyer AHCI_QUIRK_BADPMP },
84 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
85 1.28 bouyer AHCI_QUIRK_BADPMP },
86 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
87 1.28 bouyer AHCI_QUIRK_BADPMP },
88 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
89 1.28 bouyer AHCI_QUIRK_BADPMP },
90 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
91 1.28 bouyer AHCI_QUIRK_BADPMP },
92 1.13 tron { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
93 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
94 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
95 1.28 bouyer AHCI_QUIRK_BADPMP },
96 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
97 1.28 bouyer AHCI_QUIRK_BADPMP },
98 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
99 1.28 bouyer AHCI_QUIRK_BADPMP },
100 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
101 1.28 bouyer AHCI_QUIRK_BADPMP },
102 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
103 1.28 bouyer AHCI_QUIRK_BADPMP },
104 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
105 1.28 bouyer AHCI_QUIRK_BADPMP },
106 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
107 1.28 bouyer AHCI_QUIRK_BADPMP },
108 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
109 1.28 bouyer AHCI_QUIRK_BADPMP },
110 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
111 1.28 bouyer AHCI_QUIRK_BADPMP },
112 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
113 1.28 bouyer AHCI_QUIRK_BADPMP },
114 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
115 1.28 bouyer AHCI_QUIRK_BADPMP },
116 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
117 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
118 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
119 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
120 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
121 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
122 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
123 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
124 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
125 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
126 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
127 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
128 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
129 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
130 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
131 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
132 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
133 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
134 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
135 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
136 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
137 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
138 1.22 jmcneill { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
139 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
140 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
141 1.28 bouyer AHCI_QUIRK_BADPMP },
142 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
143 1.28 bouyer AHCI_QUIRK_BADPMP },
144 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
145 1.28 bouyer AHCI_QUIRK_BADPMP },
146 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
147 1.28 bouyer AHCI_QUIRK_BADPMP },
148 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
149 1.28 bouyer AHCI_QUIRK_BADPMP },
150 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
151 1.28 bouyer AHCI_QUIRK_BADPMP },
152 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
153 1.28 bouyer AHCI_QUIRK_BADPMP },
154 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
155 1.28 bouyer AHCI_QUIRK_BADPMP },
156 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
157 1.28 bouyer AHCI_QUIRK_BADPMP },
158 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
159 1.28 bouyer AHCI_QUIRK_BADPMP },
160 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
161 1.28 bouyer AHCI_QUIRK_BADPMP },
162 1.28 bouyer { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
163 1.28 bouyer AHCI_QUIRK_BADPMP },
164 1.25 matt { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
165 1.25 matt AHCI_PCI_QUIRK_FORCE },
166 1.15 cegger { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
167 1.28 bouyer AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
168 1.28 bouyer { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
169 1.28 bouyer AHCI_QUIRK_BADPMP },
170 1.35 msaitoh { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
171 1.26 jakllsch AHCI_PCI_QUIRK_FORCE },
172 1.21 jakllsch /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
173 1.21 jakllsch { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
174 1.28 bouyer AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMPRESET },
175 1.28 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
176 1.28 bouyer AHCI_QUIRK_BADPMPRESET },
177 1.28 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
178 1.28 bouyer AHCI_QUIRK_BADPMPRESET },
179 1.28 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
180 1.28 bouyer AHCI_QUIRK_BADPMPRESET },
181 1.28 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_FC,
182 1.28 bouyer AHCI_QUIRK_BADPMPRESET },
183 1.28 bouyer { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
184 1.28 bouyer AHCI_QUIRK_BADPMPRESET },
185 1.28 bouyer { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
186 1.28 bouyer AHCI_QUIRK_BADPMP },
187 1.28 bouyer { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
188 1.28 bouyer AHCI_QUIRK_BADPMP },
189 1.31 matt { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
190 1.31 matt AHCI_PCI_QUIRK_FORCE },
191 1.31 matt { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
192 1.31 matt AHCI_PCI_QUIRK_FORCE },
193 1.31 matt { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
194 1.31 matt AHCI_PCI_QUIRK_FORCE },
195 1.31 matt { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
196 1.31 matt AHCI_PCI_QUIRK_FORCE },
197 1.12 dillo };
198 1.12 dillo
199 1.2 jmcneill struct ahci_pci_softc {
200 1.9 cube struct ahci_softc ah_sc;
201 1.2 jmcneill pci_chipset_tag_t sc_pc;
202 1.2 jmcneill pcitag_t sc_pcitag;
203 1.20 jakllsch void * sc_ih;
204 1.2 jmcneill };
205 1.2 jmcneill
206 1.28 bouyer static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
207 1.9 cube static int ahci_pci_match(device_t, cfdata_t, void *);
208 1.9 cube static void ahci_pci_attach(device_t, device_t, void *);
209 1.20 jakllsch static int ahci_pci_detach(device_t, int);
210 1.19 dyoung static bool ahci_pci_resume(device_t, const pmf_qual_t *);
211 1.2 jmcneill
212 1.1 bouyer
213 1.9 cube CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
214 1.20 jakllsch ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL);
215 1.20 jakllsch
216 1.28 bouyer static int
217 1.28 bouyer ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
218 1.20 jakllsch {
219 1.20 jakllsch int i;
220 1.20 jakllsch
221 1.20 jakllsch for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
222 1.20 jakllsch if (vendor == ahci_pci_quirks[i].vendor &&
223 1.20 jakllsch product == ahci_pci_quirks[i].product)
224 1.28 bouyer return ahci_pci_quirks[i].quirks;
225 1.28 bouyer return 0;
226 1.20 jakllsch }
227 1.1 bouyer
228 1.1 bouyer static int
229 1.9 cube ahci_pci_match(device_t parent, cfdata_t match, void *aux)
230 1.1 bouyer {
231 1.1 bouyer struct pci_attach_args *pa = aux;
232 1.1 bouyer bus_space_tag_t regt;
233 1.1 bouyer bus_space_handle_t regh;
234 1.1 bouyer bus_size_t size;
235 1.1 bouyer int ret = 0;
236 1.20 jakllsch bool force;
237 1.12 dillo
238 1.28 bouyer force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
239 1.28 bouyer PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
240 1.1 bouyer
241 1.12 dillo /* if wrong class and not forced by quirks, don't match */
242 1.12 dillo if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
243 1.12 dillo ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
244 1.12 dillo PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
245 1.12 dillo PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
246 1.20 jakllsch (force == false))
247 1.12 dillo return 0;
248 1.12 dillo
249 1.12 dillo if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
250 1.12 dillo PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
251 1.12 dillo ®t, ®h, NULL, &size) != 0)
252 1.12 dillo return 0;
253 1.12 dillo
254 1.12 dillo if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
255 1.3 xtraeme PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
256 1.20 jakllsch (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
257 1.20 jakllsch (force == true))
258 1.12 dillo ret = 3;
259 1.1 bouyer
260 1.12 dillo bus_space_unmap(regt, regh, size);
261 1.5 jnemeth return ret;
262 1.1 bouyer }
263 1.1 bouyer
264 1.1 bouyer static void
265 1.9 cube ahci_pci_attach(device_t parent, device_t self, void *aux)
266 1.1 bouyer {
267 1.1 bouyer struct pci_attach_args *pa = aux;
268 1.9 cube struct ahci_pci_softc *psc = device_private(self);
269 1.2 jmcneill struct ahci_softc *sc = &psc->ah_sc;
270 1.1 bouyer const char *intrstr;
271 1.21 jakllsch bool ahci_cap_64bit;
272 1.21 jakllsch bool ahci_bad_64bit;
273 1.1 bouyer pci_intr_handle_t intrhandle;
274 1.36 christos char intrbuf[PCI_INTRSTR_LEN];
275 1.1 bouyer
276 1.11 cube sc->sc_atac.atac_dev = self;
277 1.10 cube
278 1.1 bouyer if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
279 1.1 bouyer PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
280 1.20 jakllsch &sc->sc_ahcit, &sc->sc_ahcih, NULL, &sc->sc_ahcis) != 0) {
281 1.9 cube aprint_error_dev(self, "can't map ahci registers\n");
282 1.1 bouyer return;
283 1.1 bouyer }
284 1.2 jmcneill psc->sc_pc = pa->pa_pc;
285 1.2 jmcneill psc->sc_pcitag = pa->pa_tag;
286 1.2 jmcneill
287 1.27 drochner pci_aprint_devinfo(pa, "AHCI disk controller");
288 1.1 bouyer
289 1.1 bouyer if (pci_intr_map(pa, &intrhandle) != 0) {
290 1.20 jakllsch aprint_error_dev(self, "couldn't map interrupt\n");
291 1.1 bouyer return;
292 1.1 bouyer }
293 1.36 christos intrstr = pci_intr_string(pa->pa_pc, intrhandle,
294 1.36 christos intrbuf, sizeof(intrbuf));
295 1.20 jakllsch psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc);
296 1.20 jakllsch if (psc->sc_ih == NULL) {
297 1.20 jakllsch aprint_error_dev(self, "couldn't establish interrupt\n");
298 1.1 bouyer return;
299 1.1 bouyer }
300 1.36 christos aprint_normal_dev(self, "interrupting at %s\n", intrstr);
301 1.21 jakllsch
302 1.1 bouyer sc->sc_dmat = pa->pa_dmat;
303 1.3 xtraeme
304 1.30 bouyer sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
305 1.28 bouyer PCI_PRODUCT(pa->pa_id));
306 1.28 bouyer
307 1.21 jakllsch ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
308 1.30 bouyer ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
309 1.21 jakllsch
310 1.21 jakllsch if (pci_dma64_available(pa) && ahci_cap_64bit) {
311 1.21 jakllsch if (!ahci_bad_64bit)
312 1.21 jakllsch sc->sc_dmat = pa->pa_dmat64;
313 1.21 jakllsch aprint_verbose_dev(self, "64-bit DMA%s\n",
314 1.21 jakllsch (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
315 1.21 jakllsch }
316 1.21 jakllsch
317 1.6 mlelstv if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
318 1.7 mlelstv AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
319 1.3 xtraeme sc->sc_atac_capflags = ATAC_CAP_RAID;
320 1.6 mlelstv } else {
321 1.7 mlelstv AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
322 1.6 mlelstv }
323 1.3 xtraeme
324 1.1 bouyer ahci_attach(sc);
325 1.2 jmcneill
326 1.2 jmcneill if (!pmf_device_register(self, NULL, ahci_pci_resume))
327 1.2 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
328 1.2 jmcneill }
329 1.2 jmcneill
330 1.20 jakllsch static int
331 1.20 jakllsch ahci_pci_detach(device_t dv, int flags)
332 1.20 jakllsch {
333 1.20 jakllsch struct ahci_pci_softc *psc;
334 1.20 jakllsch struct ahci_softc *sc;
335 1.20 jakllsch int rv;
336 1.20 jakllsch
337 1.20 jakllsch psc = device_private(dv);
338 1.20 jakllsch sc = &psc->ah_sc;
339 1.20 jakllsch
340 1.20 jakllsch if ((rv = ahci_detach(sc, flags)))
341 1.20 jakllsch return rv;
342 1.20 jakllsch
343 1.24 dyoung pmf_device_deregister(dv);
344 1.24 dyoung
345 1.20 jakllsch if (psc->sc_ih != NULL)
346 1.20 jakllsch pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
347 1.20 jakllsch
348 1.20 jakllsch bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
349 1.20 jakllsch
350 1.20 jakllsch return 0;
351 1.20 jakllsch }
352 1.20 jakllsch
353 1.2 jmcneill static bool
354 1.19 dyoung ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
355 1.2 jmcneill {
356 1.2 jmcneill struct ahci_pci_softc *psc = device_private(dv);
357 1.2 jmcneill struct ahci_softc *sc = &psc->ah_sc;
358 1.2 jmcneill int s;
359 1.2 jmcneill
360 1.2 jmcneill s = splbio();
361 1.20 jakllsch ahci_resume(sc);
362 1.2 jmcneill splx(s);
363 1.2 jmcneill
364 1.2 jmcneill return true;
365 1.1 bouyer }
366