ahcisata_pci.c revision 1.1.12.1
1 /* $NetBSD: ahcisata_pci.c,v 1.1.12.1 2007/08/04 18:20:51 he Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.1.12.1 2007/08/04 18:20:51 he Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/pnp.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 struct ahci_pci_softc { 53 struct ahci_softc ah_sc; /* must come first, struct device */ 54 pci_chipset_tag_t sc_pc; 55 pcitag_t sc_pcitag; 56 struct pci_conf_state sc_pciconf; 57 }; 58 59 60 static int ahci_pci_match(struct device *, struct cfdata *, void *); 61 static void ahci_pci_attach(struct device *, struct device *, void *); 62 63 static pnp_status_t ahci_pci_power(device_t, pnp_request_t, void *); 64 65 66 CFATTACH_DECL(ahcisata_pci, sizeof(struct ahci_pci_softc), 67 ahci_pci_match, ahci_pci_attach, NULL, NULL); 68 69 static int 70 ahci_pci_match(struct device *parent, struct cfdata *match, 71 void *aux) 72 { 73 struct pci_attach_args *pa = aux; 74 bus_space_tag_t regt; 75 bus_space_handle_t regh; 76 bus_size_t size; 77 int ret = 0; 78 79 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 80 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 81 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) { 82 /* check if the chip is in ahci mode */ 83 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 84 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 85 ®t, ®h, NULL, &size) != 0) 86 return (0); 87 if (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) 88 ret = 3; 89 bus_space_unmap(regt, regh, size); 90 return (3); 91 } 92 93 return (ret); 94 } 95 96 static void 97 ahci_pci_attach(struct device *parent, struct device *self, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)self; 101 struct ahci_softc *sc = &psc->ah_sc; 102 bus_size_t size; 103 char devinfo[256]; 104 const char *intrstr; 105 pci_intr_handle_t intrhandle; 106 void *ih; 107 108 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 109 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 110 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) { 111 aprint_error("%s: can't map ahci registers\n", AHCINAME(sc)); 112 return; 113 } 114 psc->sc_pc = pa->pa_pc; 115 psc->sc_pcitag = pa->pa_tag; 116 117 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 118 aprint_naive(": AHCI disk controller\n"); 119 aprint_normal(": %s\n", devinfo); 120 121 if (pci_intr_map(pa, &intrhandle) != 0) { 122 aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc)); 123 return; 124 } 125 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 126 ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 127 if (ih == NULL) { 128 aprint_error("%s: couldn't establish interrupt", AHCINAME(sc)); 129 return; 130 } 131 aprint_normal("%s: interrupting at %s\n", AHCINAME(sc), 132 intrstr ? intrstr : "unknown interrupt"); 133 sc->sc_dmat = pa->pa_dmat; 134 ahci_attach(sc); 135 136 /* register device power management */ 137 pnp_register(self, ahci_pci_power); 138 } 139 140 static pnp_status_t 141 ahci_pci_power(device_t dv, pnp_request_t req, void *opaque) 142 { 143 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)dv; 144 struct ahci_softc *sc = &psc->ah_sc; 145 pnp_status_t status; 146 pnp_state_t *state; 147 pnp_capabilities_t *caps; 148 pci_chipset_tag_t pc; 149 pcireg_t val; 150 pcitag_t tag; 151 int off, s; 152 153 status = PNP_STATUS_UNSUPPORTED; 154 pc = psc->sc_pc; 155 tag = psc->sc_pcitag; 156 157 switch (req) { 158 case PNP_REQUEST_GET_CAPABILITIES: 159 caps = opaque; 160 161 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &off, &val)) 162 return PNP_STATUS_UNSUPPORTED; 163 caps->state = pci_pnp_capabilities(val); 164 status = PNP_STATUS_SUCCESS; 165 break; 166 case PNP_REQUEST_SET_STATE: 167 state = opaque; 168 switch (*state) { 169 case PNP_STATE_D0: 170 val = PCI_PMCSR_STATE_D0; 171 break; 172 case PNP_STATE_D3: 173 val = PCI_PMCSR_STATE_D3; 174 s = splbio(); 175 pci_conf_capture(pc, tag, &psc->sc_pciconf); 176 splx(s); 177 break; 178 default: 179 return PNP_STATUS_UNSUPPORTED; 180 } 181 182 if (pci_set_powerstate(pc, tag, val) == 0) { 183 status = PNP_STATUS_SUCCESS; 184 if (*state != PNP_STATE_D0) 185 break; 186 187 s = splbio(); 188 pci_conf_restore(pc, tag, &psc->sc_pciconf); 189 190 ahci_reset(sc); 191 ahci_setup_ports(sc); 192 ahci_reprobe_drives(sc); 193 ahci_enable_intrs(sc); 194 195 splx(s); 196 } 197 case PNP_REQUEST_GET_STATE: 198 state = opaque; 199 if (pci_get_powerstate(pc, tag, &val) != 0) 200 return PNP_STATUS_UNSUPPORTED; 201 202 *state = pci_pnp_powerstate(val); 203 status = PNP_STATUS_SUCCESS; 204 break; 205 default: 206 status = PNP_STATUS_UNSUPPORTED; 207 break; 208 } 209 return status; 210 } 211
Indexes created Fri Oct 03 02:09:57 GMT 2025