ahcisata_pci.c revision 1.12.4.2.4.1
1 /* $NetBSD: ahcisata_pci.c,v 1.12.4.2.4.1 2013/11/05 18:32:45 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.12.4.2.4.1 2013/11/05 18:32:45 matt Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/pmf.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 #define AHCI_PCI_QUIRK_FORCE 1 /* force attach */ 53 #define AHCI_PCI_QUIRK_BAR0 2 54 55 static const struct pci_quirkdata ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 65 AHCI_PCI_QUIRK_FORCE }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 67 AHCI_PCI_QUIRK_FORCE }, 68 { PCI_VENDOR_NETLOGIC, PCI_PRODUCT_NETLOGIC_XLP_AHCISATA, 69 AHCI_PCI_QUIRK_BAR0 }, 70 }; 71 72 struct ahci_pci_softc { 73 struct ahci_softc ah_sc; 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 }; 77 78 79 static int ahci_pci_match(device_t, cfdata_t, void *); 80 static void ahci_pci_attach(device_t, device_t, void *); 81 const struct pci_quirkdata *ahci_pci_lookup_quirkdata(pci_vendor_id_t, 82 pci_product_id_t); 83 static bool ahci_pci_resume(device_t PMF_FN_PROTO); 84 85 86 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 87 ahci_pci_match, ahci_pci_attach, NULL, NULL); 88 89 static int 90 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 91 { 92 struct pci_attach_args *pa = aux; 93 bus_space_tag_t regt; 94 bus_space_handle_t regh; 95 bus_size_t size; 96 int ret = 0; 97 const struct pci_quirkdata *quirks; 98 int bar = AHCI_PCI_ABAR; 99 100 quirks = ahci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 101 PCI_PRODUCT(pa->pa_id)); 102 103 /* if wrong class and not forced by quirks, don't match */ 104 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 105 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 106 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 107 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 108 (quirks == NULL || (quirks->quirks & AHCI_PCI_QUIRK_FORCE) == 0)) 109 return 0; 110 111 /* 112 * Sometimes people just can't read specs. 113 */ 114 if (quirks != NULL && (quirks->quirks & AHCI_PCI_QUIRK_BAR0)) { 115 bar = PCI_BAR0; 116 } 117 118 pcireg_t mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 119 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 120 printf("%s: tag %#lx: unexpected type %#x\n", 121 __func__, pa->pa_tag, mem_type); 122 return 0; 123 } 124 125 if (pci_mapreg_map(pa, bar, mem_type, 0, 126 ®t, ®h, NULL, &size) != 0) { 127 printf("%s: tag %#lx: pci_mapreg_map failed\n", 128 __func__, pa->pa_tag); 129 return 0; 130 } 131 132 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 133 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 134 (quirks && quirks->quirks & AHCI_PCI_QUIRK_FORCE) || 135 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE)) 136 ret = 3; 137 138 bus_space_unmap(regt, regh, size); 139 return ret; 140 } 141 142 static void 143 ahci_pci_attach(device_t parent, device_t self, void *aux) 144 { 145 struct pci_attach_args *pa = aux; 146 struct ahci_pci_softc *psc = device_private(self); 147 struct ahci_softc *sc = &psc->ah_sc; 148 bus_size_t size; 149 char devinfo[256]; 150 const char *intrstr; 151 pci_intr_handle_t intrhandle; 152 void *ih; 153 const struct pci_quirkdata *quirks; 154 int bar = AHCI_PCI_ABAR; 155 156 sc->sc_atac.atac_dev = self; 157 158 /* 159 * Sometimes people just can't read specs. 160 */ 161 quirks = ahci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 162 PCI_PRODUCT(pa->pa_id)); 163 if (quirks != NULL && (quirks->quirks & AHCI_PCI_QUIRK_BAR0)) { 164 bar = PCI_BAR0; 165 } 166 167 if (pci_mapreg_map(pa, bar, PCI_MAPREG_TYPE_MEM, 0, 168 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) { 169 aprint_error_dev(self, ": can't map ahci registers\n"); 170 return; 171 } 172 psc->sc_pc = pa->pa_pc; 173 psc->sc_pcitag = pa->pa_tag; 174 175 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 176 aprint_naive(": AHCI disk controller\n"); 177 aprint_normal(": %s\n", devinfo); 178 179 if (pci_intr_map(pa, &intrhandle) != 0) { 180 aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc)); 181 return; 182 } 183 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 184 ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 185 if (ih == NULL) { 186 aprint_error("%s: couldn't establish interrupt", AHCINAME(sc)); 187 return; 188 } 189 aprint_normal("%s: interrupting at %s\n", AHCINAME(sc), 190 intrstr ? intrstr : "unknown interrupt"); 191 sc->sc_dmat = pa->pa_dmat; 192 193 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 194 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 195 sc->sc_atac_capflags = ATAC_CAP_RAID; 196 } else { 197 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 198 } 199 200 ahci_attach(sc); 201 202 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 203 aprint_error_dev(self, "couldn't establish power handler\n"); 204 } 205 206 static bool 207 ahci_pci_resume(device_t dv PMF_FN_ARGS) 208 { 209 struct ahci_pci_softc *psc = device_private(dv); 210 struct ahci_softc *sc = &psc->ah_sc; 211 int s; 212 213 s = splbio(); 214 ahci_reset(sc); 215 ahci_setup_ports(sc); 216 ahci_reprobe_drives(sc); 217 ahci_enable_intrs(sc); 218 splx(s); 219 220 return true; 221 } 222 223 const struct pci_quirkdata * 224 ahci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 225 { 226 int i; 227 228 for (i = 0; i < (sizeof ahci_pci_quirks / sizeof ahci_pci_quirks[0]); 229 i++) 230 if (vendor == ahci_pci_quirks[i].vendor && 231 product == ahci_pci_quirks[i].product) 232 return (&ahci_pci_quirks[i]); 233 return (NULL); 234 } 235
Indexes created Thu Oct 02 14:10:14 GMT 2025