ahcisata_pci.c revision 1.12.4.3
1 /* $NetBSD: ahcisata_pci.c,v 1.12.4.3 2010/11/21 19:29:30 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.12.4.3 2010/11/21 19:29:30 riz Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/pmf.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/ic/ahcisatavar.h> 51 52 #define AHCI_PCI_QUIRK_FORCE 1 /* force attach */ 53 54 static const struct pci_quirkdata ahci_pci_quirks[] = { 55 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 56 AHCI_PCI_QUIRK_FORCE }, 57 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 58 AHCI_PCI_QUIRK_FORCE }, 59 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 60 AHCI_PCI_QUIRK_FORCE }, 61 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 62 AHCI_PCI_QUIRK_FORCE }, 63 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 64 AHCI_PCI_QUIRK_FORCE }, 65 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 66 AHCI_PCI_QUIRK_FORCE }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 68 AHCI_PCI_QUIRK_FORCE }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 70 AHCI_PCI_QUIRK_FORCE }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 72 AHCI_PCI_QUIRK_FORCE }, 73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 74 AHCI_PCI_QUIRK_FORCE }, 75 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 76 AHCI_PCI_QUIRK_FORCE }, 77 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 78 AHCI_PCI_QUIRK_FORCE }, 79 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 80 AHCI_PCI_QUIRK_FORCE }, 81 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 82 AHCI_PCI_QUIRK_FORCE }, 83 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 84 AHCI_PCI_QUIRK_FORCE }, 85 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 86 AHCI_PCI_QUIRK_FORCE }, 87 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 88 AHCI_PCI_QUIRK_FORCE }, 89 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 90 AHCI_PCI_QUIRK_FORCE }, 91 }; 92 93 struct ahci_pci_softc { 94 struct ahci_softc ah_sc; 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 }; 98 99 100 static int ahci_pci_match(device_t, cfdata_t, void *); 101 static void ahci_pci_attach(device_t, device_t, void *); 102 const struct pci_quirkdata *ahci_pci_lookup_quirkdata(pci_vendor_id_t, 103 pci_product_id_t); 104 static bool ahci_pci_resume(device_t PMF_FN_PROTO); 105 106 107 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 108 ahci_pci_match, ahci_pci_attach, NULL, NULL); 109 110 static int 111 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 112 { 113 struct pci_attach_args *pa = aux; 114 bus_space_tag_t regt; 115 bus_space_handle_t regh; 116 bus_size_t size; 117 int ret = 0; 118 const struct pci_quirkdata *quirks; 119 120 quirks = ahci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 121 PCI_PRODUCT(pa->pa_id)); 122 123 /* if wrong class and not forced by quirks, don't match */ 124 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 125 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 126 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 127 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 128 (quirks == NULL || (quirks->quirks & AHCI_PCI_QUIRK_FORCE) == 0)) 129 return 0; 130 131 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 132 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 133 ®t, ®h, NULL, &size) != 0) 134 return 0; 135 136 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 137 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 138 (quirks && quirks->quirks & AHCI_PCI_QUIRK_FORCE) || 139 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE)) 140 ret = 3; 141 142 bus_space_unmap(regt, regh, size); 143 return ret; 144 } 145 146 static void 147 ahci_pci_attach(device_t parent, device_t self, void *aux) 148 { 149 struct pci_attach_args *pa = aux; 150 struct ahci_pci_softc *psc = device_private(self); 151 struct ahci_softc *sc = &psc->ah_sc; 152 bus_size_t size; 153 char devinfo[256]; 154 const char *intrstr; 155 pci_intr_handle_t intrhandle; 156 void *ih; 157 158 sc->sc_atac.atac_dev = self; 159 160 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 161 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 162 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) { 163 aprint_error_dev(self, "can't map ahci registers\n"); 164 return; 165 } 166 psc->sc_pc = pa->pa_pc; 167 psc->sc_pcitag = pa->pa_tag; 168 169 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 170 aprint_naive(": AHCI disk controller\n"); 171 aprint_normal(": %s\n", devinfo); 172 173 if (pci_intr_map(pa, &intrhandle) != 0) { 174 aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc)); 175 return; 176 } 177 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 178 ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 179 if (ih == NULL) { 180 aprint_error("%s: couldn't establish interrupt", AHCINAME(sc)); 181 return; 182 } 183 aprint_normal("%s: interrupting at %s\n", AHCINAME(sc), 184 intrstr ? intrstr : "unknown interrupt"); 185 sc->sc_dmat = pa->pa_dmat; 186 187 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 188 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 189 sc->sc_atac_capflags = ATAC_CAP_RAID; 190 } else { 191 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 192 } 193 194 ahci_attach(sc); 195 196 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 197 aprint_error_dev(self, "couldn't establish power handler\n"); 198 } 199 200 static bool 201 ahci_pci_resume(device_t dv PMF_FN_ARGS) 202 { 203 struct ahci_pci_softc *psc = device_private(dv); 204 struct ahci_softc *sc = &psc->ah_sc; 205 int s; 206 207 s = splbio(); 208 ahci_reset(sc); 209 ahci_setup_ports(sc); 210 ahci_reprobe_drives(sc); 211 ahci_enable_intrs(sc); 212 splx(s); 213 214 return true; 215 } 216 217 const struct pci_quirkdata * 218 ahci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 219 { 220 int i; 221 222 for (i = 0; i < (sizeof ahci_pci_quirks / sizeof ahci_pci_quirks[0]); 223 i++) 224 if (vendor == ahci_pci_quirks[i].vendor && 225 product == ahci_pci_quirks[i].product) 226 return (&ahci_pci_quirks[i]); 227 return (NULL); 228 } 229
Indexes created Thu Oct 02 14:10:14 GMT 2025