ahcisata_pci.c revision 1.19
1 /* $NetBSD: ahcisata_pci.c,v 1.19 2010/02/24 22:37:59 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.19 2010/02/24 22:37:59 dyoung Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/pmf.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pciidereg.h> 44 #include <dev/pci/pciidevar.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 #define AHCI_PCI_QUIRK_FORCE 1 /* force attach */ 48 49 static const struct pci_quirkdata ahci_pci_quirks[] = { 50 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 51 AHCI_PCI_QUIRK_FORCE }, 52 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 53 AHCI_PCI_QUIRK_FORCE }, 54 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 55 AHCI_PCI_QUIRK_FORCE }, 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 57 AHCI_PCI_QUIRK_FORCE }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 59 AHCI_PCI_QUIRK_FORCE }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 61 AHCI_PCI_QUIRK_FORCE }, 62 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 63 AHCI_PCI_QUIRK_FORCE }, 64 }; 65 66 struct ahci_pci_softc { 67 struct ahci_softc ah_sc; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_pcitag; 70 }; 71 72 73 static int ahci_pci_match(device_t, cfdata_t, void *); 74 static void ahci_pci_attach(device_t, device_t, void *); 75 const struct pci_quirkdata *ahci_pci_lookup_quirkdata(pci_vendor_id_t, 76 pci_product_id_t); 77 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 78 79 80 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 81 ahci_pci_match, ahci_pci_attach, NULL, NULL); 82 83 static int 84 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 bus_space_tag_t regt; 88 bus_space_handle_t regh; 89 bus_size_t size; 90 int ret = 0; 91 const struct pci_quirkdata *quirks; 92 93 quirks = ahci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 94 PCI_PRODUCT(pa->pa_id)); 95 96 /* if wrong class and not forced by quirks, don't match */ 97 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 98 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 99 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 100 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 101 (quirks == NULL || (quirks->quirks & AHCI_PCI_QUIRK_FORCE) == 0)) 102 return 0; 103 104 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 105 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 106 ®t, ®h, NULL, &size) != 0) 107 return 0; 108 109 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 110 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 111 (quirks && quirks->quirks & AHCI_PCI_QUIRK_FORCE) || 112 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE)) 113 ret = 3; 114 115 bus_space_unmap(regt, regh, size); 116 return ret; 117 } 118 119 static void 120 ahci_pci_attach(device_t parent, device_t self, void *aux) 121 { 122 struct pci_attach_args *pa = aux; 123 struct ahci_pci_softc *psc = device_private(self); 124 struct ahci_softc *sc = &psc->ah_sc; 125 bus_size_t size; 126 char devinfo[256]; 127 const char *intrstr; 128 pci_intr_handle_t intrhandle; 129 void *ih; 130 131 sc->sc_atac.atac_dev = self; 132 133 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 134 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 135 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) { 136 aprint_error_dev(self, "can't map ahci registers\n"); 137 return; 138 } 139 psc->sc_pc = pa->pa_pc; 140 psc->sc_pcitag = pa->pa_tag; 141 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 143 aprint_naive(": AHCI disk controller\n"); 144 aprint_normal(": %s\n", devinfo); 145 146 if (pci_intr_map(pa, &intrhandle) != 0) { 147 aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc)); 148 return; 149 } 150 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 151 ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 152 if (ih == NULL) { 153 aprint_error("%s: couldn't establish interrupt", AHCINAME(sc)); 154 return; 155 } 156 aprint_normal("%s: interrupting at %s\n", AHCINAME(sc), 157 intrstr ? intrstr : "unknown interrupt"); 158 sc->sc_dmat = pa->pa_dmat; 159 160 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 161 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 162 sc->sc_atac_capflags = ATAC_CAP_RAID; 163 } else { 164 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 165 } 166 167 ahci_attach(sc); 168 169 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 170 aprint_error_dev(self, "couldn't establish power handler\n"); 171 } 172 173 static bool 174 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 175 { 176 struct ahci_pci_softc *psc = device_private(dv); 177 struct ahci_softc *sc = &psc->ah_sc; 178 int s; 179 180 s = splbio(); 181 ahci_reset(sc); 182 ahci_setup_ports(sc); 183 ahci_reprobe_drives(sc); 184 ahci_enable_intrs(sc); 185 splx(s); 186 187 return true; 188 } 189 190 const struct pci_quirkdata * 191 ahci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 192 { 193 int i; 194 195 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 196 if (vendor == ahci_pci_quirks[i].vendor && 197 product == ahci_pci_quirks[i].product) 198 return (&ahci_pci_quirks[i]); 199 return (NULL); 200 } 201
Indexes created Tue Sep 30 20:09:53 GMT 2025