ahcisata_pci.c revision 1.20
1 /* $NetBSD: ahcisata_pci.c,v 1.20 2010/07/27 22:07:51 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.20 2010/07/27 22:07:51 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/pmf.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pciidereg.h> 44 #include <dev/pci/pciidevar.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 struct ahci_pci_quirk { 48 pci_vendor_id_t vendor; /* Vendor ID */ 49 pci_product_id_t product; /* Product ID */ 50 int quirks; /* quirks; see below */ 51 }; 52 53 #define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 65 AHCI_PCI_QUIRK_FORCE }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 67 AHCI_PCI_QUIRK_FORCE }, 68 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 69 AHCI_PCI_QUIRK_FORCE }, 70 }; 71 72 struct ahci_pci_softc { 73 struct ahci_softc ah_sc; 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 void * sc_ih; 77 }; 78 79 static bool ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t, int); 80 static int ahci_pci_match(device_t, cfdata_t, void *); 81 static void ahci_pci_attach(device_t, device_t, void *); 82 static int ahci_pci_detach(device_t, int); 83 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 84 85 86 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 87 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL); 88 89 static bool 90 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product, int quirk) 91 { 92 int i; 93 94 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 95 if (vendor == ahci_pci_quirks[i].vendor && 96 product == ahci_pci_quirks[i].product) 97 return (ahci_pci_quirks[i].quirks & quirk) != 0; 98 return false; 99 } 100 101 static int 102 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 103 { 104 struct pci_attach_args *pa = aux; 105 bus_space_tag_t regt; 106 bus_space_handle_t regh; 107 bus_size_t size; 108 int ret = 0; 109 bool force; 110 111 force = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 112 PCI_PRODUCT(pa->pa_id), 113 AHCI_PCI_QUIRK_FORCE); 114 115 /* if wrong class and not forced by quirks, don't match */ 116 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 117 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 118 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 119 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 120 (force == false)) 121 return 0; 122 123 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 124 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 125 ®t, ®h, NULL, &size) != 0) 126 return 0; 127 128 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 129 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 130 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 131 (force == true)) 132 ret = 3; 133 134 bus_space_unmap(regt, regh, size); 135 return ret; 136 } 137 138 static void 139 ahci_pci_attach(device_t parent, device_t self, void *aux) 140 { 141 struct pci_attach_args *pa = aux; 142 struct ahci_pci_softc *psc = device_private(self); 143 struct ahci_softc *sc = &psc->ah_sc; 144 char devinfo[256]; 145 const char *intrstr; 146 pci_intr_handle_t intrhandle; 147 148 sc->sc_atac.atac_dev = self; 149 150 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 151 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 152 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &sc->sc_ahcis) != 0) { 153 aprint_error_dev(self, "can't map ahci registers\n"); 154 return; 155 } 156 psc->sc_pc = pa->pa_pc; 157 psc->sc_pcitag = pa->pa_tag; 158 159 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 160 aprint_naive(": AHCI disk controller\n"); 161 aprint_normal(": %s\n", devinfo); 162 163 if (pci_intr_map(pa, &intrhandle) != 0) { 164 aprint_error_dev(self, "couldn't map interrupt\n"); 165 return; 166 } 167 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 168 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 169 if (psc->sc_ih == NULL) { 170 aprint_error_dev(self, "couldn't establish interrupt\n"); 171 return; 172 } 173 aprint_normal_dev(self, "interrupting at %s\n", 174 intrstr ? intrstr : "unknown interrupt"); 175 sc->sc_dmat = pa->pa_dmat; 176 177 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 178 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 179 sc->sc_atac_capflags = ATAC_CAP_RAID; 180 } else { 181 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 182 } 183 184 ahci_attach(sc); 185 186 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 187 aprint_error_dev(self, "couldn't establish power handler\n"); 188 } 189 190 static int 191 ahci_pci_detach(device_t dv, int flags) 192 { 193 struct ahci_pci_softc *psc; 194 struct ahci_softc *sc; 195 int rv; 196 197 psc = device_private(dv); 198 sc = &psc->ah_sc; 199 200 if ((rv = ahci_detach(sc, flags))) 201 return rv; 202 203 if (psc->sc_ih != NULL) 204 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 205 206 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 207 208 return 0; 209 } 210 211 static bool 212 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 213 { 214 struct ahci_pci_softc *psc = device_private(dv); 215 struct ahci_softc *sc = &psc->ah_sc; 216 int s; 217 218 s = splbio(); 219 ahci_resume(sc); 220 splx(s); 221 222 return true; 223 } 224
Indexes created Tue Sep 30 20:09:53 GMT 2025