ahcisata_pci.c revision 1.21
1 /* $NetBSD: ahcisata_pci.c,v 1.21 2010/07/27 22:27:52 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.21 2010/07/27 22:27:52 jakllsch Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/pmf.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pciidereg.h> 44 #include <dev/pci/pciidevar.h> 45 #include <dev/ic/ahcisatavar.h> 46 47 struct ahci_pci_quirk { 48 pci_vendor_id_t vendor; /* Vendor ID */ 49 pci_product_id_t product; /* Product ID */ 50 int quirks; /* quirks; see below */ 51 }; 52 53 #define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 54 #define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */ 55 56 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 57 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 58 AHCI_PCI_QUIRK_FORCE }, 59 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 60 AHCI_PCI_QUIRK_FORCE }, 61 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 62 AHCI_PCI_QUIRK_FORCE }, 63 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 64 AHCI_PCI_QUIRK_FORCE }, 65 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 66 AHCI_PCI_QUIRK_FORCE }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 68 AHCI_PCI_QUIRK_FORCE }, 69 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 70 AHCI_PCI_QUIRK_FORCE }, 71 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 72 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 73 AHCI_PCI_QUIRK_BAD64 }, 74 }; 75 76 struct ahci_pci_softc { 77 struct ahci_softc ah_sc; 78 pci_chipset_tag_t sc_pc; 79 pcitag_t sc_pcitag; 80 void * sc_ih; 81 }; 82 83 static bool ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t, int); 84 static int ahci_pci_match(device_t, cfdata_t, void *); 85 static void ahci_pci_attach(device_t, device_t, void *); 86 static int ahci_pci_detach(device_t, int); 87 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 88 89 90 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 91 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL); 92 93 static bool 94 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product, int quirk) 95 { 96 int i; 97 98 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 99 if (vendor == ahci_pci_quirks[i].vendor && 100 product == ahci_pci_quirks[i].product) 101 return (ahci_pci_quirks[i].quirks & quirk) != 0; 102 return false; 103 } 104 105 static int 106 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 107 { 108 struct pci_attach_args *pa = aux; 109 bus_space_tag_t regt; 110 bus_space_handle_t regh; 111 bus_size_t size; 112 int ret = 0; 113 bool force; 114 115 force = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 116 PCI_PRODUCT(pa->pa_id), 117 AHCI_PCI_QUIRK_FORCE); 118 119 /* if wrong class and not forced by quirks, don't match */ 120 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 121 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 122 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 123 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 124 (force == false)) 125 return 0; 126 127 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 128 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 129 ®t, ®h, NULL, &size) != 0) 130 return 0; 131 132 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 133 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 134 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 135 (force == true)) 136 ret = 3; 137 138 bus_space_unmap(regt, regh, size); 139 return ret; 140 } 141 142 static void 143 ahci_pci_attach(device_t parent, device_t self, void *aux) 144 { 145 struct pci_attach_args *pa = aux; 146 struct ahci_pci_softc *psc = device_private(self); 147 struct ahci_softc *sc = &psc->ah_sc; 148 char devinfo[256]; 149 const char *intrstr; 150 bool ahci_cap_64bit; 151 bool ahci_bad_64bit; 152 pci_intr_handle_t intrhandle; 153 154 sc->sc_atac.atac_dev = self; 155 156 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 157 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 158 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &sc->sc_ahcis) != 0) { 159 aprint_error_dev(self, "can't map ahci registers\n"); 160 return; 161 } 162 psc->sc_pc = pa->pa_pc; 163 psc->sc_pcitag = pa->pa_tag; 164 165 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 166 aprint_naive(": AHCI disk controller\n"); 167 aprint_normal(": %s\n", devinfo); 168 169 if (pci_intr_map(pa, &intrhandle) != 0) { 170 aprint_error_dev(self, "couldn't map interrupt\n"); 171 return; 172 } 173 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 174 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 175 if (psc->sc_ih == NULL) { 176 aprint_error_dev(self, "couldn't establish interrupt\n"); 177 return; 178 } 179 aprint_normal_dev(self, "interrupting at %s\n", 180 intrstr ? intrstr : "unknown interrupt"); 181 182 sc->sc_dmat = pa->pa_dmat; 183 184 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 185 ahci_bad_64bit = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 186 PCI_PRODUCT(pa->pa_id), 187 AHCI_PCI_QUIRK_BAD64); 188 189 if (pci_dma64_available(pa) && ahci_cap_64bit) { 190 if (!ahci_bad_64bit) 191 sc->sc_dmat = pa->pa_dmat64; 192 aprint_verbose_dev(self, "64-bit DMA%s\n", 193 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 194 } 195 196 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 197 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 198 sc->sc_atac_capflags = ATAC_CAP_RAID; 199 } else { 200 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 201 } 202 203 ahci_attach(sc); 204 205 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 206 aprint_error_dev(self, "couldn't establish power handler\n"); 207 } 208 209 static int 210 ahci_pci_detach(device_t dv, int flags) 211 { 212 struct ahci_pci_softc *psc; 213 struct ahci_softc *sc; 214 int rv; 215 216 psc = device_private(dv); 217 sc = &psc->ah_sc; 218 219 if ((rv = ahci_detach(sc, flags))) 220 return rv; 221 222 if (psc->sc_ih != NULL) 223 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 224 225 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 226 227 return 0; 228 } 229 230 static bool 231 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 232 { 233 struct ahci_pci_softc *psc = device_private(dv); 234 struct ahci_softc *sc = &psc->ah_sc; 235 int s; 236 237 s = splbio(); 238 ahci_resume(sc); 239 splx(s); 240 241 return true; 242 } 243
Indexes created Tue Sep 30 20:09:53 GMT 2025