ahcisata_pci.c revision 1.25
1 /* $NetBSD: ahcisata_pci.c,v 1.25 2011/05/27 15:11:59 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.25 2011/05/27 15:11:59 matt Exp $"); 30 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/disklabel.h> 37 #include <sys/pmf.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/ic/ahcisatavar.h> 44 45 struct ahci_pci_quirk { 46 pci_vendor_id_t vendor; /* Vendor ID */ 47 pci_product_id_t product; /* Product ID */ 48 int quirks; /* quirks; see below */ 49 }; 50 51 #define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 52 #define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */ 53 54 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 55 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 56 AHCI_PCI_QUIRK_FORCE }, 57 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 58 AHCI_PCI_QUIRK_FORCE }, 59 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 60 AHCI_PCI_QUIRK_FORCE }, 61 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 62 AHCI_PCI_QUIRK_FORCE }, 63 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 64 AHCI_PCI_QUIRK_FORCE }, 65 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 66 AHCI_PCI_QUIRK_FORCE }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 68 AHCI_PCI_QUIRK_FORCE }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 70 AHCI_PCI_QUIRK_FORCE }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 72 AHCI_PCI_QUIRK_FORCE }, 73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 74 AHCI_PCI_QUIRK_FORCE }, 75 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 76 AHCI_PCI_QUIRK_FORCE }, 77 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 78 AHCI_PCI_QUIRK_FORCE }, 79 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 80 AHCI_PCI_QUIRK_FORCE }, 81 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 82 AHCI_PCI_QUIRK_FORCE }, 83 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 84 AHCI_PCI_QUIRK_FORCE }, 85 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 86 AHCI_PCI_QUIRK_FORCE }, 87 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 88 AHCI_PCI_QUIRK_FORCE }, 89 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 90 AHCI_PCI_QUIRK_FORCE }, 91 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 92 AHCI_PCI_QUIRK_FORCE }, 93 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 94 AHCI_PCI_QUIRK_FORCE }, 95 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 96 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 97 AHCI_PCI_QUIRK_BAD64 }, 98 }; 99 100 struct ahci_pci_softc { 101 struct ahci_softc ah_sc; 102 pci_chipset_tag_t sc_pc; 103 pcitag_t sc_pcitag; 104 void * sc_ih; 105 }; 106 107 static bool ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t, int); 108 static int ahci_pci_match(device_t, cfdata_t, void *); 109 static void ahci_pci_attach(device_t, device_t, void *); 110 static int ahci_pci_detach(device_t, int); 111 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 112 113 114 CFATTACH_DECL_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 115 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL); 116 117 static bool 118 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product, int quirk) 119 { 120 int i; 121 122 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 123 if (vendor == ahci_pci_quirks[i].vendor && 124 product == ahci_pci_quirks[i].product) 125 return (ahci_pci_quirks[i].quirks & quirk) != 0; 126 return false; 127 } 128 129 static int 130 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 131 { 132 struct pci_attach_args *pa = aux; 133 bus_space_tag_t regt; 134 bus_space_handle_t regh; 135 bus_size_t size; 136 int ret = 0; 137 bool force; 138 139 force = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 140 PCI_PRODUCT(pa->pa_id), 141 AHCI_PCI_QUIRK_FORCE); 142 143 /* if wrong class and not forced by quirks, don't match */ 144 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 145 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 146 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 147 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 148 (force == false)) 149 return 0; 150 151 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 152 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 153 ®t, ®h, NULL, &size) != 0) 154 return 0; 155 156 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 157 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 158 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 159 (force == true)) 160 ret = 3; 161 162 bus_space_unmap(regt, regh, size); 163 return ret; 164 } 165 166 static void 167 ahci_pci_attach(device_t parent, device_t self, void *aux) 168 { 169 struct pci_attach_args *pa = aux; 170 struct ahci_pci_softc *psc = device_private(self); 171 struct ahci_softc *sc = &psc->ah_sc; 172 char devinfo[256]; 173 const char *intrstr; 174 bool ahci_cap_64bit; 175 bool ahci_bad_64bit; 176 pci_intr_handle_t intrhandle; 177 178 sc->sc_atac.atac_dev = self; 179 180 if (pci_mapreg_map(pa, AHCI_PCI_ABAR, 181 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 182 &sc->sc_ahcit, &sc->sc_ahcih, NULL, &sc->sc_ahcis) != 0) { 183 aprint_error_dev(self, "can't map ahci registers\n"); 184 return; 185 } 186 psc->sc_pc = pa->pa_pc; 187 psc->sc_pcitag = pa->pa_tag; 188 189 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 190 aprint_naive(": AHCI disk controller\n"); 191 aprint_normal(": %s\n", devinfo); 192 193 if (pci_intr_map(pa, &intrhandle) != 0) { 194 aprint_error_dev(self, "couldn't map interrupt\n"); 195 return; 196 } 197 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 198 psc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc); 199 if (psc->sc_ih == NULL) { 200 aprint_error_dev(self, "couldn't establish interrupt\n"); 201 return; 202 } 203 aprint_normal_dev(self, "interrupting at %s\n", 204 intrstr ? intrstr : "unknown interrupt"); 205 206 sc->sc_dmat = pa->pa_dmat; 207 208 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 209 ahci_bad_64bit = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 210 PCI_PRODUCT(pa->pa_id), 211 AHCI_PCI_QUIRK_BAD64); 212 213 if (pci_dma64_available(pa) && ahci_cap_64bit) { 214 if (!ahci_bad_64bit) 215 sc->sc_dmat = pa->pa_dmat64; 216 aprint_verbose_dev(self, "64-bit DMA%s\n", 217 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 218 } 219 220 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 221 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 222 sc->sc_atac_capflags = ATAC_CAP_RAID; 223 } else { 224 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 225 } 226 227 ahci_attach(sc); 228 229 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 230 aprint_error_dev(self, "couldn't establish power handler\n"); 231 } 232 233 static int 234 ahci_pci_detach(device_t dv, int flags) 235 { 236 struct ahci_pci_softc *psc; 237 struct ahci_softc *sc; 238 int rv; 239 240 psc = device_private(dv); 241 sc = &psc->ah_sc; 242 243 if ((rv = ahci_detach(sc, flags))) 244 return rv; 245 246 pmf_device_deregister(dv); 247 248 if (psc->sc_ih != NULL) 249 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 250 251 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 252 253 return 0; 254 } 255 256 static bool 257 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 258 { 259 struct ahci_pci_softc *psc = device_private(dv); 260 struct ahci_softc *sc = &psc->ah_sc; 261 int s; 262 263 s = splbio(); 264 ahci_resume(sc); 265 splx(s); 266 267 return true; 268 } 269
Indexes created Tue Sep 30 20:09:53 GMT 2025