ahcisata_pci.c revision 1.38.14.1
1 /* $NetBSD: ahcisata_pci.c,v 1.38.14.1 2018/11/26 01:52:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.38.14.1 2018/11/26 01:52:32 pgoyette Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/disklabel.h> 41 #include <sys/pmf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 struct ahci_pci_quirk { 50 pci_vendor_id_t vendor; /* Vendor ID */ 51 pci_product_id_t product; /* Product ID */ 52 int quirks; /* quirks; same as sc_ahci_quirks */ 53 }; 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 65 AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 77 AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 101 AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 145 AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 147 AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 169 AHCI_PCI_QUIRK_FORCE }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 173 AHCI_QUIRK_BADPMP }, 174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 175 AHCI_PCI_QUIRK_FORCE }, 176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMPRESET }, 179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 180 AHCI_QUIRK_BADPMPRESET }, 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 182 AHCI_QUIRK_BADPMPRESET }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 184 AHCI_QUIRK_BADPMPRESET }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 186 AHCI_QUIRK_BADPMPRESET }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 188 AHCI_QUIRK_BADPMPRESET }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA, 190 AHCI_QUIRK_BADPMP }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 192 AHCI_QUIRK_BADPMP }, 193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 194 AHCI_PCI_QUIRK_FORCE }, 195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 196 AHCI_PCI_QUIRK_FORCE }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 200 AHCI_PCI_QUIRK_FORCE }, 201 }; 202 203 struct ahci_pci_softc { 204 struct ahci_softc ah_sc; 205 pci_chipset_tag_t sc_pc; 206 pcitag_t sc_pcitag; 207 pci_intr_handle_t *sc_pihp; 208 void *sc_ih; 209 }; 210 211 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 212 static int ahci_pci_match(device_t, cfdata_t, void *); 213 static void ahci_pci_attach(device_t, device_t, void *); 214 static int ahci_pci_detach(device_t, int); 215 static void ahci_pci_childdetached(device_t, device_t); 216 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 217 218 219 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 220 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 221 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 222 223 #define AHCI_PCI_ABAR_CAVIUM 0x10 224 225 static int 226 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 227 { 228 int i; 229 230 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 231 if (vendor == ahci_pci_quirks[i].vendor && 232 product == ahci_pci_quirks[i].product) 233 return ahci_pci_quirks[i].quirks; 234 return 0; 235 } 236 237 static int 238 ahci_pci_abar(struct pci_attach_args *pa) 239 { 240 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 241 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 242 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 243 return AHCI_PCI_ABAR_CAVIUM; 244 } 245 } 246 247 return AHCI_PCI_ABAR; 248 } 249 250 251 static int 252 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 253 { 254 struct pci_attach_args *pa = aux; 255 bus_space_tag_t regt; 256 bus_space_handle_t regh; 257 bus_size_t size; 258 int ret = 0; 259 bool force; 260 261 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 262 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 263 264 /* if wrong class and not forced by quirks, don't match */ 265 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 266 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 267 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 268 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 269 (force == false)) 270 return 0; 271 272 int bar = ahci_pci_abar(pa); 273 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 274 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 275 return 0; 276 277 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 278 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 279 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 280 (force == true)) 281 ret = 3; 282 283 bus_space_unmap(regt, regh, size); 284 return ret; 285 } 286 287 static void 288 ahci_pci_attach(device_t parent, device_t self, void *aux) 289 { 290 struct pci_attach_args *pa = aux; 291 struct ahci_pci_softc *psc = device_private(self); 292 struct ahci_softc *sc = &psc->ah_sc; 293 const char *intrstr; 294 bool ahci_cap_64bit; 295 bool ahci_bad_64bit; 296 char intrbuf[PCI_INTRSTR_LEN]; 297 298 sc->sc_atac.atac_dev = self; 299 300 int bar = ahci_pci_abar(pa); 301 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 302 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 303 NULL, &sc->sc_ahcis) != 0) { 304 aprint_error_dev(self, "can't map ahci registers\n"); 305 return; 306 } 307 psc->sc_pc = pa->pa_pc; 308 psc->sc_pcitag = pa->pa_tag; 309 310 pci_aprint_devinfo(pa, "AHCI disk controller"); 311 312 313 /* Allocation settings */ 314 int counts[PCI_INTR_TYPE_SIZE] = { 315 [PCI_INTR_TYPE_INTX] = 1, 316 #ifndef AHCISATA_DISABLE_MSI 317 [PCI_INTR_TYPE_MSI] = 1, 318 #endif 319 #ifndef AHCISATA_DISABLE_MSIX 320 [PCI_INTR_TYPE_MSIX] = 1, 321 #endif 322 }; 323 324 alloc_retry: 325 /* Allocate and establish the interrupt. */ 326 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) { 327 aprint_error_dev(self, "can't allocate handler\n"); 328 goto fail; 329 } 330 331 intrstr = pci_intr_string(pa->pa_pc, psc->sc_pihp[0], intrbuf, 332 sizeof(intrbuf)); 333 psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, psc->sc_pihp[0], 334 IPL_BIO, ahci_intr, sc, device_xname(sc->sc_atac.atac_dev)); 335 if (psc->sc_ih == NULL) { 336 const pci_intr_type_t intr_type = pci_intr_type(pa->pa_pc, 337 psc->sc_pihp[0]); 338 pci_intr_release(pa->pa_pc, psc->sc_pihp, 1); 339 psc->sc_ih = NULL; 340 switch (intr_type) { 341 #ifndef AHCISATA_DISABLE_MSIX 342 case PCI_INTR_TYPE_MSIX: 343 /* The next try is for MSI: Disable MSIX */ 344 counts[PCI_INTR_TYPE_INTX] = 1; 345 #ifndef AHCISATA_DISABLE_MSI 346 counts[PCI_INTR_TYPE_MSI] = 1; 347 #endif 348 counts[PCI_INTR_TYPE_MSIX] = 0; 349 goto alloc_retry; 350 #endif 351 #ifndef AHCISATA_DISABLE_MSI 352 case PCI_INTR_TYPE_MSI: 353 /* The next try is for INTx: Disable MSI */ 354 counts[PCI_INTR_TYPE_MSI] = 0; 355 counts[PCI_INTR_TYPE_INTX] = 1; 356 goto alloc_retry; 357 #endif 358 case PCI_INTR_TYPE_INTX: 359 default: 360 counts[PCI_INTR_TYPE_INTX] = 1; 361 aprint_error_dev(self, "couldn't establish interrupt"); 362 if (intrstr != NULL) 363 aprint_error(" at %s", intrstr); 364 aprint_error("\n"); 365 goto fail; 366 } 367 } 368 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 369 370 sc->sc_dmat = pa->pa_dmat; 371 372 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 373 PCI_PRODUCT(pa->pa_id)); 374 375 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 376 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 377 378 if (pci_dma64_available(pa) && ahci_cap_64bit) { 379 if (!ahci_bad_64bit) 380 sc->sc_dmat = pa->pa_dmat64; 381 aprint_verbose_dev(self, "64-bit DMA%s\n", 382 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 383 } 384 385 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 386 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 387 sc->sc_atac_capflags = ATAC_CAP_RAID; 388 } else { 389 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 390 } 391 392 ahci_attach(sc); 393 394 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 395 aprint_error_dev(self, "couldn't establish power handler\n"); 396 397 return; 398 fail: 399 if (psc->sc_pihp != NULL) { 400 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 401 psc->sc_pihp = NULL; 402 } 403 if (sc->sc_ahcis) { 404 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 405 sc->sc_ahcis = 0; 406 } 407 408 return; 409 410 } 411 412 static void 413 ahci_pci_childdetached(device_t dv, device_t child) 414 { 415 struct ahci_pci_softc *psc = device_private(dv); 416 struct ahci_softc *sc = &psc->ah_sc; 417 418 ahci_childdetached(sc, child); 419 } 420 421 static int 422 ahci_pci_detach(device_t dv, int flags) 423 { 424 struct ahci_pci_softc *psc; 425 struct ahci_softc *sc; 426 int rv; 427 428 psc = device_private(dv); 429 sc = &psc->ah_sc; 430 431 if ((rv = ahci_detach(sc, flags))) 432 return rv; 433 434 pmf_device_deregister(dv); 435 436 if (psc->sc_ih != NULL) { 437 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 438 psc->sc_ih = NULL; 439 } 440 441 if (psc->sc_pihp != NULL) { 442 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 443 psc->sc_pihp = NULL; 444 } 445 446 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 447 448 return 0; 449 } 450 451 static bool 452 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 453 { 454 struct ahci_pci_softc *psc = device_private(dv); 455 struct ahci_softc *sc = &psc->ah_sc; 456 int s; 457 458 s = splbio(); 459 ahci_resume(sc); 460 splx(s); 461 462 return true; 463 } 464
Indexes created Thu Oct 02 14:10:14 GMT 2025