ahcisata_pci.c revision 1.48
1 /* $NetBSD: ahcisata_pci.c,v 1.48 2018/11/30 17:47:54 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.48 2018/11/30 17:47:54 jdolecek Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/disklabel.h> 41 #include <sys/pmf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 struct ahci_pci_quirk { 50 pci_vendor_id_t vendor; /* Vendor ID */ 51 pci_product_id_t product; /* Product ID */ 52 int quirks; /* quirks; same as sc_ahci_quirks */ 53 }; 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 65 AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 77 AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 101 AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 145 AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 147 AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 169 AHCI_PCI_QUIRK_FORCE }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 173 AHCI_QUIRK_BADPMP }, 174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 175 AHCI_PCI_QUIRK_FORCE }, 176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMPRESET }, 179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 180 AHCI_QUIRK_BADPMPRESET }, 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 182 AHCI_QUIRK_BADPMPRESET }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 184 AHCI_QUIRK_BADPMPRESET }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 186 AHCI_QUIRK_BADPMPRESET }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 188 AHCI_QUIRK_BADPMPRESET }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA, 190 AHCI_QUIRK_BADPMP }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 192 AHCI_QUIRK_BADPMP }, 193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 194 AHCI_PCI_QUIRK_FORCE }, 195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 196 AHCI_PCI_QUIRK_FORCE }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 200 AHCI_PCI_QUIRK_FORCE }, 201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA, 202 AHCI_PCI_QUIRK_FORCE }, 203 }; 204 205 struct ahci_pci_softc { 206 struct ahci_softc ah_sc; 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pcitag; 209 pci_intr_handle_t *sc_pihp; 210 void *sc_ih; 211 }; 212 213 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 214 static int ahci_pci_match(device_t, cfdata_t, void *); 215 static void ahci_pci_attach(device_t, device_t, void *); 216 static int ahci_pci_detach(device_t, int); 217 static void ahci_pci_childdetached(device_t, device_t); 218 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 219 220 221 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 222 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 223 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 224 225 #define AHCI_PCI_ABAR_CAVIUM 0x10 226 227 static int 228 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 229 { 230 int i; 231 232 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 233 if (vendor == ahci_pci_quirks[i].vendor && 234 product == ahci_pci_quirks[i].product) 235 return ahci_pci_quirks[i].quirks; 236 return 0; 237 } 238 239 static int 240 ahci_pci_abar(struct pci_attach_args *pa) 241 { 242 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 243 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 244 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 245 return AHCI_PCI_ABAR_CAVIUM; 246 } 247 } 248 249 return AHCI_PCI_ABAR; 250 } 251 252 253 static int 254 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 255 { 256 struct pci_attach_args *pa = aux; 257 bus_space_tag_t regt; 258 bus_space_handle_t regh; 259 bus_size_t size; 260 int ret = 0; 261 bool force; 262 263 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 264 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 265 266 /* if wrong class and not forced by quirks, don't match */ 267 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 268 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 269 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 270 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 271 (force == false)) 272 return 0; 273 274 int bar = ahci_pci_abar(pa); 275 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 276 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 277 return 0; 278 279 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 280 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 281 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 282 (force == true)) 283 ret = 3; 284 285 bus_space_unmap(regt, regh, size); 286 return ret; 287 } 288 289 static void 290 ahci_pci_attach(device_t parent, device_t self, void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 struct ahci_pci_softc *psc = device_private(self); 294 struct ahci_softc *sc = &psc->ah_sc; 295 const char *intrstr; 296 bool ahci_cap_64bit; 297 bool ahci_bad_64bit; 298 char intrbuf[PCI_INTRSTR_LEN]; 299 300 sc->sc_atac.atac_dev = self; 301 302 int bar = ahci_pci_abar(pa); 303 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 304 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 305 NULL, &sc->sc_ahcis) != 0) { 306 aprint_error_dev(self, "can't map ahci registers\n"); 307 return; 308 } 309 psc->sc_pc = pa->pa_pc; 310 psc->sc_pcitag = pa->pa_tag; 311 312 pci_aprint_devinfo(pa, "AHCI disk controller"); 313 314 /* Allocate and establish the interrupt. */ 315 if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0)) { 316 aprint_error_dev(self, "can't allocate handler\n"); 317 goto fail; 318 } 319 320 intrstr = pci_intr_string(pa->pa_pc, psc->sc_pihp[0], intrbuf, 321 sizeof(intrbuf)); 322 psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, psc->sc_pihp[0], 323 IPL_BIO, ahci_intr, sc, device_xname(sc->sc_atac.atac_dev)); 324 if (psc->sc_ih == NULL) { 325 pci_intr_release(pa->pa_pc, psc->sc_pihp, 1); 326 psc->sc_ih = NULL; 327 aprint_error_dev(self, "couldn't establish interrupt"); 328 if (intrstr != NULL) 329 aprint_error(" at %s", intrstr); 330 aprint_error("\n"); 331 goto fail; 332 } 333 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 334 335 sc->sc_dmat = pa->pa_dmat; 336 337 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 338 PCI_PRODUCT(pa->pa_id)); 339 340 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 341 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 342 343 if (pci_dma64_available(pa) && ahci_cap_64bit) { 344 if (!ahci_bad_64bit) 345 sc->sc_dmat = pa->pa_dmat64; 346 aprint_verbose_dev(self, "64-bit DMA%s\n", 347 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 348 } 349 350 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 351 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 352 sc->sc_atac_capflags = ATAC_CAP_RAID; 353 } else { 354 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 355 } 356 357 ahci_attach(sc); 358 359 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 360 aprint_error_dev(self, "couldn't establish power handler\n"); 361 362 return; 363 fail: 364 if (psc->sc_pihp != NULL) { 365 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 366 psc->sc_pihp = NULL; 367 } 368 if (sc->sc_ahcis) { 369 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 370 sc->sc_ahcis = 0; 371 } 372 373 return; 374 375 } 376 377 static void 378 ahci_pci_childdetached(device_t dv, device_t child) 379 { 380 struct ahci_pci_softc *psc = device_private(dv); 381 struct ahci_softc *sc = &psc->ah_sc; 382 383 ahci_childdetached(sc, child); 384 } 385 386 static int 387 ahci_pci_detach(device_t dv, int flags) 388 { 389 struct ahci_pci_softc *psc; 390 struct ahci_softc *sc; 391 int rv; 392 393 psc = device_private(dv); 394 sc = &psc->ah_sc; 395 396 if ((rv = ahci_detach(sc, flags))) 397 return rv; 398 399 pmf_device_deregister(dv); 400 401 if (psc->sc_ih != NULL) { 402 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 403 psc->sc_ih = NULL; 404 } 405 406 if (psc->sc_pihp != NULL) { 407 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 408 psc->sc_pihp = NULL; 409 } 410 411 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 412 413 return 0; 414 } 415 416 static bool 417 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 418 { 419 struct ahci_pci_softc *psc = device_private(dv); 420 struct ahci_softc *sc = &psc->ah_sc; 421 int s; 422 423 s = splbio(); 424 ahci_resume(sc); 425 splx(s); 426 427 return true; 428 } 429
Indexes created Tue Sep 30 20:09:53 GMT 2025