ahcisata_pci.c revision 1.51
1 /* $NetBSD: ahcisata_pci.c,v 1.51 2019/01/14 21:29:56 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.51 2019/01/14 21:29:56 jdolecek Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/disklabel.h> 41 #include <sys/pmf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 struct ahci_pci_quirk { 50 pci_vendor_id_t vendor; /* Vendor ID */ 51 pci_product_id_t product; /* Product ID */ 52 int quirks; /* quirks; same as sc_ahci_quirks */ 53 }; 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 65 AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 77 AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 101 AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 145 AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 147 AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 169 AHCI_PCI_QUIRK_FORCE }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 173 AHCI_QUIRK_BADPMP }, 174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 175 AHCI_PCI_QUIRK_FORCE }, 176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP }, 179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 180 AHCI_QUIRK_BADPMP }, 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 182 AHCI_QUIRK_BADPMP }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 184 AHCI_QUIRK_BADPMP }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 186 AHCI_QUIRK_BADPMP }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 188 AHCI_QUIRK_BADPMP }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA, 190 AHCI_QUIRK_BADPMP }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 192 AHCI_QUIRK_BADPMP }, 193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 194 AHCI_PCI_QUIRK_FORCE }, 195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 196 AHCI_PCI_QUIRK_FORCE }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 200 AHCI_PCI_QUIRK_FORCE }, 201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA, 202 AHCI_PCI_QUIRK_FORCE }, 203 }; 204 205 struct ahci_pci_softc { 206 struct ahci_softc ah_sc; 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pcitag; 209 pci_intr_handle_t *sc_pihp; 210 int sc_nintr; 211 void **sc_ih; 212 }; 213 214 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 215 static int ahci_pci_match(device_t, cfdata_t, void *); 216 static void ahci_pci_attach(device_t, device_t, void *); 217 static int ahci_pci_detach(device_t, int); 218 static void ahci_pci_childdetached(device_t, device_t); 219 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 220 221 222 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 223 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 224 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 225 226 #define AHCI_PCI_ABAR_CAVIUM 0x10 227 228 static int 229 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 230 { 231 int i; 232 233 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 234 if (vendor == ahci_pci_quirks[i].vendor && 235 product == ahci_pci_quirks[i].product) 236 return ahci_pci_quirks[i].quirks; 237 return 0; 238 } 239 240 static int 241 ahci_pci_abar(struct pci_attach_args *pa) 242 { 243 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 244 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 245 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 246 return AHCI_PCI_ABAR_CAVIUM; 247 } 248 } 249 250 return AHCI_PCI_ABAR; 251 } 252 253 254 static int 255 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 bus_space_tag_t regt; 259 bus_space_handle_t regh; 260 bus_size_t size; 261 int ret = 0; 262 bool force; 263 264 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 265 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 266 267 /* if wrong class and not forced by quirks, don't match */ 268 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 269 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 270 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 271 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 272 (force == false)) 273 return 0; 274 275 int bar = ahci_pci_abar(pa); 276 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 277 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 278 return 0; 279 280 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 281 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 282 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 283 (force == true)) 284 ret = 3; 285 286 bus_space_unmap(regt, regh, size); 287 return ret; 288 } 289 290 static int 291 ahci_pci_intr_establish(struct ahci_softc *sc, int port) 292 { 293 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc; 294 device_t self = sc->sc_atac.atac_dev; 295 char intrbuf[PCI_INTRSTR_LEN]; 296 char intr_xname[INTRDEVNAMEBUF]; 297 const char *intrstr; 298 int vec; 299 int (*intr_handler)(void *); 300 void *intr_arg; 301 302 KASSERT(psc->sc_pihp != NULL); 303 KASSERT(psc->sc_nintr > 0); 304 305 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self)); 306 307 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) { 308 /* Only one interrupt, established on vector 0 */ 309 intr_handler = ahci_intr; 310 intr_arg = sc; 311 vec = 0; 312 313 if (psc->sc_ih[vec] != NULL) { 314 /* Already established, nothing more to do */ 315 goto out; 316 } 317 318 } else { 319 /* 320 * Theoretically AHCI device can have less MSI/MSI-X vectors 321 * than supported ports. Hardware is allowed to revert 322 * to single message MSI, but not required to do so. 323 * So handle the case when it did not revert to single MSI. 324 * In this case last available interrupt vector is used 325 * for port == max vector, and all further ports. 326 * This last vector must use the general interrupt handler, 327 * since it needs to be able to handle several ports. 328 * NOTE: such case was never actually observed yet 329 */ 330 if (sc->sc_atac.atac_nchannels > psc->sc_nintr 331 && port >= (psc->sc_nintr - 1)) { 332 intr_handler = ahci_intr; 333 intr_arg = sc; 334 vec = psc->sc_nintr - 1; 335 336 if (psc->sc_ih[vec] != NULL) { 337 /* Already established, nothing more to do */ 338 goto out; 339 } 340 341 if (port == vec) { 342 /* Print error once */ 343 aprint_error_dev(self, 344 "port %d independant interrupt vector not " 345 "available, sharing with further ports", 346 port); 347 } 348 } else { 349 /* Vector according to port */ 350 KASSERT(port < psc->sc_nintr); 351 KASSERT(psc->sc_ih[port] == NULL); 352 intr_handler = ahci_intr_port; 353 intr_arg = &sc->sc_channels[port]; 354 vec = port; 355 356 snprintf(intr_xname, sizeof(intr_xname), "%s port%d", 357 device_xname(self), port); 358 } 359 } 360 361 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf, 362 sizeof(intrbuf)); 363 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc, 364 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname); 365 if (psc->sc_ih == NULL) { 366 aprint_error_dev(self, "couldn't establish interrupt"); 367 if (intrstr != NULL) 368 aprint_error(" at %s", intrstr); 369 aprint_error("\n"); 370 goto fail; 371 } 372 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 373 374 out: 375 return 0; 376 377 fail: 378 return EAGAIN; 379 } 380 381 static void 382 ahci_pci_attach(device_t parent, device_t self, void *aux) 383 { 384 struct pci_attach_args *pa = aux; 385 struct ahci_pci_softc *psc = device_private(self); 386 struct ahci_softc *sc = &psc->ah_sc; 387 bool ahci_cap_64bit; 388 bool ahci_bad_64bit; 389 390 sc->sc_atac.atac_dev = self; 391 392 int bar = ahci_pci_abar(pa); 393 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 394 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 395 NULL, &sc->sc_ahcis) != 0) { 396 aprint_error_dev(self, "can't map ahci registers\n"); 397 return; 398 } 399 psc->sc_pc = pa->pa_pc; 400 psc->sc_pcitag = pa->pa_tag; 401 402 pci_aprint_devinfo(pa, "AHCI disk controller"); 403 404 int counts[PCI_INTR_TYPE_SIZE] = { 405 [PCI_INTR_TYPE_INTX] = 1, 406 [PCI_INTR_TYPE_MSI] = 1, 407 [PCI_INTR_TYPE_MSIX] = -1, 408 }; 409 410 /* Allocate and establish the interrupt. */ 411 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) { 412 aprint_error_dev(self, "can't allocate handler\n"); 413 goto fail; 414 } 415 416 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])]; 417 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP); 418 sc->sc_intr_establish = ahci_pci_intr_establish; 419 420 sc->sc_dmat = pa->pa_dmat; 421 422 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 423 PCI_PRODUCT(pa->pa_id)); 424 425 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 426 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 427 428 if (pci_dma64_available(pa) && ahci_cap_64bit) { 429 if (!ahci_bad_64bit) 430 sc->sc_dmat = pa->pa_dmat64; 431 aprint_verbose_dev(self, "64-bit DMA%s\n", 432 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 433 } 434 435 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 436 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 437 sc->sc_atac_capflags = ATAC_CAP_RAID; 438 } else { 439 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 440 } 441 442 ahci_attach(sc); 443 444 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 445 aprint_error_dev(self, "couldn't establish power handler\n"); 446 447 return; 448 fail: 449 if (psc->sc_pihp != NULL) { 450 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 451 psc->sc_pihp = NULL; 452 } 453 if (sc->sc_ahcis) { 454 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 455 sc->sc_ahcis = 0; 456 } 457 458 return; 459 460 } 461 462 static void 463 ahci_pci_childdetached(device_t dv, device_t child) 464 { 465 struct ahci_pci_softc *psc = device_private(dv); 466 struct ahci_softc *sc = &psc->ah_sc; 467 468 ahci_childdetached(sc, child); 469 } 470 471 static int 472 ahci_pci_detach(device_t dv, int flags) 473 { 474 struct ahci_pci_softc *psc; 475 struct ahci_softc *sc; 476 int rv; 477 478 psc = device_private(dv); 479 sc = &psc->ah_sc; 480 481 if ((rv = ahci_detach(sc, flags))) 482 return rv; 483 484 pmf_device_deregister(dv); 485 486 if (psc->sc_ih != NULL) { 487 for (int intr = 0; intr < psc->sc_nintr; intr++) { 488 if (psc->sc_ih[intr] != NULL) { 489 pci_intr_disestablish(psc->sc_pc, 490 psc->sc_ih[intr]); 491 psc->sc_ih[intr] = NULL; 492 } 493 } 494 495 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr); 496 psc->sc_ih = NULL; 497 } 498 499 if (psc->sc_pihp != NULL) { 500 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 501 psc->sc_pihp = NULL; 502 } 503 504 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 505 506 return 0; 507 } 508 509 static bool 510 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 511 { 512 struct ahci_pci_softc *psc = device_private(dv); 513 struct ahci_softc *sc = &psc->ah_sc; 514 int s; 515 516 s = splbio(); 517 ahci_resume(sc); 518 splx(s); 519 520 return true; 521 } 522
Indexes created Tue Sep 30 20:09:53 GMT 2025