ahcisata_pci.c revision 1.55.4.4
1 /* $NetBSD: ahcisata_pci.c,v 1.55.4.4 2025/05/09 11:13:53 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.55.4.4 2025/05/09 11:13:53 martin Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #ifdef _KERNEL_OPT 36 #include "opt_ahcisata_pci.h" 37 #endif 38 39 #include <sys/types.h> 40 #include <sys/kmem.h> 41 #include <sys/param.h> 42 #include <sys/kernel.h> 43 #include <sys/systm.h> 44 #include <sys/disklabel.h> 45 #include <sys/pmf.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pciidereg.h> 50 #include <dev/pci/pciidevar.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 struct ahci_pci_quirk { 54 pci_vendor_id_t vendor; /* Vendor ID */ 55 pci_product_id_t product; /* Product ID */ 56 int quirks; /* quirks; same as sc_ahci_quirks */ 57 }; 58 59 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 65 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 67 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 73 AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 77 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 97 AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 101 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 121 AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 123 AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 145 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 147 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 169 AHCI_QUIRK_BADPMP }, 170 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 171 AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 173 AHCI_PCI_QUIRK_FORCE }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 175 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 177 AHCI_QUIRK_BADPMP }, 178 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 179 AHCI_PCI_QUIRK_FORCE }, 180 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 182 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 184 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 186 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 188 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 189 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 190 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 191 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 192 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 193 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 194 AHCI_QUIRK_BADPMP }, 195 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_AHCI, 196 AHCI_QUIRK_BADPMP }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 200 AHCI_PCI_QUIRK_FORCE }, 201 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 202 AHCI_PCI_QUIRK_FORCE }, 203 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 204 AHCI_PCI_QUIRK_FORCE }, 205 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1062_JMB575, 206 AHCI_PCI_QUIRK_FORCE }, 207 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA, 208 AHCI_PCI_QUIRK_FORCE }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI, 210 AHCI_QUIRK_BADPMP }, 211 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI, 212 AHCI_QUIRK_BADPMP }, 213 }; 214 215 struct ahci_pci_softc { 216 struct ahci_softc ah_sc; 217 pci_chipset_tag_t sc_pc; 218 pcitag_t sc_pcitag; 219 pci_intr_handle_t *sc_pihp; 220 int sc_nintr; 221 void **sc_ih; 222 }; 223 224 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 225 static int ahci_pci_match(device_t, cfdata_t, void *); 226 static void ahci_pci_attach(device_t, device_t, void *); 227 static int ahci_pci_detach(device_t, int); 228 static void ahci_pci_childdetached(device_t, device_t); 229 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 230 231 232 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 233 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 234 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 235 236 #define AHCI_PCI_ABAR_CAVIUM 0x10 237 238 static int 239 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 240 { 241 int i; 242 243 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 244 if (vendor == ahci_pci_quirks[i].vendor && 245 product == ahci_pci_quirks[i].product) 246 return ahci_pci_quirks[i].quirks; 247 return 0; 248 } 249 250 static int 251 ahci_pci_abar(struct pci_attach_args *pa) 252 { 253 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 254 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 255 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 256 return AHCI_PCI_ABAR_CAVIUM; 257 } 258 } 259 260 return AHCI_PCI_ABAR; 261 } 262 263 264 static int 265 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 266 { 267 struct pci_attach_args *pa = aux; 268 bus_space_tag_t regt; 269 bus_space_handle_t regh; 270 bus_size_t size; 271 int ret = 0; 272 bool force; 273 274 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 275 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 276 277 /* if wrong class and not forced by quirks, don't match */ 278 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 279 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 280 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 281 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 282 (force == false)) 283 return 0; 284 285 int bar = ahci_pci_abar(pa); 286 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 287 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 288 return 0; 289 290 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 291 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 292 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 293 (force == true)) 294 ret = 3; 295 296 bus_space_unmap(regt, regh, size); 297 return ret; 298 } 299 300 static int 301 ahci_pci_intr_establish(struct ahci_softc *sc, int port) 302 { 303 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc; 304 device_t self = sc->sc_atac.atac_dev; 305 char intrbuf[PCI_INTRSTR_LEN]; 306 char intr_xname[INTRDEVNAMEBUF]; 307 const char *intrstr; 308 int vec; 309 int (*intr_handler)(void *); 310 void *intr_arg; 311 312 KASSERT(psc->sc_pihp != NULL); 313 KASSERT(psc->sc_nintr > 0); 314 315 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self)); 316 317 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) { 318 /* Only one interrupt, established on vector 0 */ 319 intr_handler = ahci_intr; 320 intr_arg = sc; 321 vec = 0; 322 323 if (psc->sc_ih[vec] != NULL) { 324 /* Already established, nothing more to do */ 325 goto out; 326 } 327 328 } else { 329 /* 330 * Theoretically AHCI device can have less MSI/MSI-X vectors 331 * than supported ports. Hardware is allowed to revert 332 * to single message MSI, but not required to do so. 333 * So handle the case when it did not revert to single MSI. 334 * In this case last available interrupt vector is used 335 * for port == max vector, and all further ports. 336 * This last vector must use the general interrupt handler, 337 * since it needs to be able to handle several ports. 338 * NOTE: such case was never actually observed yet 339 */ 340 if (sc->sc_atac.atac_nchannels > psc->sc_nintr 341 && port >= (psc->sc_nintr - 1)) { 342 intr_handler = ahci_intr; 343 intr_arg = sc; 344 vec = psc->sc_nintr - 1; 345 346 if (psc->sc_ih[vec] != NULL) { 347 /* Already established, nothing more to do */ 348 goto out; 349 } 350 351 if (port == vec) { 352 /* Print error once */ 353 aprint_error_dev(self, 354 "port %d independant interrupt vector not " 355 "available, sharing with further ports", 356 port); 357 } 358 } else { 359 /* Vector according to port */ 360 KASSERT(port < psc->sc_nintr); 361 KASSERT(psc->sc_ih[port] == NULL); 362 intr_handler = ahci_intr_port; 363 intr_arg = &sc->sc_channels[port]; 364 vec = port; 365 366 snprintf(intr_xname, sizeof(intr_xname), "%s port%d", 367 device_xname(self), port); 368 } 369 } 370 371 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf, 372 sizeof(intrbuf)); 373 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc, 374 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname); 375 if (psc->sc_ih == NULL) { 376 aprint_error_dev(self, "couldn't establish interrupt"); 377 if (intrstr != NULL) 378 aprint_error(" at %s", intrstr); 379 aprint_error("\n"); 380 goto fail; 381 } 382 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 383 384 out: 385 return 0; 386 387 fail: 388 return EAGAIN; 389 } 390 391 static void 392 ahci_pci_attach(device_t parent, device_t self, void *aux) 393 { 394 struct pci_attach_args *pa = aux; 395 struct ahci_pci_softc *psc = device_private(self); 396 struct ahci_softc *sc = &psc->ah_sc; 397 bool ahci_cap_64bit; 398 bool ahci_bad_64bit; 399 pcireg_t reg; 400 401 sc->sc_atac.atac_dev = self; 402 403 int bar = ahci_pci_abar(pa); 404 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 405 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 406 NULL, &sc->sc_ahcis) != 0) { 407 aprint_error_dev(self, "can't map ahci registers\n"); 408 return; 409 } 410 psc->sc_pc = pa->pa_pc; 411 psc->sc_pcitag = pa->pa_tag; 412 413 pci_aprint_devinfo(pa, "AHCI disk controller"); 414 415 int counts[PCI_INTR_TYPE_SIZE] = { 416 [PCI_INTR_TYPE_INTX] = 1, 417 [PCI_INTR_TYPE_MSI] = 1, 418 [PCI_INTR_TYPE_MSIX] = -1, 419 }; 420 421 /* Allocate and establish the interrupt. */ 422 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) { 423 aprint_error_dev(self, "can't allocate handler\n"); 424 goto fail; 425 } 426 427 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])]; 428 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP); 429 sc->sc_intr_establish = ahci_pci_intr_establish; 430 431 sc->sc_dmat = pa->pa_dmat; 432 433 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 434 PCI_PRODUCT(pa->pa_id)); 435 436 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 437 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 438 439 if (pci_dma64_available(pa) && ahci_cap_64bit) { 440 if (!ahci_bad_64bit) 441 sc->sc_dmat = pa->pa_dmat64; 442 aprint_verbose_dev(self, "64-bit DMA%s\n", 443 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 444 } 445 446 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 447 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 448 sc->sc_atac_capflags = ATAC_CAP_RAID; 449 } else { 450 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 451 } 452 453 reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG); 454 reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); 455 pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 456 457 ahci_attach(sc); 458 459 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 460 aprint_error_dev(self, "couldn't establish power handler\n"); 461 462 return; 463 fail: 464 if (psc->sc_pihp != NULL) { 465 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 466 psc->sc_pihp = NULL; 467 } 468 if (sc->sc_ahcis) { 469 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 470 sc->sc_ahcis = 0; 471 } 472 473 return; 474 475 } 476 477 static void 478 ahci_pci_childdetached(device_t dv, device_t child) 479 { 480 struct ahci_pci_softc *psc = device_private(dv); 481 struct ahci_softc *sc = &psc->ah_sc; 482 483 ahci_childdetached(sc, child); 484 } 485 486 static int 487 ahci_pci_detach(device_t dv, int flags) 488 { 489 struct ahci_pci_softc *psc; 490 struct ahci_softc *sc; 491 int rv; 492 493 psc = device_private(dv); 494 sc = &psc->ah_sc; 495 496 if ((rv = ahci_detach(sc, flags))) 497 return rv; 498 499 pmf_device_deregister(dv); 500 501 if (psc->sc_ih != NULL) { 502 for (int intr = 0; intr < psc->sc_nintr; intr++) { 503 if (psc->sc_ih[intr] != NULL) { 504 pci_intr_disestablish(psc->sc_pc, 505 psc->sc_ih[intr]); 506 psc->sc_ih[intr] = NULL; 507 } 508 } 509 510 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr); 511 psc->sc_ih = NULL; 512 } 513 514 if (psc->sc_pihp != NULL) { 515 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 516 psc->sc_pihp = NULL; 517 } 518 519 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 520 521 return 0; 522 } 523 524 static bool 525 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 526 { 527 struct ahci_pci_softc *psc = device_private(dv); 528 struct ahci_softc *sc = &psc->ah_sc; 529 int s; 530 531 s = splbio(); 532 ahci_resume(sc); 533 splx(s); 534 535 return true; 536 } 537
Indexes created Thu Oct 02 14:10:14 GMT 2025