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ahcisata_pci.c revision 1.62
      1 /*	$NetBSD: ahcisata_pci.c,v 1.62 2022/05/14 04:04:55 rin Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2006 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.62 2022/05/14 04:04:55 rin Exp $");
     30 
     31 #ifdef _KERNEL_OPT
     32 #include "opt_ahcisata_pci.h"
     33 #endif
     34 
     35 #include <sys/types.h>
     36 #include <sys/kmem.h>
     37 #include <sys/param.h>
     38 #include <sys/kernel.h>
     39 #include <sys/systm.h>
     40 #include <sys/disklabel.h>
     41 #include <sys/pmf.h>
     42 
     43 #include <dev/pci/pcivar.h>
     44 #include <dev/pci/pcidevs.h>
     45 #include <dev/pci/pciidereg.h>
     46 #include <dev/pci/pciidevar.h>
     47 #include <dev/ic/ahcisatavar.h>
     48 
     49 struct ahci_pci_quirk {
     50 	pci_vendor_id_t  vendor;	/* Vendor ID */
     51 	pci_product_id_t product;	/* Product ID */
     52 	int              quirks;	/* quirks; same as sc_ahci_quirks */
     53 };
     54 
     55 static const struct ahci_pci_quirk ahci_pci_quirks[] = {
     56 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
     57 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     58 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
     59 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     60 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
     61 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     62 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
     63 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     64 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
     65 	    AHCI_QUIRK_BADPMP },
     66 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
     67 	    AHCI_QUIRK_BADPMP },
     68 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
     69 	    AHCI_QUIRK_BADPMP },
     70 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
     71 	    AHCI_QUIRK_BADPMP },
     72 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
     73 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     74 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
     75 	    AHCI_QUIRK_BADPMP },
     76 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
     77 	    AHCI_QUIRK_BADPMP },
     78 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
     79 	     AHCI_QUIRK_BADPMP },
     80 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
     81 	     AHCI_QUIRK_BADPMP },
     82 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
     83 	     AHCI_QUIRK_BADPMP },
     84 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
     85 	     AHCI_QUIRK_BADPMP },
     86 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
     87 	     AHCI_QUIRK_BADPMP },
     88 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
     89 	     AHCI_QUIRK_BADPMP },
     90 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
     91 	     AHCI_QUIRK_BADPMP },
     92 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
     93 	     AHCI_QUIRK_BADPMP },
     94 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
     95 	     AHCI_QUIRK_BADPMP },
     96 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
     97 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     98 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
     99 	    AHCI_QUIRK_BADPMP },
    100 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
    101 	    AHCI_QUIRK_BADPMP },
    102 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
    103 	    AHCI_QUIRK_BADPMP },
    104 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
    105 	    AHCI_QUIRK_BADPMP },
    106 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
    107 	    AHCI_QUIRK_BADPMP },
    108 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
    109 	    AHCI_QUIRK_BADPMP },
    110 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
    111 	    AHCI_QUIRK_BADPMP },
    112 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
    113 	    AHCI_QUIRK_BADPMP },
    114 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
    115 	    AHCI_QUIRK_BADPMP },
    116 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
    117 	    AHCI_QUIRK_BADPMP },
    118 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
    119 	    AHCI_QUIRK_BADPMP },
    120 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
    121 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    122 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
    123 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    124 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
    125 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    126 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
    127 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    128 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
    129 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    130 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
    131 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    132 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
    133 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    134 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
    135 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    136 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
    137 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    138 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
    139 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    140 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
    141 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    142 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
    143 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    144 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
    145 	    AHCI_QUIRK_BADPMP },
    146 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
    147 	    AHCI_QUIRK_BADPMP },
    148 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
    149 	    AHCI_QUIRK_BADPMP },
    150 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
    151 	    AHCI_QUIRK_BADPMP },
    152 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
    153 	    AHCI_QUIRK_BADPMP },
    154 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
    155 	    AHCI_QUIRK_BADPMP },
    156 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
    157 	    AHCI_QUIRK_BADPMP },
    158 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
    159 	    AHCI_QUIRK_BADPMP },
    160 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
    161 	    AHCI_QUIRK_BADPMP },
    162 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
    163 	    AHCI_QUIRK_BADPMP },
    164 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
    165 	    AHCI_QUIRK_BADPMP },
    166 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
    167 	    AHCI_QUIRK_BADPMP },
    168 	{ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
    169 	    AHCI_PCI_QUIRK_FORCE },
    170 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
    171 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    172 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
    173 	    AHCI_QUIRK_BADPMP },
    174 	{ PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
    175 	    AHCI_PCI_QUIRK_FORCE },
    176 	/* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
    177 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
    178 	    AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    179 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
    180 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    181 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
    182 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    183 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
    184 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    185 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
    186 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    187 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
    188 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    189 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
    190 	    AHCI_QUIRK_BADPMP },
    191 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
    192 	    AHCI_QUIRK_BADPMP },
    193 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
    194 	    AHCI_PCI_QUIRK_FORCE },
    195 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
    196 	    AHCI_PCI_QUIRK_FORCE },
    197 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
    198 	    AHCI_PCI_QUIRK_FORCE },
    199 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
    200 	    AHCI_PCI_QUIRK_FORCE },
    201 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
    202 	    AHCI_PCI_QUIRK_FORCE },
    203 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
    204 	    AHCI_QUIRK_BADPMP },
    205 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
    206 	    AHCI_QUIRK_BADPMP },
    207 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI,
    208 	    AHCI_QUIRK_EXTRA_DELAY },
    209 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SATA_AHCI,
    210 	    AHCI_QUIRK_EXTRA_DELAY },
    211 #if 0
    212 	/*
    213 	 * XXX Non-reproducible failures reported. May need extra-delay quirk.
    214 	 */
    215 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0,
    216 	    AHCI_QUIRK_EXTRA_DELAY },
    217 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1,
    218 	    AHCI_QUIRK_EXTRA_DELAY },
    219 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4,
    220 	    AHCI_QUIRK_EXTRA_DELAY },
    221 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5,
    222 	    AHCI_QUIRK_EXTRA_DELAY },
    223 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6,
    224 	    AHCI_QUIRK_EXTRA_DELAY },
    225 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7,
    226 	    AHCI_QUIRK_EXTRA_DELAY },
    227 #endif
    228 };
    229 
    230 struct ahci_pci_softc {
    231 	struct ahci_softc ah_sc;
    232 	pci_chipset_tag_t sc_pc;
    233 	pcitag_t sc_pcitag;
    234 	pci_intr_handle_t *sc_pihp;
    235 	int sc_nintr;
    236 	void **sc_ih;
    237 };
    238 
    239 static int  ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
    240 static int  ahci_pci_match(device_t, cfdata_t, void *);
    241 static void ahci_pci_attach(device_t, device_t, void *);
    242 static int  ahci_pci_detach(device_t, int);
    243 static void ahci_pci_childdetached(device_t, device_t);
    244 static bool ahci_pci_resume(device_t, const pmf_qual_t *);
    245 
    246 
    247 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
    248     ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
    249     NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
    250 
    251 #define	AHCI_PCI_ABAR_CAVIUM	0x10
    252 
    253 static int
    254 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
    255 {
    256 	int i;
    257 
    258 	for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
    259 		if (vendor == ahci_pci_quirks[i].vendor &&
    260 		    product == ahci_pci_quirks[i].product)
    261 			return ahci_pci_quirks[i].quirks;
    262 	return 0;
    263 }
    264 
    265 static int
    266 ahci_pci_abar(struct pci_attach_args *pa)
    267 {
    268 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
    269 		if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
    270 		    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
    271 			return AHCI_PCI_ABAR_CAVIUM;
    272 		}
    273 	}
    274 
    275 	return AHCI_PCI_ABAR;
    276 }
    277 
    278 
    279 static int
    280 ahci_pci_match(device_t parent, cfdata_t match, void *aux)
    281 {
    282 	struct pci_attach_args *pa = aux;
    283 	bus_space_tag_t regt;
    284 	bus_space_handle_t regh;
    285 	bus_size_t size;
    286 	int ret = 0;
    287 	bool force;
    288 
    289 	force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
    290 	    PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
    291 
    292 	/* if wrong class and not forced by quirks, don't match */
    293 	if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
    294 	    ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
    295 	     PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
    296 	     PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
    297 	    (force == false))
    298 		return 0;
    299 
    300 	int bar = ahci_pci_abar(pa);
    301 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    302 	if (pci_mapreg_map(pa, bar, memtype, 0, &regt, &regh, NULL, &size) != 0)
    303 		return 0;
    304 
    305 	if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
    306 	     PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
    307 	    (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
    308 	    (force == true))
    309 		ret = 3;
    310 
    311 	bus_space_unmap(regt, regh, size);
    312 	return ret;
    313 }
    314 
    315 static int
    316 ahci_pci_intr_establish(struct ahci_softc *sc, int port)
    317 {
    318 	struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
    319 	device_t self = sc->sc_atac.atac_dev;
    320 	char intrbuf[PCI_INTRSTR_LEN];
    321 	char intr_xname[INTRDEVNAMEBUF];
    322 	const char *intrstr;
    323 	int vec;
    324 	int (*intr_handler)(void *);
    325 	void *intr_arg;
    326 
    327 	KASSERT(psc->sc_pihp != NULL);
    328 	KASSERT(psc->sc_nintr > 0);
    329 
    330 	snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
    331 
    332 	if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
    333 		/* Only one interrupt, established on vector 0 */
    334 		intr_handler = ahci_intr;
    335 		intr_arg = sc;
    336 		vec = 0;
    337 
    338 		if (psc->sc_ih[vec] != NULL) {
    339 			/* Already established, nothing more to do */
    340 			goto out;
    341 		}
    342 
    343 	} else {
    344 		/*
    345 		 * Theoretically AHCI device can have less MSI/MSI-X vectors
    346 		 * than supported ports. Hardware is allowed to revert
    347 		 * to single message MSI, but not required to do so.
    348 		 * So handle the case when it did not revert to single MSI.
    349 		 * In this case last available interrupt vector is used
    350 		 * for port == max vector, and all further ports.
    351 		 * This last vector must use the general interrupt handler,
    352 		 * since it needs to be able to handle several ports.
    353 		 * NOTE: such case was never actually observed yet
    354 		 */
    355 		if (sc->sc_atac.atac_nchannels > psc->sc_nintr
    356 		    && port >= (psc->sc_nintr - 1)) {
    357 			intr_handler = ahci_intr;
    358 			intr_arg = sc;
    359 			vec = psc->sc_nintr - 1;
    360 
    361 			if (psc->sc_ih[vec] != NULL) {
    362 				/* Already established, nothing more to do */
    363 				goto out;
    364 			}
    365 
    366 			if (port == vec) {
    367 				/* Print error once */
    368 				aprint_error_dev(self,
    369 				    "port %d independant interrupt vector not "
    370 				    "available, sharing with further ports",
    371 				    port);
    372 			}
    373 		} else {
    374 			/* Vector according to port */
    375 			KASSERT(port < psc->sc_nintr);
    376 			KASSERT(psc->sc_ih[port] == NULL);
    377 			intr_handler = ahci_intr_port;
    378 			intr_arg = &sc->sc_channels[port];
    379 			vec = port;
    380 
    381 			snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
    382 			    device_xname(self), port);
    383 		}
    384 	}
    385 
    386 	intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
    387 	    sizeof(intrbuf));
    388 	psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
    389 	    psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
    390 	if (psc->sc_ih[vec] == NULL) {
    391 		aprint_error_dev(self, "couldn't establish interrupt");
    392 		if (intrstr != NULL)
    393 			aprint_error(" at %s", intrstr);
    394 		aprint_error("\n");
    395 		goto fail;
    396 	}
    397 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    398 
    399 out:
    400 	return 0;
    401 
    402 fail:
    403 	return EAGAIN;
    404 }
    405 
    406 static void
    407 ahci_pci_attach(device_t parent, device_t self, void *aux)
    408 {
    409 	struct pci_attach_args *pa = aux;
    410 	struct ahci_pci_softc *psc = device_private(self);
    411 	struct ahci_softc *sc = &psc->ah_sc;
    412 	bool ahci_cap_64bit;
    413 	bool ahci_bad_64bit;
    414 	pcireg_t reg;
    415 
    416 	sc->sc_atac.atac_dev = self;
    417 
    418 	int bar = ahci_pci_abar(pa);
    419 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    420 	if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
    421 	    NULL, &sc->sc_ahcis) != 0) {
    422 		aprint_error_dev(self, "can't map ahci registers\n");
    423 		return;
    424 	}
    425 	psc->sc_pc = pa->pa_pc;
    426 	psc->sc_pcitag = pa->pa_tag;
    427 
    428 	pci_aprint_devinfo(pa, "AHCI disk controller");
    429 
    430 	int counts[PCI_INTR_TYPE_SIZE] = {
    431 		[PCI_INTR_TYPE_INTX] = 1,
    432 		[PCI_INTR_TYPE_MSI] = 1,
    433 		[PCI_INTR_TYPE_MSIX] = -1,
    434 	};
    435 
    436 	/* Allocate and establish the interrupt. */
    437 	if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
    438 		aprint_error_dev(self, "can't allocate handler\n");
    439 		goto fail;
    440 	}
    441 
    442 	psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
    443 	psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
    444 	sc->sc_intr_establish = ahci_pci_intr_establish;
    445 
    446 	sc->sc_dmat = pa->pa_dmat;
    447 
    448 	sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
    449 					    PCI_PRODUCT(pa->pa_id));
    450 
    451 	ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
    452 	ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
    453 
    454 	if (pci_dma64_available(pa) && ahci_cap_64bit) {
    455 		if (!ahci_bad_64bit)
    456 			sc->sc_dmat = pa->pa_dmat64;
    457 		aprint_verbose_dev(self, "64-bit DMA%s\n",
    458 		    (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
    459 	}
    460 
    461 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
    462 		AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
    463 		sc->sc_atac_capflags = ATAC_CAP_RAID;
    464 	} else {
    465 		AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
    466 	}
    467 
    468 	reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
    469 	reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
    470 	pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
    471 
    472 	ahci_attach(sc);
    473 
    474 	if (!pmf_device_register(self, NULL, ahci_pci_resume))
    475 		aprint_error_dev(self, "couldn't establish power handler\n");
    476 
    477 	return;
    478 fail:
    479 	if (psc->sc_pihp != NULL) {
    480 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    481 		psc->sc_pihp = NULL;
    482 	}
    483 	if (sc->sc_ahcis) {
    484 		bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    485 		sc->sc_ahcis = 0;
    486 	}
    487 
    488 	return;
    489 
    490 }
    491 
    492 static void
    493 ahci_pci_childdetached(device_t dv, device_t child)
    494 {
    495 	struct ahci_pci_softc *psc = device_private(dv);
    496 	struct ahci_softc *sc = &psc->ah_sc;
    497 
    498 	ahci_childdetached(sc, child);
    499 }
    500 
    501 static int
    502 ahci_pci_detach(device_t dv, int flags)
    503 {
    504 	struct ahci_pci_softc *psc;
    505 	struct ahci_softc *sc;
    506 	int rv;
    507 
    508 	psc = device_private(dv);
    509 	sc = &psc->ah_sc;
    510 
    511 	if ((rv = ahci_detach(sc, flags)))
    512 		return rv;
    513 
    514 	pmf_device_deregister(dv);
    515 
    516 	if (psc->sc_ih != NULL) {
    517 		for (int intr = 0; intr < psc->sc_nintr; intr++) {
    518 			if (psc->sc_ih[intr] != NULL) {
    519 				pci_intr_disestablish(psc->sc_pc,
    520 				    psc->sc_ih[intr]);
    521 				psc->sc_ih[intr] = NULL;
    522 			}
    523 		}
    524 
    525 		kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
    526 		psc->sc_ih = NULL;
    527 	}
    528 
    529 	if (psc->sc_pihp != NULL) {
    530 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    531 		psc->sc_pihp = NULL;
    532 	}
    533 
    534 	bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    535 
    536 	return 0;
    537 }
    538 
    539 static bool
    540 ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
    541 {
    542 	struct ahci_pci_softc *psc = device_private(dv);
    543 	struct ahci_softc *sc = &psc->ah_sc;
    544 	int s;
    545 
    546 	s = splbio();
    547 	ahci_resume(sc);
    548 	splx(s);
    549 
    550 	return true;
    551 }
    552