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ahcisata_pci.c revision 1.63
      1 /*	$NetBSD: ahcisata_pci.c,v 1.63 2022/05/29 11:18:33 rin Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2006 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.63 2022/05/29 11:18:33 rin Exp $");
     30 
     31 #ifdef _KERNEL_OPT
     32 #include "opt_ahcisata_pci.h"
     33 #endif
     34 
     35 #include <sys/types.h>
     36 #include <sys/kmem.h>
     37 #include <sys/param.h>
     38 #include <sys/kernel.h>
     39 #include <sys/systm.h>
     40 #include <sys/disklabel.h>
     41 #include <sys/pmf.h>
     42 
     43 #include <dev/pci/pcivar.h>
     44 #include <dev/pci/pcidevs.h>
     45 #include <dev/pci/pciidereg.h>
     46 #include <dev/pci/pciidevar.h>
     47 #include <dev/ic/ahcisatavar.h>
     48 
     49 struct ahci_pci_quirk {
     50 	pci_vendor_id_t  vendor;	/* Vendor ID */
     51 	pci_product_id_t product;	/* Product ID */
     52 	int              quirks;	/* quirks; same as sc_ahci_quirks */
     53 };
     54 
     55 static const struct ahci_pci_quirk ahci_pci_quirks[] = {
     56 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
     57 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     58 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
     59 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     60 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
     61 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     62 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
     63 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     64 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
     65 	    AHCI_QUIRK_BADPMP },
     66 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
     67 	    AHCI_QUIRK_BADPMP },
     68 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
     69 	    AHCI_QUIRK_BADPMP },
     70 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
     71 	    AHCI_QUIRK_BADPMP },
     72 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
     73 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     74 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
     75 	    AHCI_QUIRK_BADPMP },
     76 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
     77 	    AHCI_QUIRK_BADPMP },
     78 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
     79 	     AHCI_QUIRK_BADPMP },
     80 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
     81 	     AHCI_QUIRK_BADPMP },
     82 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
     83 	     AHCI_QUIRK_BADPMP },
     84 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
     85 	     AHCI_QUIRK_BADPMP },
     86 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
     87 	     AHCI_QUIRK_BADPMP },
     88 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
     89 	     AHCI_QUIRK_BADPMP },
     90 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
     91 	     AHCI_QUIRK_BADPMP },
     92 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
     93 	     AHCI_QUIRK_BADPMP },
     94 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
     95 	     AHCI_QUIRK_BADPMP },
     96 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
     97 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     98 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
     99 	    AHCI_QUIRK_BADPMP },
    100 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
    101 	    AHCI_QUIRK_BADPMP },
    102 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
    103 	    AHCI_QUIRK_BADPMP },
    104 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
    105 	    AHCI_QUIRK_BADPMP },
    106 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
    107 	    AHCI_QUIRK_BADPMP },
    108 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
    109 	    AHCI_QUIRK_BADPMP },
    110 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
    111 	    AHCI_QUIRK_BADPMP },
    112 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
    113 	    AHCI_QUIRK_BADPMP },
    114 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
    115 	    AHCI_QUIRK_BADPMP },
    116 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
    117 	    AHCI_QUIRK_BADPMP },
    118 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
    119 	    AHCI_QUIRK_BADPMP },
    120 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
    121 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    122 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
    123 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    124 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
    125 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    126 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
    127 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    128 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
    129 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    130 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
    131 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    132 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
    133 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    134 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
    135 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    136 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
    137 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    138 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
    139 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    140 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
    141 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    142 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
    143 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    144 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
    145 	    AHCI_QUIRK_BADPMP },
    146 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
    147 	    AHCI_QUIRK_BADPMP },
    148 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
    149 	    AHCI_QUIRK_BADPMP },
    150 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
    151 	    AHCI_QUIRK_BADPMP },
    152 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
    153 	    AHCI_QUIRK_BADPMP },
    154 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
    155 	    AHCI_QUIRK_BADPMP },
    156 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
    157 	    AHCI_QUIRK_BADPMP },
    158 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
    159 	    AHCI_QUIRK_BADPMP },
    160 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
    161 	    AHCI_QUIRK_BADPMP },
    162 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
    163 	    AHCI_QUIRK_BADPMP },
    164 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
    165 	    AHCI_QUIRK_BADPMP },
    166 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
    167 	    AHCI_QUIRK_BADPMP },
    168 	{ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
    169 	    AHCI_PCI_QUIRK_FORCE },
    170 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
    171 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    172 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
    173 	    AHCI_QUIRK_BADPMP },
    174 	{ PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
    175 	    AHCI_PCI_QUIRK_FORCE },
    176 	/* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
    177 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
    178 	    AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    179 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
    180 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    181 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
    182 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    183 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
    184 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    185 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
    186 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    187 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
    188 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    189 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
    190 	    AHCI_QUIRK_BADPMP },
    191 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
    192 	    AHCI_QUIRK_BADPMP },
    193 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
    194 	    AHCI_PCI_QUIRK_FORCE },
    195 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
    196 	    AHCI_PCI_QUIRK_FORCE },
    197 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
    198 	    AHCI_PCI_QUIRK_FORCE },
    199 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
    200 	    AHCI_PCI_QUIRK_FORCE },
    201 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
    202 	    AHCI_PCI_QUIRK_FORCE },
    203 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
    204 	    AHCI_QUIRK_BADPMP },
    205 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
    206 	    AHCI_QUIRK_BADPMP },
    207 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI,
    208 	    AHCI_QUIRK_EXTRA_DELAY },
    209 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BSW_AHCI,
    210 	    AHCI_QUIRK_EXTRA_DELAY },
    211 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SER_DT_SATA_AHCI,
    212 	    AHCI_QUIRK_EXTRA_DELAY },
    213 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SATA_AHCI,
    214 	    AHCI_QUIRK_EXTRA_DELAY },
    215 #if 0
    216 	/*
    217 	 * XXX Non-reproducible failures reported. May need extra-delay quirk.
    218 	 */
    219 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0,
    220 	    AHCI_QUIRK_EXTRA_DELAY },
    221 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1,
    222 	    AHCI_QUIRK_EXTRA_DELAY },
    223 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4,
    224 	    AHCI_QUIRK_EXTRA_DELAY },
    225 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5,
    226 	    AHCI_QUIRK_EXTRA_DELAY },
    227 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6,
    228 	    AHCI_QUIRK_EXTRA_DELAY },
    229 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7,
    230 	    AHCI_QUIRK_EXTRA_DELAY },
    231 #endif
    232 };
    233 
    234 struct ahci_pci_softc {
    235 	struct ahci_softc ah_sc;
    236 	pci_chipset_tag_t sc_pc;
    237 	pcitag_t sc_pcitag;
    238 	pci_intr_handle_t *sc_pihp;
    239 	int sc_nintr;
    240 	void **sc_ih;
    241 };
    242 
    243 static int  ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
    244 static int  ahci_pci_match(device_t, cfdata_t, void *);
    245 static void ahci_pci_attach(device_t, device_t, void *);
    246 static int  ahci_pci_detach(device_t, int);
    247 static void ahci_pci_childdetached(device_t, device_t);
    248 static bool ahci_pci_resume(device_t, const pmf_qual_t *);
    249 
    250 
    251 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
    252     ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
    253     NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
    254 
    255 #define	AHCI_PCI_ABAR_CAVIUM	0x10
    256 
    257 static int
    258 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
    259 {
    260 	int i;
    261 
    262 	for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
    263 		if (vendor == ahci_pci_quirks[i].vendor &&
    264 		    product == ahci_pci_quirks[i].product)
    265 			return ahci_pci_quirks[i].quirks;
    266 	return 0;
    267 }
    268 
    269 static int
    270 ahci_pci_abar(struct pci_attach_args *pa)
    271 {
    272 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
    273 		if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
    274 		    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
    275 			return AHCI_PCI_ABAR_CAVIUM;
    276 		}
    277 	}
    278 
    279 	return AHCI_PCI_ABAR;
    280 }
    281 
    282 
    283 static int
    284 ahci_pci_match(device_t parent, cfdata_t match, void *aux)
    285 {
    286 	struct pci_attach_args *pa = aux;
    287 	bus_space_tag_t regt;
    288 	bus_space_handle_t regh;
    289 	bus_size_t size;
    290 	int ret = 0;
    291 	bool force;
    292 
    293 	force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
    294 	    PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
    295 
    296 	/* if wrong class and not forced by quirks, don't match */
    297 	if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
    298 	    ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
    299 	     PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
    300 	     PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
    301 	    (force == false))
    302 		return 0;
    303 
    304 	int bar = ahci_pci_abar(pa);
    305 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    306 	if (pci_mapreg_map(pa, bar, memtype, 0, &regt, &regh, NULL, &size) != 0)
    307 		return 0;
    308 
    309 	if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
    310 	     PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
    311 	    (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
    312 	    (force == true))
    313 		ret = 3;
    314 
    315 	bus_space_unmap(regt, regh, size);
    316 	return ret;
    317 }
    318 
    319 static int
    320 ahci_pci_intr_establish(struct ahci_softc *sc, int port)
    321 {
    322 	struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
    323 	device_t self = sc->sc_atac.atac_dev;
    324 	char intrbuf[PCI_INTRSTR_LEN];
    325 	char intr_xname[INTRDEVNAMEBUF];
    326 	const char *intrstr;
    327 	int vec;
    328 	int (*intr_handler)(void *);
    329 	void *intr_arg;
    330 
    331 	KASSERT(psc->sc_pihp != NULL);
    332 	KASSERT(psc->sc_nintr > 0);
    333 
    334 	snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
    335 
    336 	if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
    337 		/* Only one interrupt, established on vector 0 */
    338 		intr_handler = ahci_intr;
    339 		intr_arg = sc;
    340 		vec = 0;
    341 
    342 		if (psc->sc_ih[vec] != NULL) {
    343 			/* Already established, nothing more to do */
    344 			goto out;
    345 		}
    346 
    347 	} else {
    348 		/*
    349 		 * Theoretically AHCI device can have less MSI/MSI-X vectors
    350 		 * than supported ports. Hardware is allowed to revert
    351 		 * to single message MSI, but not required to do so.
    352 		 * So handle the case when it did not revert to single MSI.
    353 		 * In this case last available interrupt vector is used
    354 		 * for port == max vector, and all further ports.
    355 		 * This last vector must use the general interrupt handler,
    356 		 * since it needs to be able to handle several ports.
    357 		 * NOTE: such case was never actually observed yet
    358 		 */
    359 		if (sc->sc_atac.atac_nchannels > psc->sc_nintr
    360 		    && port >= (psc->sc_nintr - 1)) {
    361 			intr_handler = ahci_intr;
    362 			intr_arg = sc;
    363 			vec = psc->sc_nintr - 1;
    364 
    365 			if (psc->sc_ih[vec] != NULL) {
    366 				/* Already established, nothing more to do */
    367 				goto out;
    368 			}
    369 
    370 			if (port == vec) {
    371 				/* Print error once */
    372 				aprint_error_dev(self,
    373 				    "port %d independant interrupt vector not "
    374 				    "available, sharing with further ports",
    375 				    port);
    376 			}
    377 		} else {
    378 			/* Vector according to port */
    379 			KASSERT(port < psc->sc_nintr);
    380 			KASSERT(psc->sc_ih[port] == NULL);
    381 			intr_handler = ahci_intr_port;
    382 			intr_arg = &sc->sc_channels[port];
    383 			vec = port;
    384 
    385 			snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
    386 			    device_xname(self), port);
    387 		}
    388 	}
    389 
    390 	intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
    391 	    sizeof(intrbuf));
    392 	psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
    393 	    psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
    394 	if (psc->sc_ih[vec] == NULL) {
    395 		aprint_error_dev(self, "couldn't establish interrupt");
    396 		if (intrstr != NULL)
    397 			aprint_error(" at %s", intrstr);
    398 		aprint_error("\n");
    399 		goto fail;
    400 	}
    401 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    402 
    403 out:
    404 	return 0;
    405 
    406 fail:
    407 	return EAGAIN;
    408 }
    409 
    410 static void
    411 ahci_pci_attach(device_t parent, device_t self, void *aux)
    412 {
    413 	struct pci_attach_args *pa = aux;
    414 	struct ahci_pci_softc *psc = device_private(self);
    415 	struct ahci_softc *sc = &psc->ah_sc;
    416 	bool ahci_cap_64bit;
    417 	bool ahci_bad_64bit;
    418 	pcireg_t reg;
    419 
    420 	sc->sc_atac.atac_dev = self;
    421 
    422 	int bar = ahci_pci_abar(pa);
    423 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    424 	if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
    425 	    NULL, &sc->sc_ahcis) != 0) {
    426 		aprint_error_dev(self, "can't map ahci registers\n");
    427 		return;
    428 	}
    429 	psc->sc_pc = pa->pa_pc;
    430 	psc->sc_pcitag = pa->pa_tag;
    431 
    432 	pci_aprint_devinfo(pa, "AHCI disk controller");
    433 
    434 	int counts[PCI_INTR_TYPE_SIZE] = {
    435 		[PCI_INTR_TYPE_INTX] = 1,
    436 		[PCI_INTR_TYPE_MSI] = 1,
    437 		[PCI_INTR_TYPE_MSIX] = -1,
    438 	};
    439 
    440 	/* Allocate and establish the interrupt. */
    441 	if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
    442 		aprint_error_dev(self, "can't allocate handler\n");
    443 		goto fail;
    444 	}
    445 
    446 	psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
    447 	psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
    448 	sc->sc_intr_establish = ahci_pci_intr_establish;
    449 
    450 	sc->sc_dmat = pa->pa_dmat;
    451 
    452 	sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
    453 					    PCI_PRODUCT(pa->pa_id));
    454 
    455 	ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
    456 	ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
    457 
    458 	if (pci_dma64_available(pa) && ahci_cap_64bit) {
    459 		if (!ahci_bad_64bit)
    460 			sc->sc_dmat = pa->pa_dmat64;
    461 		aprint_verbose_dev(self, "64-bit DMA%s\n",
    462 		    (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
    463 	}
    464 
    465 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
    466 		AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
    467 		sc->sc_atac_capflags = ATAC_CAP_RAID;
    468 	} else {
    469 		AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
    470 	}
    471 
    472 	reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
    473 	reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
    474 	pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
    475 
    476 	ahci_attach(sc);
    477 
    478 	if (!pmf_device_register(self, NULL, ahci_pci_resume))
    479 		aprint_error_dev(self, "couldn't establish power handler\n");
    480 
    481 	return;
    482 fail:
    483 	if (psc->sc_pihp != NULL) {
    484 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    485 		psc->sc_pihp = NULL;
    486 	}
    487 	if (sc->sc_ahcis) {
    488 		bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    489 		sc->sc_ahcis = 0;
    490 	}
    491 
    492 	return;
    493 
    494 }
    495 
    496 static void
    497 ahci_pci_childdetached(device_t dv, device_t child)
    498 {
    499 	struct ahci_pci_softc *psc = device_private(dv);
    500 	struct ahci_softc *sc = &psc->ah_sc;
    501 
    502 	ahci_childdetached(sc, child);
    503 }
    504 
    505 static int
    506 ahci_pci_detach(device_t dv, int flags)
    507 {
    508 	struct ahci_pci_softc *psc;
    509 	struct ahci_softc *sc;
    510 	int rv;
    511 
    512 	psc = device_private(dv);
    513 	sc = &psc->ah_sc;
    514 
    515 	if ((rv = ahci_detach(sc, flags)))
    516 		return rv;
    517 
    518 	pmf_device_deregister(dv);
    519 
    520 	if (psc->sc_ih != NULL) {
    521 		for (int intr = 0; intr < psc->sc_nintr; intr++) {
    522 			if (psc->sc_ih[intr] != NULL) {
    523 				pci_intr_disestablish(psc->sc_pc,
    524 				    psc->sc_ih[intr]);
    525 				psc->sc_ih[intr] = NULL;
    526 			}
    527 		}
    528 
    529 		kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
    530 		psc->sc_ih = NULL;
    531 	}
    532 
    533 	if (psc->sc_pihp != NULL) {
    534 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    535 		psc->sc_pihp = NULL;
    536 	}
    537 
    538 	bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    539 
    540 	return 0;
    541 }
    542 
    543 static bool
    544 ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
    545 {
    546 	struct ahci_pci_softc *psc = device_private(dv);
    547 	struct ahci_softc *sc = &psc->ah_sc;
    548 	int s;
    549 
    550 	s = splbio();
    551 	ahci_resume(sc);
    552 	splx(s);
    553 
    554 	return true;
    555 }
    556