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ahcisata_pci.c revision 1.64
      1 /*	$NetBSD: ahcisata_pci.c,v 1.64 2022/05/29 22:26:21 rin Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2006 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.64 2022/05/29 22:26:21 rin Exp $");
     30 
     31 #ifdef _KERNEL_OPT
     32 #include "opt_ahcisata_pci.h"
     33 #endif
     34 
     35 #include <sys/types.h>
     36 #include <sys/kmem.h>
     37 #include <sys/param.h>
     38 #include <sys/kernel.h>
     39 #include <sys/systm.h>
     40 #include <sys/disklabel.h>
     41 #include <sys/pmf.h>
     42 
     43 #include <dev/pci/pcivar.h>
     44 #include <dev/pci/pcidevs.h>
     45 #include <dev/pci/pciidereg.h>
     46 #include <dev/pci/pciidevar.h>
     47 #include <dev/ic/ahcisatavar.h>
     48 
     49 struct ahci_pci_quirk {
     50 	pci_vendor_id_t  vendor;	/* Vendor ID */
     51 	pci_product_id_t product;	/* Product ID */
     52 	int              quirks;	/* quirks; same as sc_ahci_quirks */
     53 };
     54 
     55 static const struct ahci_pci_quirk ahci_pci_quirks[] = {
     56 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
     57 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     58 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
     59 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     60 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
     61 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     62 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
     63 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     64 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
     65 	    AHCI_QUIRK_BADPMP },
     66 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
     67 	    AHCI_QUIRK_BADPMP },
     68 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
     69 	    AHCI_QUIRK_BADPMP },
     70 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
     71 	    AHCI_QUIRK_BADPMP },
     72 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
     73 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     74 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
     75 	    AHCI_QUIRK_BADPMP },
     76 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
     77 	    AHCI_QUIRK_BADPMP },
     78 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
     79 	     AHCI_QUIRK_BADPMP },
     80 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
     81 	     AHCI_QUIRK_BADPMP },
     82 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
     83 	     AHCI_QUIRK_BADPMP },
     84 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
     85 	     AHCI_QUIRK_BADPMP },
     86 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
     87 	     AHCI_QUIRK_BADPMP },
     88 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
     89 	     AHCI_QUIRK_BADPMP },
     90 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
     91 	     AHCI_QUIRK_BADPMP },
     92 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
     93 	     AHCI_QUIRK_BADPMP },
     94 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
     95 	     AHCI_QUIRK_BADPMP },
     96 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
     97 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
     98 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
     99 	    AHCI_QUIRK_BADPMP },
    100 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
    101 	    AHCI_QUIRK_BADPMP },
    102 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
    103 	    AHCI_QUIRK_BADPMP },
    104 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
    105 	    AHCI_QUIRK_BADPMP },
    106 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
    107 	    AHCI_QUIRK_BADPMP },
    108 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
    109 	    AHCI_QUIRK_BADPMP },
    110 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
    111 	    AHCI_QUIRK_BADPMP },
    112 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
    113 	    AHCI_QUIRK_BADPMP },
    114 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
    115 	    AHCI_QUIRK_BADPMP },
    116 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
    117 	    AHCI_QUIRK_BADPMP },
    118 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
    119 	    AHCI_QUIRK_BADPMP },
    120 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
    121 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    122 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
    123 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    124 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
    125 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    126 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
    127 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    128 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
    129 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    130 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
    131 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    132 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
    133 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    134 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
    135 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    136 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
    137 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    138 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
    139 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    140 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
    141 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    142 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
    143 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    144 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
    145 	    AHCI_QUIRK_BADPMP },
    146 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
    147 	    AHCI_QUIRK_BADPMP },
    148 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
    149 	    AHCI_QUIRK_BADPMP },
    150 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
    151 	    AHCI_QUIRK_BADPMP },
    152 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
    153 	    AHCI_QUIRK_BADPMP },
    154 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
    155 	    AHCI_QUIRK_BADPMP },
    156 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
    157 	    AHCI_QUIRK_BADPMP },
    158 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
    159 	    AHCI_QUIRK_BADPMP },
    160 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
    161 	    AHCI_QUIRK_BADPMP },
    162 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
    163 	    AHCI_QUIRK_BADPMP },
    164 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
    165 	    AHCI_QUIRK_BADPMP },
    166 	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
    167 	    AHCI_QUIRK_BADPMP },
    168 	{ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
    169 	    AHCI_PCI_QUIRK_FORCE },
    170 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
    171 	    AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
    172 	{ PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
    173 	    AHCI_QUIRK_BADPMP },
    174 	{ PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
    175 	    AHCI_PCI_QUIRK_FORCE },
    176 	/* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
    177 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
    178 	    AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    179 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
    180 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    181 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
    182 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    183 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
    184 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    185 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
    186 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    187 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
    188 	    AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
    189 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA,
    190 	    AHCI_QUIRK_BADPMP },
    191 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
    192 	    AHCI_QUIRK_BADPMP },
    193 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
    194 	    AHCI_PCI_QUIRK_FORCE },
    195 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
    196 	    AHCI_PCI_QUIRK_FORCE },
    197 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
    198 	    AHCI_PCI_QUIRK_FORCE },
    199 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
    200 	    AHCI_PCI_QUIRK_FORCE },
    201 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
    202 	    AHCI_PCI_QUIRK_FORCE },
    203 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
    204 	    AHCI_QUIRK_BADPMP },
    205 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
    206 	    AHCI_QUIRK_BADPMP },
    207 
    208     /* extra delay */
    209 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI,
    210 	    AHCI_QUIRK_EXTRA_DELAY },
    211 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SER_MO_SATA_AHCI,
    212 	    AHCI_QUIRK_EXTRA_DELAY },
    213 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BSW_AHCI,
    214 	    AHCI_QUIRK_EXTRA_DELAY },
    215 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SER_DT_SATA_AHCI,
    216 	    AHCI_QUIRK_EXTRA_DELAY },
    217 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SATA_AHCI,
    218 	    AHCI_QUIRK_EXTRA_DELAY },
    219 #if 0
    220 	/*
    221 	 * XXX Non-reproducible failures reported. May need extra-delay quirk.
    222 	 */
    223 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0,
    224 	    AHCI_QUIRK_EXTRA_DELAY },
    225 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1,
    226 	    AHCI_QUIRK_EXTRA_DELAY },
    227 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4,
    228 	    AHCI_QUIRK_EXTRA_DELAY },
    229 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5,
    230 	    AHCI_QUIRK_EXTRA_DELAY },
    231 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6,
    232 	    AHCI_QUIRK_EXTRA_DELAY },
    233 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7,
    234 	    AHCI_QUIRK_EXTRA_DELAY },
    235 #endif
    236 };
    237 
    238 struct ahci_pci_softc {
    239 	struct ahci_softc ah_sc;
    240 	pci_chipset_tag_t sc_pc;
    241 	pcitag_t sc_pcitag;
    242 	pci_intr_handle_t *sc_pihp;
    243 	int sc_nintr;
    244 	void **sc_ih;
    245 };
    246 
    247 static int  ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
    248 static int  ahci_pci_match(device_t, cfdata_t, void *);
    249 static void ahci_pci_attach(device_t, device_t, void *);
    250 static int  ahci_pci_detach(device_t, int);
    251 static void ahci_pci_childdetached(device_t, device_t);
    252 static bool ahci_pci_resume(device_t, const pmf_qual_t *);
    253 
    254 
    255 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
    256     ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
    257     NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
    258 
    259 #define	AHCI_PCI_ABAR_CAVIUM	0x10
    260 
    261 static int
    262 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
    263 {
    264 	int i;
    265 
    266 	for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
    267 		if (vendor == ahci_pci_quirks[i].vendor &&
    268 		    product == ahci_pci_quirks[i].product)
    269 			return ahci_pci_quirks[i].quirks;
    270 	return 0;
    271 }
    272 
    273 static int
    274 ahci_pci_abar(struct pci_attach_args *pa)
    275 {
    276 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
    277 		if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
    278 		    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
    279 			return AHCI_PCI_ABAR_CAVIUM;
    280 		}
    281 	}
    282 
    283 	return AHCI_PCI_ABAR;
    284 }
    285 
    286 
    287 static int
    288 ahci_pci_match(device_t parent, cfdata_t match, void *aux)
    289 {
    290 	struct pci_attach_args *pa = aux;
    291 	bus_space_tag_t regt;
    292 	bus_space_handle_t regh;
    293 	bus_size_t size;
    294 	int ret = 0;
    295 	bool force;
    296 
    297 	force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
    298 	    PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
    299 
    300 	/* if wrong class and not forced by quirks, don't match */
    301 	if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
    302 	    ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
    303 	     PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
    304 	     PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
    305 	    (force == false))
    306 		return 0;
    307 
    308 	int bar = ahci_pci_abar(pa);
    309 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    310 	if (pci_mapreg_map(pa, bar, memtype, 0, &regt, &regh, NULL, &size) != 0)
    311 		return 0;
    312 
    313 	if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
    314 	     PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
    315 	    (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
    316 	    (force == true))
    317 		ret = 3;
    318 
    319 	bus_space_unmap(regt, regh, size);
    320 	return ret;
    321 }
    322 
    323 static int
    324 ahci_pci_intr_establish(struct ahci_softc *sc, int port)
    325 {
    326 	struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
    327 	device_t self = sc->sc_atac.atac_dev;
    328 	char intrbuf[PCI_INTRSTR_LEN];
    329 	char intr_xname[INTRDEVNAMEBUF];
    330 	const char *intrstr;
    331 	int vec;
    332 	int (*intr_handler)(void *);
    333 	void *intr_arg;
    334 
    335 	KASSERT(psc->sc_pihp != NULL);
    336 	KASSERT(psc->sc_nintr > 0);
    337 
    338 	snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
    339 
    340 	if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
    341 		/* Only one interrupt, established on vector 0 */
    342 		intr_handler = ahci_intr;
    343 		intr_arg = sc;
    344 		vec = 0;
    345 
    346 		if (psc->sc_ih[vec] != NULL) {
    347 			/* Already established, nothing more to do */
    348 			goto out;
    349 		}
    350 
    351 	} else {
    352 		/*
    353 		 * Theoretically AHCI device can have less MSI/MSI-X vectors
    354 		 * than supported ports. Hardware is allowed to revert
    355 		 * to single message MSI, but not required to do so.
    356 		 * So handle the case when it did not revert to single MSI.
    357 		 * In this case last available interrupt vector is used
    358 		 * for port == max vector, and all further ports.
    359 		 * This last vector must use the general interrupt handler,
    360 		 * since it needs to be able to handle several ports.
    361 		 * NOTE: such case was never actually observed yet
    362 		 */
    363 		if (sc->sc_atac.atac_nchannels > psc->sc_nintr
    364 		    && port >= (psc->sc_nintr - 1)) {
    365 			intr_handler = ahci_intr;
    366 			intr_arg = sc;
    367 			vec = psc->sc_nintr - 1;
    368 
    369 			if (psc->sc_ih[vec] != NULL) {
    370 				/* Already established, nothing more to do */
    371 				goto out;
    372 			}
    373 
    374 			if (port == vec) {
    375 				/* Print error once */
    376 				aprint_error_dev(self,
    377 				    "port %d independant interrupt vector not "
    378 				    "available, sharing with further ports",
    379 				    port);
    380 			}
    381 		} else {
    382 			/* Vector according to port */
    383 			KASSERT(port < psc->sc_nintr);
    384 			KASSERT(psc->sc_ih[port] == NULL);
    385 			intr_handler = ahci_intr_port;
    386 			intr_arg = &sc->sc_channels[port];
    387 			vec = port;
    388 
    389 			snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
    390 			    device_xname(self), port);
    391 		}
    392 	}
    393 
    394 	intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
    395 	    sizeof(intrbuf));
    396 	psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
    397 	    psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
    398 	if (psc->sc_ih[vec] == NULL) {
    399 		aprint_error_dev(self, "couldn't establish interrupt");
    400 		if (intrstr != NULL)
    401 			aprint_error(" at %s", intrstr);
    402 		aprint_error("\n");
    403 		goto fail;
    404 	}
    405 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    406 
    407 out:
    408 	return 0;
    409 
    410 fail:
    411 	return EAGAIN;
    412 }
    413 
    414 static void
    415 ahci_pci_attach(device_t parent, device_t self, void *aux)
    416 {
    417 	struct pci_attach_args *pa = aux;
    418 	struct ahci_pci_softc *psc = device_private(self);
    419 	struct ahci_softc *sc = &psc->ah_sc;
    420 	bool ahci_cap_64bit;
    421 	bool ahci_bad_64bit;
    422 	pcireg_t reg;
    423 
    424 	sc->sc_atac.atac_dev = self;
    425 
    426 	int bar = ahci_pci_abar(pa);
    427 	pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
    428 	if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
    429 	    NULL, &sc->sc_ahcis) != 0) {
    430 		aprint_error_dev(self, "can't map ahci registers\n");
    431 		return;
    432 	}
    433 	psc->sc_pc = pa->pa_pc;
    434 	psc->sc_pcitag = pa->pa_tag;
    435 
    436 	pci_aprint_devinfo(pa, "AHCI disk controller");
    437 
    438 	int counts[PCI_INTR_TYPE_SIZE] = {
    439 		[PCI_INTR_TYPE_INTX] = 1,
    440 		[PCI_INTR_TYPE_MSI] = 1,
    441 		[PCI_INTR_TYPE_MSIX] = -1,
    442 	};
    443 
    444 	/* Allocate and establish the interrupt. */
    445 	if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
    446 		aprint_error_dev(self, "can't allocate handler\n");
    447 		goto fail;
    448 	}
    449 
    450 	psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
    451 	psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
    452 	sc->sc_intr_establish = ahci_pci_intr_establish;
    453 
    454 	sc->sc_dmat = pa->pa_dmat;
    455 
    456 	sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
    457 					    PCI_PRODUCT(pa->pa_id));
    458 
    459 	ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
    460 	ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
    461 
    462 	if (pci_dma64_available(pa) && ahci_cap_64bit) {
    463 		if (!ahci_bad_64bit)
    464 			sc->sc_dmat = pa->pa_dmat64;
    465 		aprint_verbose_dev(self, "64-bit DMA%s\n",
    466 		    (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
    467 	}
    468 
    469 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
    470 		AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
    471 		sc->sc_atac_capflags = ATAC_CAP_RAID;
    472 	} else {
    473 		AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
    474 	}
    475 
    476 	reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
    477 	reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
    478 	pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
    479 
    480 	ahci_attach(sc);
    481 
    482 	if (!pmf_device_register(self, NULL, ahci_pci_resume))
    483 		aprint_error_dev(self, "couldn't establish power handler\n");
    484 
    485 	return;
    486 fail:
    487 	if (psc->sc_pihp != NULL) {
    488 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    489 		psc->sc_pihp = NULL;
    490 	}
    491 	if (sc->sc_ahcis) {
    492 		bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    493 		sc->sc_ahcis = 0;
    494 	}
    495 
    496 	return;
    497 
    498 }
    499 
    500 static void
    501 ahci_pci_childdetached(device_t dv, device_t child)
    502 {
    503 	struct ahci_pci_softc *psc = device_private(dv);
    504 	struct ahci_softc *sc = &psc->ah_sc;
    505 
    506 	ahci_childdetached(sc, child);
    507 }
    508 
    509 static int
    510 ahci_pci_detach(device_t dv, int flags)
    511 {
    512 	struct ahci_pci_softc *psc;
    513 	struct ahci_softc *sc;
    514 	int rv;
    515 
    516 	psc = device_private(dv);
    517 	sc = &psc->ah_sc;
    518 
    519 	if ((rv = ahci_detach(sc, flags)))
    520 		return rv;
    521 
    522 	pmf_device_deregister(dv);
    523 
    524 	if (psc->sc_ih != NULL) {
    525 		for (int intr = 0; intr < psc->sc_nintr; intr++) {
    526 			if (psc->sc_ih[intr] != NULL) {
    527 				pci_intr_disestablish(psc->sc_pc,
    528 				    psc->sc_ih[intr]);
    529 				psc->sc_ih[intr] = NULL;
    530 			}
    531 		}
    532 
    533 		kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
    534 		psc->sc_ih = NULL;
    535 	}
    536 
    537 	if (psc->sc_pihp != NULL) {
    538 		pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
    539 		psc->sc_pihp = NULL;
    540 	}
    541 
    542 	bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
    543 
    544 	return 0;
    545 }
    546 
    547 static bool
    548 ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
    549 {
    550 	struct ahci_pci_softc *psc = device_private(dv);
    551 	struct ahci_softc *sc = &psc->ah_sc;
    552 	int s;
    553 
    554 	s = splbio();
    555 	ahci_resume(sc);
    556 	splx(s);
    557 
    558 	return true;
    559 }
    560