ahcisata_pci.c revision 1.69
1 /* $NetBSD: ahcisata_pci.c,v 1.69 2023/07/31 11:24:32 tnn Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.69 2023/07/31 11:24:32 tnn Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/disklabel.h> 41 #include <sys/pmf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 struct ahci_pci_quirk { 50 pci_vendor_id_t vendor; /* Vendor ID */ 51 pci_product_id_t product; /* Product ID */ 52 int quirks; /* quirks; same as sc_ahci_quirks */ 53 }; 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 65 AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 77 AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 101 AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 145 AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 147 AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 169 AHCI_PCI_QUIRK_FORCE }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 173 AHCI_QUIRK_BADPMP }, 174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 175 AHCI_PCI_QUIRK_FORCE }, 176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 180 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 182 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 184 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 186 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 188 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA, 190 AHCI_QUIRK_BADPMP }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 192 AHCI_QUIRK_BADPMP }, 193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 194 AHCI_PCI_QUIRK_FORCE }, 195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 196 AHCI_PCI_QUIRK_FORCE }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 200 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_EXTRA_DELAY }, 201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA, 202 AHCI_PCI_QUIRK_FORCE }, 203 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI, 204 AHCI_QUIRK_BADPMP }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI, 206 AHCI_QUIRK_BADPMP }, 207 208 /* extra delay */ 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI, 210 AHCI_QUIRK_EXTRA_DELAY }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SER_MO_SATA_AHCI, 212 AHCI_QUIRK_EXTRA_DELAY }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BSW_AHCI, 214 AHCI_QUIRK_EXTRA_DELAY }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SER_DT_SATA_AHCI, 216 AHCI_QUIRK_EXTRA_DELAY }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SATA_AHCI, 218 AHCI_QUIRK_EXTRA_DELAY }, 219 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_FCH_SATA_D, AHCI_QUIRK_EXTRA_DELAY }, 220 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM106X, 221 AHCI_QUIRK_EXTRA_DELAY }, 222 223 #if 0 224 /* 225 * XXX Non-reproducible failures reported. May need extra-delay quirk. 226 */ 227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0, 228 AHCI_QUIRK_EXTRA_DELAY }, 229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1, 230 AHCI_QUIRK_EXTRA_DELAY }, 231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4, 232 AHCI_QUIRK_EXTRA_DELAY }, 233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5, 234 AHCI_QUIRK_EXTRA_DELAY }, 235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6, 236 AHCI_QUIRK_EXTRA_DELAY }, 237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7, 238 AHCI_QUIRK_EXTRA_DELAY }, 239 #endif 240 }; 241 242 struct ahci_pci_softc { 243 struct ahci_softc ah_sc; 244 pci_chipset_tag_t sc_pc; 245 pcitag_t sc_pcitag; 246 pci_intr_handle_t *sc_pihp; 247 int sc_nintr; 248 void **sc_ih; 249 }; 250 251 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 252 static int ahci_pci_match(device_t, cfdata_t, void *); 253 static void ahci_pci_attach(device_t, device_t, void *); 254 static int ahci_pci_detach(device_t, int); 255 static void ahci_pci_childdetached(device_t, device_t); 256 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 257 258 259 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 260 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 261 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 262 263 #define AHCI_PCI_ABAR_CAVIUM 0x10 264 265 static int 266 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 267 { 268 int i; 269 270 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 271 if (vendor == ahci_pci_quirks[i].vendor && 272 product == ahci_pci_quirks[i].product) 273 return ahci_pci_quirks[i].quirks; 274 return 0; 275 } 276 277 static int 278 ahci_pci_abar(struct pci_attach_args *pa) 279 { 280 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 281 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 282 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 283 return AHCI_PCI_ABAR_CAVIUM; 284 } 285 } 286 287 return AHCI_PCI_ABAR; 288 } 289 290 291 static int 292 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 293 { 294 struct pci_attach_args *pa = aux; 295 bus_space_tag_t regt; 296 bus_space_handle_t regh; 297 bus_size_t size; 298 int ret = 0; 299 bool force; 300 301 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 302 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 303 304 /* if wrong class and not forced by quirks, don't match */ 305 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 306 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 307 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 308 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 309 (force == false)) 310 return 0; 311 312 int bar = ahci_pci_abar(pa); 313 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 314 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 315 return 0; 316 317 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 318 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 319 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 320 (force == true)) 321 ret = 3; 322 323 bus_space_unmap(regt, regh, size); 324 return ret; 325 } 326 327 static int 328 ahci_pci_intr_establish(struct ahci_softc *sc, int port) 329 { 330 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc; 331 device_t self = sc->sc_atac.atac_dev; 332 char intrbuf[PCI_INTRSTR_LEN]; 333 char intr_xname[INTRDEVNAMEBUF]; 334 const char *intrstr; 335 int vec; 336 int (*intr_handler)(void *); 337 void *intr_arg; 338 339 KASSERT(psc->sc_pihp != NULL); 340 KASSERT(psc->sc_nintr > 0); 341 342 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self)); 343 344 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) { 345 /* Only one interrupt, established on vector 0 */ 346 intr_handler = ahci_intr; 347 intr_arg = sc; 348 vec = 0; 349 350 if (psc->sc_ih[vec] != NULL) { 351 /* Already established, nothing more to do */ 352 goto out; 353 } 354 355 } else { 356 /* 357 * Theoretically AHCI device can have less MSI/MSI-X vectors 358 * than supported ports. Hardware is allowed to revert 359 * to single message MSI, but not required to do so. 360 * So handle the case when it did not revert to single MSI. 361 * In this case last available interrupt vector is used 362 * for port == max vector, and all further ports. 363 * This last vector must use the general interrupt handler, 364 * since it needs to be able to handle several ports. 365 * NOTE: such case was never actually observed yet 366 */ 367 if (sc->sc_atac.atac_nchannels > psc->sc_nintr 368 && port >= (psc->sc_nintr - 1)) { 369 intr_handler = ahci_intr; 370 intr_arg = sc; 371 vec = psc->sc_nintr - 1; 372 373 if (psc->sc_ih[vec] != NULL) { 374 /* Already established, nothing more to do */ 375 goto out; 376 } 377 378 if (port == vec) { 379 /* Print error once */ 380 aprint_error_dev(self, 381 "port %d independent interrupt vector not " 382 "available, sharing with further ports", 383 port); 384 } 385 } else { 386 /* Vector according to port */ 387 KASSERT(port < psc->sc_nintr); 388 KASSERT(psc->sc_ih[port] == NULL); 389 intr_handler = ahci_intr_port; 390 intr_arg = &sc->sc_channels[port]; 391 vec = port; 392 393 snprintf(intr_xname, sizeof(intr_xname), "%s port%d", 394 device_xname(self), port); 395 } 396 } 397 398 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf, 399 sizeof(intrbuf)); 400 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc, 401 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname); 402 if (psc->sc_ih[vec] == NULL) { 403 aprint_error_dev(self, "couldn't establish interrupt"); 404 if (intrstr != NULL) 405 aprint_error(" at %s", intrstr); 406 aprint_error("\n"); 407 goto fail; 408 } 409 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 410 411 out: 412 return 0; 413 414 fail: 415 return EAGAIN; 416 } 417 418 static void 419 ahci_pci_attach(device_t parent, device_t self, void *aux) 420 { 421 struct pci_attach_args *pa = aux; 422 struct ahci_pci_softc *psc = device_private(self); 423 struct ahci_softc *sc = &psc->ah_sc; 424 bool ahci_cap_64bit; 425 bool ahci_bad_64bit; 426 pcireg_t reg; 427 428 sc->sc_atac.atac_dev = self; 429 430 int bar = ahci_pci_abar(pa); 431 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 432 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 433 NULL, &sc->sc_ahcis) != 0) { 434 aprint_error_dev(self, "can't map ahci registers\n"); 435 return; 436 } 437 psc->sc_pc = pa->pa_pc; 438 psc->sc_pcitag = pa->pa_tag; 439 440 pci_aprint_devinfo(pa, "AHCI disk controller"); 441 442 int counts[PCI_INTR_TYPE_SIZE] = { 443 [PCI_INTR_TYPE_INTX] = 1, 444 [PCI_INTR_TYPE_MSI] = 1, 445 [PCI_INTR_TYPE_MSIX] = -1, 446 }; 447 448 /* Allocate and establish the interrupt. */ 449 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) { 450 aprint_error_dev(self, "can't allocate handler\n"); 451 goto fail; 452 } 453 454 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])]; 455 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP); 456 sc->sc_intr_establish = ahci_pci_intr_establish; 457 458 sc->sc_dmat = pa->pa_dmat; 459 460 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 461 PCI_PRODUCT(pa->pa_id)); 462 463 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 464 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 465 466 if (pci_dma64_available(pa) && ahci_cap_64bit) { 467 if (!ahci_bad_64bit) 468 sc->sc_dmat = pa->pa_dmat64; 469 aprint_verbose_dev(self, "64-bit DMA%s\n", 470 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 471 } 472 473 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 474 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 475 sc->sc_atac_capflags = ATAC_CAP_RAID; 476 } else { 477 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 478 } 479 480 reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG); 481 reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); 482 pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 483 484 ahci_attach(sc); 485 486 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 487 aprint_error_dev(self, "couldn't establish power handler\n"); 488 489 return; 490 fail: 491 if (psc->sc_pihp != NULL) { 492 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 493 psc->sc_pihp = NULL; 494 } 495 if (sc->sc_ahcis) { 496 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 497 sc->sc_ahcis = 0; 498 } 499 500 return; 501 502 } 503 504 static void 505 ahci_pci_childdetached(device_t dv, device_t child) 506 { 507 struct ahci_pci_softc *psc = device_private(dv); 508 struct ahci_softc *sc = &psc->ah_sc; 509 510 ahci_childdetached(sc, child); 511 } 512 513 static int 514 ahci_pci_detach(device_t dv, int flags) 515 { 516 struct ahci_pci_softc *psc; 517 struct ahci_softc *sc; 518 int rv; 519 520 psc = device_private(dv); 521 sc = &psc->ah_sc; 522 523 if ((rv = ahci_detach(sc, flags))) 524 return rv; 525 526 pmf_device_deregister(dv); 527 528 if (psc->sc_ih != NULL) { 529 for (int intr = 0; intr < psc->sc_nintr; intr++) { 530 if (psc->sc_ih[intr] != NULL) { 531 pci_intr_disestablish(psc->sc_pc, 532 psc->sc_ih[intr]); 533 psc->sc_ih[intr] = NULL; 534 } 535 } 536 537 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr); 538 psc->sc_ih = NULL; 539 } 540 541 if (psc->sc_pihp != NULL) { 542 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 543 psc->sc_pihp = NULL; 544 } 545 546 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 547 548 return 0; 549 } 550 551 static bool 552 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 553 { 554 struct ahci_pci_softc *psc = device_private(dv); 555 struct ahci_softc *sc = &psc->ah_sc; 556 int s; 557 558 s = splbio(); 559 ahci_resume(sc); 560 splx(s); 561 562 return true; 563 } 564
Indexes created Thu Oct 02 14:10:14 GMT 2025