ahcisata_pci.c revision 1.70
1 /* $NetBSD: ahcisata_pci.c,v 1.70 2023/09/10 14:04:28 abs Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.70 2023/09/10 14:04:28 abs Exp $"); 30 31 #ifdef _KERNEL_OPT 32 #include "opt_ahcisata_pci.h" 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/param.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/disklabel.h> 41 #include <sys/pmf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/ic/ahcisatavar.h> 48 49 struct ahci_pci_quirk { 50 pci_vendor_id_t vendor; /* Vendor ID */ 51 pci_product_id_t product; /* Product ID */ 52 int quirks; /* quirks; same as sc_ahci_quirks */ 53 }; 54 55 static const struct ahci_pci_quirk ahci_pci_quirks[] = { 56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA, 57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2, 59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3, 61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4, 63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 65 AHCI_QUIRK_BADPMP }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 AHCI_QUIRK_BADPMP }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 69 AHCI_QUIRK_BADPMP }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 71 AHCI_QUIRK_BADPMP }, 72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA, 73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2, 75 AHCI_QUIRK_BADPMP }, 76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3, 77 AHCI_QUIRK_BADPMP }, 78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4, 79 AHCI_QUIRK_BADPMP }, 80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 81 AHCI_QUIRK_BADPMP }, 82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2, 83 AHCI_QUIRK_BADPMP }, 84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3, 85 AHCI_QUIRK_BADPMP }, 86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4, 87 AHCI_QUIRK_BADPMP }, 88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5, 89 AHCI_QUIRK_BADPMP }, 90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6, 91 AHCI_QUIRK_BADPMP }, 92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7, 93 AHCI_QUIRK_BADPMP }, 94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8, 95 AHCI_QUIRK_BADPMP }, 96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1, 97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2, 99 AHCI_QUIRK_BADPMP }, 100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3, 101 AHCI_QUIRK_BADPMP }, 102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4, 103 AHCI_QUIRK_BADPMP }, 104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5, 105 AHCI_QUIRK_BADPMP }, 106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6, 107 AHCI_QUIRK_BADPMP }, 108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7, 109 AHCI_QUIRK_BADPMP }, 110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8, 111 AHCI_QUIRK_BADPMP }, 112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9, 113 AHCI_QUIRK_BADPMP }, 114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10, 115 AHCI_QUIRK_BADPMP }, 116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11, 117 AHCI_QUIRK_BADPMP }, 118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12, 119 AHCI_QUIRK_BADPMP }, 120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1, 121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2, 123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3, 125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4, 127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6, 131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7, 133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8, 135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9, 137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10, 139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11, 141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12, 143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1, 145 AHCI_QUIRK_BADPMP }, 146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2, 147 AHCI_QUIRK_BADPMP }, 148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3, 149 AHCI_QUIRK_BADPMP }, 150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4, 151 AHCI_QUIRK_BADPMP }, 152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5, 153 AHCI_QUIRK_BADPMP }, 154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6, 155 AHCI_QUIRK_BADPMP }, 156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7, 157 AHCI_QUIRK_BADPMP }, 158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8, 159 AHCI_QUIRK_BADPMP }, 160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9, 161 AHCI_QUIRK_BADPMP }, 162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10, 163 AHCI_QUIRK_BADPMP }, 164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11, 165 AHCI_QUIRK_BADPMP }, 166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12, 167 AHCI_QUIRK_BADPMP }, 168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288, 169 AHCI_PCI_QUIRK_FORCE }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, 171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, 173 AHCI_QUIRK_BADPMP }, 174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX, 175 AHCI_PCI_QUIRK_FORCE }, 176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */ 177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1, 178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI, 180 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID, 182 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5, 184 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2, 186 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE, 188 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ }, 189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237R_SATA, 190 AHCI_QUIRK_BADPMP }, 191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 192 AHCI_QUIRK_BADPMP }, 193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01, 194 AHCI_PCI_QUIRK_FORCE }, 195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02, 196 AHCI_PCI_QUIRK_FORCE }, 197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11, 198 AHCI_PCI_QUIRK_FORCE }, 199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12, 200 AHCI_PCI_QUIRK_FORCE }, 201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA, 202 AHCI_PCI_QUIRK_FORCE }, 203 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI, 204 AHCI_QUIRK_BADPMP }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI, 206 AHCI_QUIRK_BADPMP }, 207 }; 208 209 struct ahci_pci_softc { 210 struct ahci_softc ah_sc; 211 pci_chipset_tag_t sc_pc; 212 pcitag_t sc_pcitag; 213 pci_intr_handle_t *sc_pihp; 214 int sc_nintr; 215 void **sc_ih; 216 }; 217 218 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t); 219 static int ahci_pci_match(device_t, cfdata_t, void *); 220 static void ahci_pci_attach(device_t, device_t, void *); 221 static int ahci_pci_detach(device_t, int); 222 static void ahci_pci_childdetached(device_t, device_t); 223 static bool ahci_pci_resume(device_t, const pmf_qual_t *); 224 225 226 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc), 227 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL, 228 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN); 229 230 #define AHCI_PCI_ABAR_CAVIUM 0x10 231 232 static int 233 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product) 234 { 235 int i; 236 237 for (i = 0; i < __arraycount(ahci_pci_quirks); i++) 238 if (vendor == ahci_pci_quirks[i].vendor && 239 product == ahci_pci_quirks[i].product) 240 return ahci_pci_quirks[i].quirks; 241 return 0; 242 } 243 244 static int 245 ahci_pci_abar(struct pci_attach_args *pa) 246 { 247 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) { 248 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI || 249 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) { 250 return AHCI_PCI_ABAR_CAVIUM; 251 } 252 } 253 254 return AHCI_PCI_ABAR; 255 } 256 257 258 static int 259 ahci_pci_match(device_t parent, cfdata_t match, void *aux) 260 { 261 struct pci_attach_args *pa = aux; 262 bus_space_tag_t regt; 263 bus_space_handle_t regh; 264 bus_size_t size; 265 int ret = 0; 266 bool force; 267 268 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id), 269 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0); 270 271 /* if wrong class and not forced by quirks, don't match */ 272 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE || 273 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA || 274 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) && 275 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) && 276 (force == false)) 277 return 0; 278 279 int bar = ahci_pci_abar(pa); 280 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 281 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0) 282 return 0; 283 284 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA && 285 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) || 286 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) || 287 (force == true)) 288 ret = 3; 289 290 bus_space_unmap(regt, regh, size); 291 return ret; 292 } 293 294 static int 295 ahci_pci_intr_establish(struct ahci_softc *sc, int port) 296 { 297 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc; 298 device_t self = sc->sc_atac.atac_dev; 299 char intrbuf[PCI_INTRSTR_LEN]; 300 char intr_xname[INTRDEVNAMEBUF]; 301 const char *intrstr; 302 int vec; 303 int (*intr_handler)(void *); 304 void *intr_arg; 305 306 KASSERT(psc->sc_pihp != NULL); 307 KASSERT(psc->sc_nintr > 0); 308 309 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self)); 310 311 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) { 312 /* Only one interrupt, established on vector 0 */ 313 intr_handler = ahci_intr; 314 intr_arg = sc; 315 vec = 0; 316 317 if (psc->sc_ih[vec] != NULL) { 318 /* Already established, nothing more to do */ 319 goto out; 320 } 321 322 } else { 323 /* 324 * Theoretically AHCI device can have less MSI/MSI-X vectors 325 * than supported ports. Hardware is allowed to revert 326 * to single message MSI, but not required to do so. 327 * So handle the case when it did not revert to single MSI. 328 * In this case last available interrupt vector is used 329 * for port == max vector, and all further ports. 330 * This last vector must use the general interrupt handler, 331 * since it needs to be able to handle several ports. 332 * NOTE: such case was never actually observed yet 333 */ 334 if (sc->sc_atac.atac_nchannels > psc->sc_nintr 335 && port >= (psc->sc_nintr - 1)) { 336 intr_handler = ahci_intr; 337 intr_arg = sc; 338 vec = psc->sc_nintr - 1; 339 340 if (psc->sc_ih[vec] != NULL) { 341 /* Already established, nothing more to do */ 342 goto out; 343 } 344 345 if (port == vec) { 346 /* Print error once */ 347 aprint_error_dev(self, 348 "port %d independent interrupt vector not " 349 "available, sharing with further ports", 350 port); 351 } 352 } else { 353 /* Vector according to port */ 354 KASSERT(port < psc->sc_nintr); 355 KASSERT(psc->sc_ih[port] == NULL); 356 intr_handler = ahci_intr_port; 357 intr_arg = &sc->sc_channels[port]; 358 vec = port; 359 360 snprintf(intr_xname, sizeof(intr_xname), "%s port%d", 361 device_xname(self), port); 362 } 363 } 364 365 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf, 366 sizeof(intrbuf)); 367 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc, 368 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname); 369 if (psc->sc_ih[vec] == NULL) { 370 aprint_error_dev(self, "couldn't establish interrupt"); 371 if (intrstr != NULL) 372 aprint_error(" at %s", intrstr); 373 aprint_error("\n"); 374 goto fail; 375 } 376 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 377 378 out: 379 return 0; 380 381 fail: 382 return EAGAIN; 383 } 384 385 static void 386 ahci_pci_attach(device_t parent, device_t self, void *aux) 387 { 388 struct pci_attach_args *pa = aux; 389 struct ahci_pci_softc *psc = device_private(self); 390 struct ahci_softc *sc = &psc->ah_sc; 391 bool ahci_cap_64bit; 392 bool ahci_bad_64bit; 393 pcireg_t reg; 394 395 sc->sc_atac.atac_dev = self; 396 397 int bar = ahci_pci_abar(pa); 398 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar); 399 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih, 400 NULL, &sc->sc_ahcis) != 0) { 401 aprint_error_dev(self, "can't map ahci registers\n"); 402 return; 403 } 404 psc->sc_pc = pa->pa_pc; 405 psc->sc_pcitag = pa->pa_tag; 406 407 pci_aprint_devinfo(pa, "AHCI disk controller"); 408 409 int counts[PCI_INTR_TYPE_SIZE] = { 410 [PCI_INTR_TYPE_INTX] = 1, 411 [PCI_INTR_TYPE_MSI] = 1, 412 [PCI_INTR_TYPE_MSIX] = -1, 413 }; 414 415 /* Allocate and establish the interrupt. */ 416 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) { 417 aprint_error_dev(self, "can't allocate handler\n"); 418 goto fail; 419 } 420 421 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])]; 422 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP); 423 sc->sc_intr_establish = ahci_pci_intr_establish; 424 425 sc->sc_dmat = pa->pa_dmat; 426 427 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id), 428 PCI_PRODUCT(pa->pa_id)); 429 430 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0; 431 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0); 432 433 if (pci_dma64_available(pa) && ahci_cap_64bit) { 434 if (!ahci_bad_64bit) 435 sc->sc_dmat = pa->pa_dmat64; 436 aprint_verbose_dev(self, "64-bit DMA%s\n", 437 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : ""); 438 } 439 440 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 441 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE); 442 sc->sc_atac_capflags = ATAC_CAP_RAID; 443 } else { 444 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE); 445 } 446 447 reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG); 448 reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); 449 pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 450 451 ahci_attach(sc); 452 453 if (!pmf_device_register(self, NULL, ahci_pci_resume)) 454 aprint_error_dev(self, "couldn't establish power handler\n"); 455 456 return; 457 fail: 458 if (psc->sc_pihp != NULL) { 459 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 460 psc->sc_pihp = NULL; 461 } 462 if (sc->sc_ahcis) { 463 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 464 sc->sc_ahcis = 0; 465 } 466 467 return; 468 469 } 470 471 static void 472 ahci_pci_childdetached(device_t dv, device_t child) 473 { 474 struct ahci_pci_softc *psc = device_private(dv); 475 struct ahci_softc *sc = &psc->ah_sc; 476 477 ahci_childdetached(sc, child); 478 } 479 480 static int 481 ahci_pci_detach(device_t dv, int flags) 482 { 483 struct ahci_pci_softc *psc; 484 struct ahci_softc *sc; 485 int rv; 486 487 psc = device_private(dv); 488 sc = &psc->ah_sc; 489 490 if ((rv = ahci_detach(sc, flags))) 491 return rv; 492 493 pmf_device_deregister(dv); 494 495 if (psc->sc_ih != NULL) { 496 for (int intr = 0; intr < psc->sc_nintr; intr++) { 497 if (psc->sc_ih[intr] != NULL) { 498 pci_intr_disestablish(psc->sc_pc, 499 psc->sc_ih[intr]); 500 psc->sc_ih[intr] = NULL; 501 } 502 } 503 504 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr); 505 psc->sc_ih = NULL; 506 } 507 508 if (psc->sc_pihp != NULL) { 509 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr); 510 psc->sc_pihp = NULL; 511 } 512 513 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis); 514 515 return 0; 516 } 517 518 static bool 519 ahci_pci_resume(device_t dv, const pmf_qual_t *qual) 520 { 521 struct ahci_pci_softc *psc = device_private(dv); 522 struct ahci_softc *sc = &psc->ah_sc; 523 int s; 524 525 s = splbio(); 526 ahci_resume(sc); 527 splx(s); 528 529 return true; 530 } 531
Indexes created Tue Sep 30 20:09:53 GMT 2025