1 /* $NetBSD: cxdtvreg.h,v 1.3 2015/07/11 10:32:46 kamil Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2008 Jonathan A. Kollasch <jakllsch (at) kollasch.net> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _DEV_PCI_CXDTVREG_H 31 #define _DEV_PCI_CXDTVREG_H 32 33 /* misc. registers */ 34 35 #define CXDTV_PDMA_STHRSH 0x200000 36 #define CXDTV_PDMA_STRGT_ADRS 0x200004 37 #define CXDTV_PDMA_SINTL_ADRS 0x200008 38 #define CXDTV_PDMA_SCNTRL 0x20000c 39 #define CXDTV_PDMA_DTHRSH 0x200010 40 #define CXDTV_PDMA_DTRGT_ADRS 0x200014 41 #define CXDTV_PDMA_DINTL_ADRS 0x200018 42 #define CXDTV_PDMA_DCNTRL 0x20001c 43 #define CXDTV_LD_SUBSYS_ID_CFG 0x200030 44 #define CXDTV_DEV_CNTRL2 0x200034 45 #define CXDTV_PCI_INT_MASK 0x200040 46 #define CXDTV_PCI_INT_STAT 0x200044 47 #define CXDTV_PCI_INT_MSTAT 0x200048 48 #define CXDTV_PLL_B 0x35c008 49 #define CXDTV_GP0_IO 0x350010 /* GPIO */ 50 #define CXDTV_GP1_IO 0x350014 51 #define CXDTV_GP2_IO 0x350018 52 #define CXDTV_GP3_IO 0x35001c 53 #define CXDTV_GPIO 0x350010 /* alt. GPIO mode */ 54 #define CXDTV_GPOE 0x350014 55 #define CXDTV_GPIO_ISM 0x350028 56 #define CXDTV_TM_CNT1_LDW 0x35c034 57 #define CXDTV_TM_CNT1_UDW 0x35c038 58 #define CXDTV_TM_LMT1_LDW 0x35c03c 59 #define CXDTV_TM_LMT1_UDW 0x35c040 60 #define CXDTV_PINMUX_IO 0x35c044 61 #define CXDTV_AFE_CFG_IO 0x35c04c 62 #define CXDTV_SRST_IO 0x35c05c 63 #define CXDTV_I2C_C_DIRECT 0x360000 /* start; 0x367fff end */ 64 #define CXDTV_I2C_C_DATACONTROL 0x368000 65 #define CXDTV_I2C_C_DATACONTROL_SDA 1 66 #define CXDTV_I2C_C_DATACONTROL_SCL 2 67 #define CXDTV_I2C_C_CTRL 0x36c004 68 #define CXDTV_I2C_C_XFER_STATUS 0x36c044 69 70 /* for CXDTV_PCI_INT_ registers */ 71 #define CXT_PI_VID_INT __BIT(0) 72 #define CXT_PI_AUD_INT __BIT(1) 73 #define CXT_PI_TS_INT __BIT(2) 74 #define CXT_PI_VIP_INT __BIT(3) 75 #define CXT_PI_HST_INT __BIT(4) 76 77 #define CXDTV_DEV_CNTRL2_RUN_RISC __BIT(5) 78 79 /* PINMUX_IO */ 80 #define MPEG_PAR_EN __BIT(7) 81 82 /* MPEG TS registers */ 83 84 #define CXDTV_DMA28_PTR1 0x30009c 85 #define CXDTV_DMA28_PTR2 0x3000dc 86 #define CXDTV_DMA28_CNT1 0x30011c 87 #define CXDTV_DMA28_CNT2 0x30015c 88 #define CXDTV_TS_GP_CNT 0x33c020 89 #define CXDTV_TS_GP_CNT_CNTRL 0x33c030 90 #define CXDTV_TS_DMA_CNTRL 0x33c040 91 #define CXDTV_TS_XFER_STATUS 0x33c044 92 #define CXDTV_TS_LNGTH 0x33c048 93 #define CXDTV_HW_SOP_CONTROL 0x33c04c 94 #define CXDTV_TS_GEN_CONTROL 0x33c050 95 #define CXDTV_TS_BD_PKT_STATUS 0x33c054 96 #define CXDTV_TS_SOP_STATUS 0x33c058 97 #define CXDTV_TS_FIFO_OVFL_STAT 0x33c05c 98 #define CXDTV_TS_VLD_MISC 0x33c060 99 #define CXDTV_TS_INT_MASK 0x200070 100 #define CXDTV_TS_INT_STAT 0x200074 101 #define CXDTV_TS_INT_MSTAT 0x200078 102 #define CXDTV_TS_INT_SSTAT 0x20007c 103 104 /* TS_DMA_CNTRL */ 105 #define CXDTV_TS_RISC_EN __BIT(4) 106 #define CXDTV_TS_FIFO_EN __BIT(0) 107 108 /* TS_INT_* */ 109 #define CXDTV_TS_RISCI2 __BIT(4) 110 #define CXDTV_TS_RISCI1 __BIT(0) 111 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI2|CXDTV_TS_RISCI1) 112 113 /* HW_SOP_CONTROL */ 114 115 /* TS_GEN_CONTROL */ 116 #define MPEG_IN_SYNC __BIT(0) 117 #define IPB_MCLK_POL __BIT(1) 118 #define IPB_PUNC_CLK __BIT(2) 119 #define IPB_SMODE __BIT(3) 120 #define IPB_BIT_RVRS __BIT(4) 121 #define IPB_ERR_ACK __BIT(5) 122 #define IPB_SW_RST __BIT(6) 123 #define IPB_STAT_CLR __BIT(7) 124 125 /* TS_SOP_STATUS */ 126 #define MPG_BAD_SOP_STAT __BITS(11,0) 127 #define IPB_SOP_SYNC_CHK __BIT(12) 128 #define IPB_SOP_BYTEWIDE __BIT(13) 129 #define IPB_SOP_SEL __BITS(15, 14) 130 #define IPB_TSSOP_POL __BIT(16) 131 132 /* RISC instructions */ 133 #define CX_RISC_WRITECR 0xd0000000 134 #define CX_RISC_WRITECM 0xc0000000 135 #define CX_RISC_WRITERM 0xb0000000 136 #define CX_RISC_READC 0xa0000000 137 #define CX_RISC_READ 0x90000000 138 #define CX_RISC_SYNC 0x80000000 139 #define CX_RISC_JUMP 0x70000000 140 #define CX_RISC_WRITEC 0x50000000 141 #define CX_RISC_SKIP 0x20000000 142 #define CX_RISC_WRITE 0x10000000 143 #define CX_RISC_SOL 0x08000000 144 #define CX_RISC_EOL 0x04000000 145 #define CX_RISC_IRQ2 0x02000000 146 #define CX_RISC_IRQ1 0x01000000 147 #define CX_RISC_IMM 0x00000001 148 #define CX_RISC_SRP 0x00000001 149 150 #define CX_CNT_CTL_NOOP 0x0 151 #define CX_CNT_CTL_INCR 0x1 152 #define CX_CNT_CTL_ZERO 0x3 153 #define CX_RISC_CNT_CTL __BITS(17,16) 154 #define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP) 155 #define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR) 156 #define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO) 157 158 /* Channel Management Data Structure */ 159 /* offsets */ 160 #define CX_CMDS_O_IRPC 0x00 161 #define CX_CMDS_O_CDTB 0x04 162 #define CX_CMDS_O_CDTS 0x08 163 #define CX_CMDS_O_IQB 0x0c 164 #define CX_CMDS_O_IQS 0x10 165 166 /* bits */ 167 #define CX_CMDS_IQS_ISRP __BIT(31) 168 169 /* PCI subsystems products */ 170 #define PCI_SUBSYSTEM_ATI_HDTV_WONDER 0xa101 171 #define PCI_SUBSYSTEM_ATI_HDTV_WONDER_HP_Z556_MC 0xa103 172 173 #endif /* !_DEV_PCI_CXDTVREG_H */ 174
Indexes created Tue Sep 23 21:09:50 GMT 2025