if_bce.c revision 1.1
1 /* $NetBSD: if_bce.c,v 1.1 2003/09/27 13:13:28 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include <dev/mii/miidevs.h> 73 #include <dev/mii/brgphyreg.h> 74 75 #include <dev/pci/if_bcereg.h> 76 77 #include <uvm/uvm_extern.h> 78 79 static int bce_probe(struct device *, struct cfdata *, void *); 80 static void bce_attach(struct device *, struct device *, void *); 81 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 82 static void bce_start __P((struct ifnet *)); 83 static void bce_watchdog __P((struct ifnet *)); 84 static int bce_intr(void *); 85 static void bce_rxintr __P((struct bce_softc *)); 86 static void bce_txintr __P((struct bce_softc *)); 87 static int bce_init __P((struct ifnet *)); 88 static void bce_add_mac 89 __P((struct bce_softc *, unsigned char *, unsigned long)); 90 static int bce_add_rxbuf __P((struct bce_softc *, int)); 91 static void bce_rxdrain __P((struct bce_softc *)); 92 static void bce_stop __P((struct ifnet *, int)); 93 static void bce_reset __P((struct bce_softc *)); 94 static void bce_set_filter __P((struct ifnet *)); 95 static int bce_mii_read __P((struct device *, int, int)); 96 static void bce_mii_write __P((struct device *, int, int, int)); 97 static void bce_statchg __P((struct device *)); 98 static int bce_mediachange __P((struct ifnet *)); 99 static void bce_mediastatus __P((struct ifnet *, struct ifmediareq *)); 100 static void bce_tick __P((void *)); 101 102 #define BCE_DEBUG 103 #ifdef BCE_DEBUG 104 #define DPRINTF(x) if (bcedebug) printf x 105 #define DPRINTFN(n,x) if (bcedebug >= (n)) printf x 106 int bcedebug = 0; 107 #else 108 #define DPRINTF(x) 109 #define DPRINTFN(n,x) 110 #endif 111 112 /* for ring descriptors */ 113 #define BCE_RXBUF_LEN (MCLBYTES - 4) 114 #define BCE_INIT_RXDESC(sc, x) \ 115 do { \ 116 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 117 \ 118 *mtod(sc->bce_cdata.bce_rx_chain[x], long *) = 0; \ 119 __bced->addr = \ 120 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 121 + 0x40000000); \ 122 if (x != (BCE_NRXDESC - 1)) \ 123 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 124 else \ 125 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 126 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 127 sizeof(struct bce_dma_slot) * x, \ 128 sizeof(struct bce_dma_slot), \ 129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 130 } while(0) 131 132 #ifdef OLDNETBSD 133 struct cfattach bce_ca = { 134 sizeof(struct bce_softc), bce_probe, bce_attach 135 }; 136 #else 137 CFATTACH_DECL(bce, sizeof(struct bce_softc), 138 bce_probe, bce_attach, NULL, NULL); 139 #endif 140 141 static const struct bce_product { 142 pci_vendor_id_t bp_vendor; 143 pci_product_id_t bp_product; 144 const char *bp_name; 145 } bce_products[] = { 146 { 147 PCI_VENDOR_BROADCOM, 148 PCI_PRODUCT_BROADCOM_BCM4401, 149 "Broadcom BCM4401 10/100 Ethernet" 150 }, 151 { 152 0, 153 0, 154 NULL 155 }, 156 }; 157 158 static const struct bce_product * 159 bce_lookup(const struct pci_attach_args * pa) 160 { 161 const struct bce_product *bp; 162 163 for (bp = bce_products; bp->bp_name != NULL; bp++) { 164 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 165 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 166 return (bp); 167 } 168 169 return (NULL); 170 } 171 172 /* 173 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 174 * against drivers product list, and return its name if a match is found. 175 */ 176 int 177 bce_probe(parent, match, aux) 178 struct device *parent; 179 struct cfdata *match; 180 void *aux; 181 { 182 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 183 184 if (bce_lookup(pa) != NULL) 185 return (1); 186 187 return (0); 188 } 189 190 void 191 bce_attach(parent, self, aux) 192 struct device *parent, *self; 193 void *aux; 194 { 195 struct bce_softc *sc = (struct bce_softc *) self; 196 struct pci_attach_args *pa = aux; 197 const struct bce_product *bp; 198 pci_chipset_tag_t pc = pa->pa_pc; 199 pci_intr_handle_t ih; 200 const char *intrstr = NULL; 201 caddr_t kva; 202 bus_dma_segment_t seg; 203 int rseg; 204 u_int32_t command; 205 struct ifnet *ifp; 206 pcireg_t memtype; 207 bus_addr_t memaddr; 208 bus_size_t memsize; 209 int pmreg; 210 pcireg_t pmode; 211 int error; 212 int i; 213 214 bp = bce_lookup(pa); 215 KASSERT(bp != NULL); 216 217 sc->bce_pa = *pa; 218 sc->bce_dmatag = pa->pa_dmat; 219 220 printf(": %s\n", bp->bp_name); 221 /* 222 * following is for new aprint_naive(": Ethernet controller\n"); 223 * aprint_normal(": %s\n", bp->bp_name); 224 */ 225 226 /* 227 * Map control/status registers. 228 */ 229 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 230 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 231 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 232 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 234 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 235 printf("%s: failed to enable memory mapping!\n", 236 /* 237 * following line for new aprint_error("%s: failed to enable 238 * memory mapping!\n", 239 */ 240 sc->bce_dev.dv_xname); 241 return; 242 } 243 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 244 switch (memtype) { 245 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 246 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 247 if (pci_mapreg_map(pa, BCE_PCI_BAR0, 248 memtype, 0, &sc->bce_btag, &sc->bce_bhandle, 249 &memaddr, &memsize) == 0) 250 break; 251 default: 252 printf("%s: unable to find mem space\n", 253 /* 254 * following for new aprint_error("%s: unable to find mem 255 * space\n", 256 */ 257 sc->bce_dev.dv_xname); 258 return; 259 } 260 261 /* Get it out of power save mode if needed. */ 262 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 263 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 264 if (pmode == 3) { 265 /* 266 * The card has lost all configuration data in 267 * this state, so punt. 268 */ 269 printf("%s: unable to wake up from power state D3\n", 270 sc->bce_dev.dv_xname); 271 return; 272 } 273 if (pmode != 0) { 274 printf("%s: waking up from power state D%d\n", 275 sc->bce_dev.dv_xname, pmode); 276 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 277 } 278 } 279 if (pci_intr_map(pa, &ih)) { 280 printf("%s: couldn't map interrupt\n", 281 /* 282 * following for new aprint_error("%s: couldn't map 283 * interrupt\n", 284 */ 285 sc->bce_dev.dv_xname); 286 return; 287 } 288 intrstr = pci_intr_string(pc, ih); 289 290 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 291 292 if (sc->bce_intrhand == NULL) { 293 printf("%s: couldn't establish interrupt", 294 /* 295 * following for new aprint_error("%s: couldn't establish 296 * interrupt", 297 */ 298 sc->bce_dev.dv_xname); 299 if (intrstr != NULL) 300 printf(" at %s", intrstr); 301 /* 302 * following for new aprint_normal(" at %s", intrstr); 303 */ 304 printf("\n"); 305 /* 306 * following for new aprint_normal("\n"); 307 */ 308 return; 309 } 310 printf("%s: interrupting at %s\n", 311 /* 312 * following for new aprint_normal("%s: interrupting at %s\n", 313 */ 314 sc->bce_dev.dv_xname, intrstr); 315 316 /* reset the chip */ 317 bce_reset(sc); 318 319 /* 320 * Allocate DMA-safe memory for ring descriptors. 321 * The receive, and transmit rings can not share the same 322 * 4k space, however both are allocated at once here. 323 */ 324 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 325 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 326 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 327 printf("%s: unable to alloc space for ring descriptors, " 328 "error = %d\n", sc->bce_dev.dv_xname, error); 329 return; 330 } 331 /* map ring space to kernel */ 332 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 333 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 334 printf("%s: unable to map DMA buffers, error = %d\n", 335 sc->bce_dev.dv_xname, error); 336 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 337 return; 338 } 339 /* create a dma map for the ring */ 340 if ((error = bus_dmamap_create(sc->bce_dmatag, 341 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 342 &sc->bce_ring_map))) { 343 printf("%s: unable to create ring DMA map, error = %d\n", 344 sc->bce_dev.dv_xname, error); 345 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 346 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 347 return; 348 } 349 /* connect the ring space to the dma map */ 350 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 351 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 352 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 353 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 354 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 355 return; 356 } 357 /* save the ring space in softc */ 358 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 359 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 360 361 /* Create the transmit buffer DMA maps. */ 362 for (i = 0; i < BCE_NTXDESC; i++) { 363 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 364 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 365 printf("%s: unable to create tx DMA map, error = %d\n", 366 sc->bce_dev.dv_xname, error); 367 } 368 sc->bce_cdata.bce_tx_chain[i] = NULL; 369 } 370 371 /* Create the receive buffer DMA maps. */ 372 for (i = 0; i < BCE_NRXDESC; i++) { 373 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 374 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 375 printf("%s: unable to create rx DMA map, error = %d\n", 376 sc->bce_dev.dv_xname, error); 377 } 378 sc->bce_cdata.bce_rx_chain[i] = NULL; 379 } 380 381 /* Set up ifnet structure */ 382 ifp = &sc->ethercom.ec_if; 383 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = bce_ioctl; 387 ifp->if_start = bce_start; 388 ifp->if_watchdog = bce_watchdog; 389 ifp->if_init = bce_init; 390 ifp->if_stop = bce_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 /* Initialize our media structures and probe the MII. */ 394 395 sc->bce_mii.mii_ifp = ifp; 396 sc->bce_mii.mii_readreg = bce_mii_read; 397 sc->bce_mii.mii_writereg = bce_mii_write; 398 sc->bce_mii.mii_statchg = bce_statchg; 399 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 400 bce_mediastatus); 401 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 402 MII_OFFSET_ANY, 0); 403 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 404 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 405 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 406 } else 407 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 408 /* get the phy */ 409 sc->bce_phy = 410 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 90) & 0x1f; 411 /* 412 * Enable activity led. 413 * XXX This should be in a phy driver, but not currently. 414 */ 415 bce_mii_write((struct device *) sc, 1, 26, 416 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); 417 /* enable traffic meter led mode */ 418 bce_mii_write((struct device *) sc, 1, 26, 419 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); 420 421 422 /* Attach the interface */ 423 if_attach(ifp); 424 sc->enaddr[0] = 425 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 79); 426 sc->enaddr[1] = 427 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 78); 428 sc->enaddr[2] = 429 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 81); 430 sc->enaddr[3] = 431 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 80); 432 sc->enaddr[4] = 433 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 83); 434 sc->enaddr[5] = 435 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 4096 + 82); 436 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 437 ether_sprintf(sc->enaddr)); 438 ether_ifattach(ifp, sc->enaddr); 439 callout_init(&sc->bce_timeout); 440 } 441 442 /* handle media, and ethernet requests */ 443 static int 444 bce_ioctl(ifp, cmd, data) 445 struct ifnet *ifp; 446 u_long cmd; 447 caddr_t data; 448 { 449 struct bce_softc *sc = ifp->if_softc; 450 struct ifreq *ifr = (struct ifreq *) data; 451 int s, error; 452 453 s = splnet(); 454 switch (cmd) { 455 case SIOCSIFMEDIA: 456 case SIOCGIFMEDIA: 457 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 458 break; 459 default: 460 error = ether_ioctl(ifp, cmd, data); 461 if (error == ENETRESET) { 462 /* change multicast list */ 463 error = 0; 464 } 465 break; 466 } 467 468 /* Try to get more packets going. */ 469 bce_start(ifp); 470 471 splx(s); 472 return error; 473 } 474 475 /* Start packet transmission on the interface. */ 476 static void 477 bce_start(ifp) 478 struct ifnet *ifp; 479 { 480 struct bce_softc *sc = ifp->if_softc; 481 struct mbuf *m0; 482 bus_dmamap_t dmamap; 483 int txstart; 484 int txsfree; 485 int newpkts = 0; 486 int error; 487 488 /* 489 * do not start another if currently transmitting, and more 490 * descriptors(tx slots) are needed for next packet. 491 */ 492 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 493 return; 494 495 /* determine number of descriptors available */ 496 if (sc->bce_txsnext >= sc->bce_txin) 497 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 498 else 499 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 500 501 /* 502 * Loop through the send queue, setting up transmit descriptors 503 * until we drain the queue, or use up all available transmit 504 * descriptors. 505 */ 506 while (txsfree > 0) { 507 int seg; 508 509 /* Grab a packet off the queue. */ 510 IFQ_POLL(&ifp->if_snd, m0); 511 if (m0 == NULL) 512 break; 513 514 /* get the transmit slot dma map */ 515 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 516 517 /* 518 * Load the DMA map. If this fails, the packet either 519 * didn't fit in the alloted number of segments, or we 520 * were short on resources. If the packet will not fit, 521 * it will be dropped. If short on resources, it will 522 * be tried again later. 523 */ 524 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 525 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 526 if (error == EFBIG) { 527 printf("%s: Tx packet consumes too many " 528 "DMA segments, dropping...\n", sc->bce_dev.dv_xname); 529 IFQ_DEQUEUE(&ifp->if_snd, m0); 530 m_freem(m0); 531 ifp->if_oerrors++; 532 continue; 533 } else if (error) { 534 /* short on resources, come back later */ 535 printf("%s: unable to load Tx buffer, " 536 "error = %d\n", sc->bce_dev.dv_xname, error); 537 break; 538 } 539 /* If not enough descriptors available, try again later */ 540 if (dmamap->dm_nsegs > txsfree) { 541 ifp->if_flags |= IFF_OACTIVE; 542 bus_dmamap_unload(sc->bce_dmatag, dmamap); 543 break; 544 } 545 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 546 547 /* So take it off the queue */ 548 IFQ_DEQUEUE(&ifp->if_snd, m0); 549 550 /* save the pointer so it can be freed later */ 551 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 552 553 /* Sync the data DMA map. */ 554 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 555 BUS_DMASYNC_PREWRITE); 556 557 /* Initialize the transmit descriptor(s). */ 558 txstart = sc->bce_txsnext; 559 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 560 unsigned long ctrl; 561 562 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 563 if (seg == 0) 564 ctrl |= CTRL_SOF; 565 if (seg == dmamap->dm_nsegs - 1) 566 ctrl |= CTRL_EOF; 567 if (sc->bce_txsnext == BCE_NTXDESC - 1) 568 ctrl |= CTRL_EOT; 569 ctrl |= CTRL_IOC; 570 sc->bce_tx_ring[sc->bce_txsnext].ctrl = ctrl; 571 sc->bce_tx_ring[sc->bce_txsnext].addr = 572 dmamap->dm_segs[seg].ds_addr + 0x40000000; 573 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 574 sc->bce_txsnext = 0; 575 else 576 sc->bce_txsnext++; 577 txsfree--; 578 } 579 /* sync descriptors being used */ 580 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 581 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 582 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 583 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 584 585 /* Give the packet to the chip. */ 586 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 587 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 588 589 newpkts++; 590 591 #if NBPFILTER > 0 592 /* Pass the packet to any BPF listeners. */ 593 if (ifp->if_bpf) 594 bpf_mtap(ifp->if_bpf, m0); 595 #endif /* NBPFILTER > 0 */ 596 } 597 if (txsfree == 0) { 598 /* No more slots left; notify upper layer. */ 599 ifp->if_flags |= IFF_OACTIVE; 600 } 601 if (newpkts) { 602 /* Set a watchdog timer in case the chip flakes out. */ 603 ifp->if_timer = 5; 604 } 605 } 606 607 /* Watchdog timer handler. */ 608 static void 609 bce_watchdog(ifp) 610 struct ifnet *ifp; 611 { 612 struct bce_softc *sc = ifp->if_softc; 613 614 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 615 ifp->if_oerrors++; 616 617 (void) bce_init(ifp); 618 619 /* Try to get more packets going. */ 620 bce_start(ifp); 621 } 622 623 int 624 bce_intr(xsc) 625 void *xsc; 626 { 627 struct bce_softc *sc; 628 struct ifnet *ifp; 629 unsigned long intstatus; 630 unsigned long intmask; 631 int wantinit; 632 int handled = 0; 633 634 sc = xsc; 635 ifp = &sc->ethercom.ec_if; 636 637 638 for (wantinit = 0; wantinit == 0;) { 639 intstatus = 640 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS); 641 intmask = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK); 642 643 /* ignore if not ours, or unsolicited interrupts */ 644 intstatus &= intmask; 645 if (intstatus == 0) 646 break; 647 648 handled = 1; 649 650 /* Ack interrupt */ 651 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 652 intstatus); 653 654 /* Receive interrupts. */ 655 if (intstatus & I_RI) { 656 bce_rxintr(sc); 657 } 658 /* Transmit interrupts. */ 659 if (intstatus & I_XI) { 660 bce_txintr(sc); 661 } 662 /* Error interrupts */ 663 if (intstatus & ~(I_RI | I_XI)) { 664 if (intstatus & I_XU) 665 printf("%s: transmit fifo underflow\n", sc->bce_dev.dv_xname); 666 if (intstatus & I_RO) { 667 printf("%s: receive fifo overflow\n", sc->bce_dev.dv_xname); 668 ifp->if_ierrors++; 669 } 670 if (intstatus & I_RU) 671 printf("%s: receive descriptor underflow\n", 672 sc->bce_dev.dv_xname); 673 if (intstatus & I_DE) 674 printf("%s: descriptor protocol error\n", 675 sc->bce_dev.dv_xname); 676 if (intstatus & I_PD) 677 printf("%s: data error\n", sc->bce_dev.dv_xname); 678 if (intstatus & I_PC) 679 printf("%s: descriptor error\n", sc->bce_dev.dv_xname); 680 if (intstatus & I_TO) 681 printf("%s: general purpose timeout\n", sc->bce_dev.dv_xname); 682 wantinit = 1; 683 } 684 } 685 686 if (handled) { 687 if (wantinit) 688 bce_init(ifp); 689 /* Try to get more packets going. */ 690 bce_start(ifp); 691 } 692 return (handled); 693 } 694 695 /* Receive interrupt handler */ 696 void 697 bce_rxintr(sc) 698 struct bce_softc *sc; 699 { 700 struct ifnet *ifp = &sc->ethercom.ec_if; 701 struct rx_pph *pph; 702 struct mbuf *m; 703 int curr; 704 int len; 705 int i; 706 707 /* get pointer to active receive slot */ 708 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 709 & RS_CD_MASK; 710 curr = curr / sizeof(struct bce_dma_slot); 711 if (curr >= BCE_NRXDESC) 712 curr = BCE_NRXDESC - 1; 713 714 /* process packets up to but not current packet being worked on */ 715 for (i = sc->bce_rxin; i != curr; i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 716 717 /* complete any post dma memory ops on packet */ 718 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 719 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 720 721 /* 722 * If the packet had an error, simply recycle the buffer, 723 * resetting the len, and flags. 724 */ 725 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 726 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 727 ifp->if_ierrors++; 728 pph->len = 0; 729 pph->flags = 0; 730 continue; 731 } 732 /* receive the packet */ 733 len = pph->len; 734 if (len == 0) 735 continue; /* no packet if empty */ 736 pph->len = 0; 737 pph->flags = 0; 738 /* bump past pre header to packet */ 739 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; 740 741 /* 742 * If the packet is small enough to fit in a 743 * single header mbuf, allocate one and copy 744 * the data into it. This greatly reduces 745 * memory consumption when receiving lots 746 * of small packets. 747 * 748 * Otherwise, add a new buffer to the receive 749 * chain. If this fails, drop the packet and 750 * recycle the old buffer. 751 */ 752 if (len <= (MHLEN - 2)) { 753 MGETHDR(m, M_DONTWAIT, MT_DATA); 754 if (m == NULL) 755 goto dropit; 756 m->m_data += 2; 757 memcpy(mtod(m, caddr_t), 758 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 759 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 760 } else { 761 m = sc->bce_cdata.bce_rx_chain[i]; 762 if (bce_add_rxbuf(sc, i) != 0) { 763 dropit: 764 ifp->if_ierrors++; 765 /* continue to use old buffer */ 766 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 767 bus_dmamap_sync(sc->bce_dmatag, 768 sc->bce_cdata.bce_rx_map[i], 0, 769 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 770 BUS_DMASYNC_PREREAD); 771 continue; 772 } 773 } 774 775 m->m_flags |= M_HASFCS; 776 m->m_pkthdr.rcvif = ifp; 777 m->m_pkthdr.len = m->m_len = len; 778 ifp->if_ipackets++; 779 780 #if NBPFILTER > 0 781 /* 782 * Pass this up to any BPF listeners, but only 783 * pass it up the stack if it's for us. 784 */ 785 if (ifp->if_bpf) 786 bpf_mtap(ifp->if_bpf, m); 787 #endif /* NBPFILTER > 0 */ 788 789 /* Pass it on. */ 790 (*ifp->if_input) (ifp, m); 791 792 /* re-check current in case it changed */ 793 curr = 794 (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) & 795 RS_CD_MASK) / sizeof(struct bce_dma_slot); 796 if (curr >= BCE_NRXDESC) 797 curr = BCE_NRXDESC - 1; 798 } 799 sc->bce_rxin = curr; 800 } 801 802 /* Transmit interrupt handler */ 803 void 804 bce_txintr(sc) 805 struct bce_softc *sc; 806 { 807 struct ifnet *ifp = &sc->ethercom.ec_if; 808 int curr; 809 int i; 810 811 ifp->if_flags &= ~IFF_OACTIVE; 812 813 /* 814 * Go through the Tx list and free mbufs for those 815 * frames which have been transmitted. 816 */ 817 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 818 RS_CD_MASK; 819 curr = curr / sizeof(struct bce_dma_slot); 820 if (curr >= BCE_NTXDESC) 821 curr = BCE_NTXDESC - 1; 822 for (i = sc->bce_txin; i != curr; i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 823 824 /* do any post dma memory ops on transmit data */ 825 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 826 continue; 827 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 828 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE); 829 bus_dmamap_unload(sc->bce_dmatag, 830 sc->bce_cdata.bce_tx_map[i]); 831 m_freem(sc->bce_cdata.bce_tx_chain[i]); 832 sc->bce_cdata.bce_tx_chain[i] = NULL; 833 ifp->if_opackets++; 834 } 835 sc->bce_txin = curr; 836 837 /* 838 * If there are no more pending transmissions, cancel the watchdog 839 * timer 840 */ 841 if (sc->bce_txsnext == sc->bce_txin) 842 ifp->if_timer = 0; 843 } 844 845 /* initialize the interface */ 846 static int 847 bce_init(ifp) 848 struct ifnet *ifp; 849 { 850 struct bce_softc *sc = ifp->if_softc; 851 unsigned long reg_win; 852 int error; 853 int i; 854 855 /* Cancel any pending I/O. */ 856 bce_stop(ifp, 0); 857 858 /* enable pci inerrupts, bursts, and prefetch */ 859 860 /* remap the pci registers to the Sonics config registers */ 861 862 /* save the current map, so it can be restored */ 863 reg_win = 864 pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN); 865 /* set register window to Sonics registers */ 866 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 867 BCE_SONICS_WIN); 868 869 /* enable SB to PCI interrupt */ 870 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 871 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 872 SBIV_ENET0); 873 874 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 875 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 876 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 877 SBTOPCI_PREF | SBTOPCI_BURST); 878 879 /* restore to ethernet register space */ 880 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 881 reg_win); 882 883 /* Reset the chip to a known state. */ 884 bce_reset(sc); 885 886 /* Initialize transmit descriptors */ 887 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 888 sc->bce_txsnext = 0; 889 sc->bce_txin = 0; 890 891 /* enable crc32 generation */ 892 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 893 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | BCE_EMC_CG); 894 895 /* setup DMA interrupt control */ 896 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); 897 898 /* setup packet filter */ 899 bce_set_filter(ifp); 900 901 /* set max frame length, account for possible vlan tag */ 902 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 903 ETHER_MAX_LEN + 32); 904 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 905 ETHER_MAX_LEN + 32); 906 907 /* set tx watermark */ 908 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 909 910 /* enable transmit */ 911 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 912 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 913 htole32(sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000)); 914 915 /* 916 * Give the receive ring to the chip, and 917 * start the receive DMA engine. 918 */ 919 sc->bce_rxin = 0; 920 921 /* clear the rx descriptor ring */ 922 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 923 /* enable receive */ 924 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 925 30 << 1 | 1); 926 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 927 htole32(sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000)); 928 929 /* Initalize receive descriptors */ 930 for (i = 0; i < BCE_NRXDESC; i++) { 931 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 932 if ((error = bce_add_rxbuf(sc, i)) != 0) { 933 printf("%s: unable to allocate or map rx(%d) mbuf, error = %d\n" 934 ,sc->bce_dev.dv_xname, i, error); 935 bce_rxdrain(sc); 936 return (error); 937 } 938 } else 939 BCE_INIT_RXDESC(sc, i); 940 } 941 942 /* Enable interrupts */ 943 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 944 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO); 945 946 /* start the receive dma */ 947 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 948 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 949 950 /* set media */ 951 mii_mediachg(&sc->bce_mii); 952 953 /* turn on the ethernet mac */ 954 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 955 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL) | EC_EE); 956 957 /* start timer */ 958 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 959 960 /* mark as running, and no outputs active */ 961 ifp->if_flags |= IFF_RUNNING; 962 ifp->if_flags &= ~IFF_OACTIVE; 963 964 return 0; 965 } 966 967 /* add a mac address to packet filter */ 968 void 969 bce_add_mac(sc, mac, idx) 970 struct bce_softc *sc; 971 unsigned char *mac; 972 unsigned long idx; 973 { 974 int i; 975 unsigned long rval; 976 977 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 978 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 979 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 980 mac[0] << 8 | mac[1] | 0x10000); 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 982 idx << 16 | 8); 983 /* wait for write to complete */ 984 for (i = 0; i < 100; i++) { 985 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL); 986 if (!(rval & 0x80000000)) 987 break; 988 delay(10); 989 } 990 if (i == 100) { 991 printf("%s: timed out writting pkt filter ctl\n", sc->bce_dev.dv_xname); 992 } 993 } 994 995 /* Add a receive buffer to the indiciated descriptor. */ 996 static int 997 bce_add_rxbuf(sc, idx) 998 struct bce_softc *sc; 999 int idx; 1000 { 1001 struct mbuf *m; 1002 int error; 1003 1004 MGETHDR(m, M_DONTWAIT, MT_DATA); 1005 if (m == NULL) 1006 return (ENOBUFS); 1007 1008 MCLGET(m, M_DONTWAIT); 1009 if ((m->m_flags & M_EXT) == 0) { 1010 m_freem(m); 1011 return (ENOBUFS); 1012 } 1013 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1014 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx]); 1015 1016 sc->bce_cdata.bce_rx_chain[idx] = m; 1017 1018 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1019 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 1020 if (error) 1021 return (error); 1022 1023 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1024 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1025 1026 BCE_INIT_RXDESC(sc, idx); 1027 1028 return (0); 1029 1030 } 1031 1032 /* Drain the receive queue. */ 1033 static void 1034 bce_rxdrain(sc) 1035 struct bce_softc *sc; 1036 { 1037 int i; 1038 1039 for (i = 0; i < BCE_NRXDESC; i++) { 1040 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1041 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i]); 1042 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1043 sc->bce_cdata.bce_rx_chain[i] = NULL; 1044 } 1045 } 1046 } 1047 1048 /* Stop transmission on the interface */ 1049 static void 1050 bce_stop(ifp, disable) 1051 struct ifnet *ifp; 1052 int disable; 1053 { 1054 struct bce_softc *sc = ifp->if_softc; 1055 int i; 1056 unsigned long val; 1057 1058 /* Stop the 1 second timer */ 1059 callout_stop(&sc->bce_timeout); 1060 1061 /* Down the MII. */ 1062 mii_down(&sc->bce_mii); 1063 1064 /* Disable interrupts. */ 1065 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1066 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK); 1067 1068 /* Disable emac */ 1069 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1070 for (i = 0; i < 200; i++) { 1071 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL); 1072 if (!(val & EC_ED)) 1073 break; 1074 delay(10); 1075 } 1076 1077 /* Stop the DMA */ 1078 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1079 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1080 delay(10); 1081 1082 /* Release any queued transmit buffers. */ 1083 for (i = 0; i < BCE_NTXDESC; i++) { 1084 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1085 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 1086 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1087 sc->bce_cdata.bce_tx_chain[i] = NULL; 1088 } 1089 } 1090 1091 /* drain receive queue */ 1092 if (disable) 1093 bce_rxdrain(sc); 1094 1095 /* Mark the interface down and cancel the watchdog timer. */ 1096 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1097 ifp->if_timer = 0; 1098 1099 } 1100 1101 /* reset the chip */ 1102 static void 1103 bce_reset(sc) 1104 struct bce_softc *sc; 1105 { 1106 unsigned long val; 1107 unsigned long sbval; 1108 int i; 1109 1110 /* if SB core is up */ 1111 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1112 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1113 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 0); 1114 1115 /* disable emac */ 1116 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1117 for (i = 0; i < 200; i++) { 1118 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL); 1119 if (!(val & EC_ED)) 1120 break; 1121 delay(10); 1122 } 1123 if (i == 200) 1124 printf("%s: timed out disabling ethernet mac\n", 1125 sc->bce_dev.dv_xname); 1126 1127 /* reset the dma engines */ 1128 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1129 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1130 /* if error on receive, wait to go idle */ 1131 if (val & 0xf0000) { 1132 for (i = 0; i < 100; i++) { 1133 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1134 BCE_DMA_RXSTATUS); 1135 if (val & 0x2000) 1136 break; 1137 delay(10); 1138 } 1139 if (i == 100) 1140 printf("%s: receive dma did not go idle after error\n", 1141 sc->bce_dev.dv_xname); 1142 } 1143 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS, 0); 1144 1145 /* reset ethernet mac */ 1146 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ES); 1147 for (i = 0; i < 200; i++) { 1148 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL); 1149 if (!(val & EC_ES)) 1150 break; 1151 delay(10); 1152 } 1153 if (i == 200) 1154 printf("%s: timed out restting ethernet mac\n", 1155 sc->bce_dev.dv_xname); 1156 } else { 1157 unsigned long reg_win; 1158 1159 /* remap the pci registers to the Sonics config registers */ 1160 1161 /* save the current map, so it can be restored */ 1162 reg_win = 1163 pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN); 1164 /* set register window to Sonics registers */ 1165 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1166 BCE_SONICS_WIN); 1167 1168 /* enable SB to PCI interrupt */ 1169 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1170 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 1171 SBIV_ENET0); 1172 1173 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1174 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1175 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 1176 SBTOPCI_PREF | SBTOPCI_BURST); 1177 1178 /* restore to ethernet register space */ 1179 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1180 reg_win); 1181 } 1182 1183 /* disable SB core if not in reset */ 1184 if (!(sbval & SBTML_RESET)) { 1185 1186 /* set the reject bit */ 1187 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1188 SBTML_REJ | SBTML_CLK); 1189 for (i = 0; i < 200; i++) { 1190 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1191 BCE_SBTMSTATELOW); 1192 if (val & SBTML_REJ) 1193 break; 1194 delay(1); 1195 } 1196 if (val == 200) 1197 printf("%s: while restting core, reject did not set\n", 1198 sc->bce_dev.dv_xname); 1199 /* wait until busy is clear */ 1200 for (i = 0; i < 200; i++) { 1201 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1202 BCE_SBTMSTATEHI); 1203 if (!(val & 0x4)) 1204 break; 1205 delay(1); 1206 } 1207 if (i == 200) 1208 printf("%s: while restting core, busy did not clear\n", 1209 sc->bce_dev.dv_xname); 1210 /* set reset and reject while enabling the clocks */ 1211 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1212 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1213 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1214 delay(10); 1215 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1216 SBTML_REJ | SBTML_RESET); 1217 delay(1); 1218 } 1219 /* enable clock */ 1220 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1221 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1222 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1223 delay(1); 1224 1225 /* clear any error bits that may be on */ 1226 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1227 if (val & 1) 1228 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1229 0); 1230 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1231 if (val & 0x60000) 1232 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1233 val & ~0x60000); 1234 1235 /* clear reset and allow it to propagate throughout the core */ 1236 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1237 SBTML_FGC | SBTML_CLK); 1238 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1239 delay(1); 1240 1241 /* leave clock enabled */ 1242 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1243 SBTML_CLK); 1244 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1245 delay(1); 1246 1247 /* initialize MDC preamble, frequency */ 1248 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); 1249 1250 /* enable phy, differs for internal, and external */ 1251 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1252 if (!(val & BCE_DC_IP)) { 1253 /* select external phy */ 1254 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1255 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1256 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1257 val & ~BCE_DC_ER); 1258 delay(100); 1259 } 1260 } 1261 1262 /* Set up the receive filter. */ 1263 void 1264 bce_set_filter(ifp) 1265 struct ifnet *ifp; 1266 { 1267 struct bce_softc *sc = ifp->if_softc; 1268 1269 if (ifp->if_flags & IFF_PROMISC) { 1270 ifp->if_flags |= IFF_ALLMULTI; 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1272 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | ERC_PE); 1273 } else { 1274 ifp->if_flags &= ~IFF_ALLMULTI; 1275 1276 /* turn off promiscuous */ 1277 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1278 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) & 1279 ~ERC_PE); 1280 1281 /* enable/disable broadcast */ 1282 if (ifp->if_flags & IFF_BROADCAST) 1283 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1284 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) & 1285 ~ERC_DB); 1286 else 1287 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1288 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1289 ERC_DB); 1290 1291 /* disable the filter */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 0); 1293 1294 /* add our own address */ 1295 bce_add_mac(sc, sc->enaddr, 0); 1296 1297 /* for now accept all multicast */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1299 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1300 ERC_AM); 1301 ifp->if_flags |= IFF_ALLMULTI; 1302 1303 /* enable the filter */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1305 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL) | 1); 1306 } 1307 } 1308 1309 /* Read a PHY register on the MII. */ 1310 int 1311 bce_mii_read(self, phy, reg) 1312 struct device *self; 1313 int phy, reg; 1314 { 1315 struct bce_softc *sc = (struct bce_softc *) self; 1316 int i; 1317 unsigned long val; 1318 1319 /* clear mii_int */ 1320 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1321 1322 /* Read the PHY register */ 1323 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1324 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | (MII_COMMAND_ACK << 16) 1325 | BCE_MIPHY(phy) | BCE_MIREG(reg)); 1326 1327 for (i = 0; i < BCE_TIMEOUT; i++) { 1328 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1329 if (val & BCE_MIINTR) 1330 break; 1331 delay(10); 1332 } 1333 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1334 if (i == BCE_TIMEOUT) { 1335 printf("%s: PHY read timed out reading phy %d, reg %d, val = 0x%08lx\n" 1336 ,sc->bce_dev.dv_xname, phy, reg, val); 1337 return (0); 1338 } 1339 return (val & BCE_MICOMM_DATA); 1340 } 1341 1342 /* Write a PHY register on the MII */ 1343 void 1344 bce_mii_write(self, phy, reg, val) 1345 struct device *self; 1346 int phy, reg, val; 1347 { 1348 struct bce_softc *sc = (struct bce_softc *) self; 1349 int i; 1350 unsigned long rval; 1351 1352 /* clear mii_int */ 1353 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1354 1355 /* Write the PHY register */ 1356 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1357 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | (MII_COMMAND_ACK << 16) 1358 | (val & BCE_MICOMM_DATA) 1359 | BCE_MIPHY(phy) | BCE_MIREG(reg)); 1360 1361 /* wait for write to complete */ 1362 for (i = 0; i < BCE_TIMEOUT; i++) { 1363 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1364 if (rval & BCE_MIINTR) 1365 break; 1366 delay(10); 1367 } 1368 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1369 if (i == BCE_TIMEOUT) { 1370 printf("%s: PHY timed out writting phy %d, reg %d, val = 0x%08x\n" 1371 ,sc->bce_dev.dv_xname, phy, reg, val); 1372 } 1373 } 1374 1375 /* sync hardware duplex mode to software state */ 1376 void 1377 bce_statchg(self) 1378 struct device *self; 1379 { 1380 struct bce_softc *sc = (struct bce_softc *) self; 1381 unsigned long reg; 1382 1383 /* if needed, change register to match duplex mode */ 1384 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1385 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1386 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1387 reg | EXC_FD); 1388 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1389 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1390 reg & ~EXC_FD); 1391 1392 /* 1393 * Enable activity led. 1394 * XXX This should be in a phy driver, but not currently. 1395 */ 1396 bce_mii_write((struct device *) sc, 1, 26, 1397 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); 1398 /* enable traffic meter led mode */ 1399 bce_mii_write((struct device *) sc, 1, 26, 1400 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); 1401 } 1402 1403 /* Set hardware to newly-selected media */ 1404 int 1405 bce_mediachange(ifp) 1406 struct ifnet *ifp; 1407 { 1408 struct bce_softc *sc = ifp->if_softc; 1409 1410 if (ifp->if_flags & IFF_UP) 1411 mii_mediachg(&sc->bce_mii); 1412 return (0); 1413 } 1414 1415 /* Get the current interface media status */ 1416 static void 1417 bce_mediastatus(ifp, ifmr) 1418 struct ifnet *ifp; 1419 struct ifmediareq *ifmr; 1420 { 1421 struct bce_softc *sc = ifp->if_softc; 1422 1423 mii_pollstat(&sc->bce_mii); 1424 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1425 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1426 } 1427 1428 /* One second timer, checks link status */ 1429 static void 1430 bce_tick(v) 1431 void *v; 1432 { 1433 struct bce_softc *sc = v; 1434 1435 /* Tick the MII. */ 1436 mii_tick(&sc->bce_mii); 1437 1438 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1439 } 1440
Indexes created Tue Sep 30 20:09:53 GMT 2025