if_bce.c revision 1.12
1 /* $NetBSD: if_bce.c,v 1.12 2006/11/16 01:33:08 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/miidevs.h> 66 #include <dev/mii/brgphyreg.h> 67 68 #include <dev/pci/if_bcereg.h> 69 70 #include <uvm/uvm_extern.h> 71 72 /* transmit buffer max frags allowed */ 73 #define BCE_NTXFRAGS 16 74 75 /* ring descriptor */ 76 struct bce_dma_slot { 77 u_int32_t ctrl; 78 u_int32_t addr; 79 }; 80 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 81 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 82 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 83 #define CTRL_EOF 0x40000000 /* end of frame */ 84 #define CTRL_SOF 0x80000000 /* start of frame */ 85 86 /* Packet status is returned in a pre-packet header */ 87 struct rx_pph { 88 u_int16_t len; 89 u_int16_t flags; 90 u_int16_t pad[12]; 91 }; 92 93 /* packet status flags bits */ 94 #define RXF_NO 0x8 /* odd number of nibbles */ 95 #define RXF_RXER 0x4 /* receive symbol error */ 96 #define RXF_CRC 0x2 /* crc error */ 97 #define RXF_OV 0x1 /* fifo overflow */ 98 99 /* number of descriptors used in a ring */ 100 #define BCE_NRXDESC 128 101 #define BCE_NTXDESC 128 102 103 /* 104 * Mbuf pointers. We need these to keep track of the virtual addresses 105 * of our mbuf chains since we can only convert from physical to virtual, 106 * not the other way around. 107 */ 108 struct bce_chain_data { 109 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 110 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 111 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 112 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 113 }; 114 115 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 116 117 struct bce_softc { 118 struct device bce_dev; 119 bus_space_tag_t bce_btag; 120 bus_space_handle_t bce_bhandle; 121 bus_dma_tag_t bce_dmatag; 122 struct ethercom ethercom; /* interface info */ 123 void *bce_intrhand; 124 struct pci_attach_args bce_pa; 125 struct mii_data bce_mii; 126 u_int32_t bce_phy; /* eeprom indicated phy */ 127 struct ifmedia bce_ifmedia; /* media info *//* Check */ 128 u_int8_t enaddr[ETHER_ADDR_LEN]; 129 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 130 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 131 struct bce_chain_data bce_cdata; /* mbufs */ 132 bus_dmamap_t bce_ring_map; 133 u_int32_t bce_intmask; /* current intr mask */ 134 u_int32_t bce_rxin; /* last rx descriptor seen */ 135 u_int32_t bce_txin; /* last tx descriptor seen */ 136 int bce_txsfree; /* no. tx slots available */ 137 int bce_txsnext; /* next available tx slot */ 138 struct callout bce_timeout; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(struct device *, struct cfdata *, void *); 162 static void bce_attach(struct device *, struct device *, void *); 163 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static void bce_set_filter(struct ifnet *); 176 static int bce_mii_read(struct device *, int, int); 177 static void bce_mii_write(struct device *, int, int, int); 178 static void bce_statchg(struct device *); 179 static int bce_mediachange(struct ifnet *); 180 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 181 static void bce_tick(void *); 182 183 #define BCE_DEBUG 184 #ifdef BCE_DEBUG 185 #define DPRINTF(x) do { \ 186 if (bcedebug) \ 187 printf x; \ 188 } while (/* CONSTCOND */ 0) 189 #define DPRINTFN(n,x) do { \ 190 if (bcedebug >= (n)) \ 191 printf x; \ 192 } while (/* CONSTCOND */ 0) 193 int bcedebug = 0; 194 #else 195 #define DPRINTF(x) 196 #define DPRINTFN(n,x) 197 #endif 198 199 #if __NetBSD_Version__ >= 106080000 200 CFATTACH_DECL(bce, sizeof(struct bce_softc), 201 bce_probe, bce_attach, NULL, NULL); 202 #else 203 struct cfattach bce_ca = { 204 sizeof(struct bce_softc), bce_probe, bce_attach 205 }; 206 #endif 207 208 #if __NetBSD_Version__ >= 106120000 209 #define APRINT_ERROR aprint_error 210 #define APRINT_NORMAL aprint_normal 211 #else 212 #define APRINT_ERROR printf 213 #define APRINT_NORMAL printf 214 #endif 215 216 217 static const struct bce_product { 218 pci_vendor_id_t bp_vendor; 219 pci_product_id_t bp_product; 220 const char *bp_name; 221 } bce_products[] = { 222 { 223 PCI_VENDOR_BROADCOM, 224 PCI_PRODUCT_BROADCOM_BCM4401, 225 "Broadcom BCM4401 10/100 Ethernet" 226 }, 227 { 228 PCI_VENDOR_BROADCOM, 229 PCI_PRODUCT_BROADCOM_BCM4401_B0, 230 "Broadcom BCM4401-B0 10/100 Ethernet" 231 }, 232 { 233 234 0, 235 0, 236 NULL 237 }, 238 }; 239 240 static const struct bce_product * 241 bce_lookup(const struct pci_attach_args * pa) 242 { 243 const struct bce_product *bp; 244 245 for (bp = bce_products; bp->bp_name != NULL; bp++) { 246 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 247 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 248 return (bp); 249 } 250 251 return (NULL); 252 } 253 254 /* 255 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 256 * against drivers product list, and return its name if a match is found. 257 */ 258 static int 259 bce_probe(struct device *parent, struct cfdata *match, 260 void *aux) 261 { 262 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 263 264 if (bce_lookup(pa) != NULL) 265 return (1); 266 267 return (0); 268 } 269 270 static void 271 bce_attach(struct device *parent, struct device *self, void *aux) 272 { 273 struct bce_softc *sc = (struct bce_softc *) self; 274 struct pci_attach_args *pa = aux; 275 const struct bce_product *bp; 276 pci_chipset_tag_t pc = pa->pa_pc; 277 pci_intr_handle_t ih; 278 const char *intrstr = NULL; 279 caddr_t kva; 280 bus_dma_segment_t seg; 281 int rseg; 282 u_int32_t command; 283 struct ifnet *ifp; 284 pcireg_t memtype; 285 bus_addr_t memaddr; 286 bus_size_t memsize; 287 int pmreg; 288 pcireg_t pmode; 289 int error; 290 int i; 291 292 bp = bce_lookup(pa); 293 KASSERT(bp != NULL); 294 295 sc->bce_pa = *pa; 296 sc->bce_dmatag = pa->pa_dmat; 297 298 #if __NetBSD_Version__ >= 106120000 299 aprint_naive(": Ethernet controller\n"); 300 #endif 301 APRINT_NORMAL(": %s\n", bp->bp_name); 302 303 /* 304 * Map control/status registers. 305 */ 306 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 307 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 308 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 309 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 310 311 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 312 APRINT_ERROR("%s: failed to enable memory mapping!\n", 313 sc->bce_dev.dv_xname); 314 return; 315 } 316 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 317 switch (memtype) { 318 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 319 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 320 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 321 &sc->bce_bhandle, &memaddr, &memsize) == 0) 322 break; 323 default: 324 APRINT_ERROR("%s: unable to find mem space\n", 325 sc->bce_dev.dv_xname); 326 return; 327 } 328 329 /* Get it out of power save mode if needed. */ 330 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 331 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 332 if (pmode == 3) { 333 /* 334 * The card has lost all configuration data in 335 * this state, so punt. 336 */ 337 printf("%s: unable to wake up from power state D3\n", 338 sc->bce_dev.dv_xname); 339 return; 340 } 341 if (pmode != 0) { 342 printf("%s: waking up from power state D%d\n", 343 sc->bce_dev.dv_xname, pmode); 344 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 345 } 346 } 347 if (pci_intr_map(pa, &ih)) { 348 APRINT_ERROR("%s: couldn't map interrupt\n", 349 sc->bce_dev.dv_xname); 350 return; 351 } 352 intrstr = pci_intr_string(pc, ih); 353 354 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 355 356 if (sc->bce_intrhand == NULL) { 357 APRINT_ERROR("%s: couldn't establish interrupt", 358 sc->bce_dev.dv_xname); 359 if (intrstr != NULL) 360 APRINT_NORMAL(" at %s", intrstr); 361 APRINT_NORMAL("\n"); 362 return; 363 } 364 APRINT_NORMAL("%s: interrupting at %s\n", 365 sc->bce_dev.dv_xname, intrstr); 366 367 /* reset the chip */ 368 bce_reset(sc); 369 370 /* 371 * Allocate DMA-safe memory for ring descriptors. 372 * The receive, and transmit rings can not share the same 373 * 4k space, however both are allocated at once here. 374 */ 375 /* 376 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 377 * due to the limition above. ?? 378 */ 379 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 380 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 381 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 382 printf("%s: unable to alloc space for ring descriptors, " 383 "error = %d\n", sc->bce_dev.dv_xname, error); 384 return; 385 } 386 /* map ring space to kernel */ 387 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 388 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 389 printf("%s: unable to map DMA buffers, error = %d\n", 390 sc->bce_dev.dv_xname, error); 391 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 392 return; 393 } 394 /* create a dma map for the ring */ 395 if ((error = bus_dmamap_create(sc->bce_dmatag, 396 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 397 &sc->bce_ring_map))) { 398 printf("%s: unable to create ring DMA map, error = %d\n", 399 sc->bce_dev.dv_xname, error); 400 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 401 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 402 return; 403 } 404 /* connect the ring space to the dma map */ 405 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 406 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 407 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 408 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 409 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 410 return; 411 } 412 /* save the ring space in softc */ 413 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 414 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 415 416 /* Create the transmit buffer DMA maps. */ 417 for (i = 0; i < BCE_NTXDESC; i++) { 418 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 419 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 420 printf("%s: unable to create tx DMA map, error = %d\n", 421 sc->bce_dev.dv_xname, error); 422 } 423 sc->bce_cdata.bce_tx_chain[i] = NULL; 424 } 425 426 /* Create the receive buffer DMA maps. */ 427 for (i = 0; i < BCE_NRXDESC; i++) { 428 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 429 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 430 printf("%s: unable to create rx DMA map, error = %d\n", 431 sc->bce_dev.dv_xname, error); 432 } 433 sc->bce_cdata.bce_rx_chain[i] = NULL; 434 } 435 436 /* Set up ifnet structure */ 437 ifp = &sc->ethercom.ec_if; 438 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 439 ifp->if_softc = sc; 440 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 441 ifp->if_ioctl = bce_ioctl; 442 ifp->if_start = bce_start; 443 ifp->if_watchdog = bce_watchdog; 444 ifp->if_init = bce_init; 445 ifp->if_stop = bce_stop; 446 IFQ_SET_READY(&ifp->if_snd); 447 448 /* Initialize our media structures and probe the MII. */ 449 450 sc->bce_mii.mii_ifp = ifp; 451 sc->bce_mii.mii_readreg = bce_mii_read; 452 sc->bce_mii.mii_writereg = bce_mii_write; 453 sc->bce_mii.mii_statchg = bce_statchg; 454 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 455 bce_mediastatus); 456 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 457 MII_OFFSET_ANY, 0); 458 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 459 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 460 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 461 } else 462 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 463 /* get the phy */ 464 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_PHY) & 0x1f; 466 /* 467 * Enable activity led. 468 * XXX This should be in a phy driver, but not currently. 469 */ 470 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 471 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 472 /* enable traffic meter led mode */ 473 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 474 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 475 476 477 /* Attach the interface */ 478 if_attach(ifp); 479 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 480 BCE_MAGIC_ENET0); 481 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 482 BCE_MAGIC_ENET1); 483 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 484 BCE_MAGIC_ENET2); 485 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 486 BCE_MAGIC_ENET3); 487 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 488 BCE_MAGIC_ENET4); 489 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 490 BCE_MAGIC_ENET5); 491 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 492 ether_sprintf(sc->enaddr)); 493 ether_ifattach(ifp, sc->enaddr); 494 callout_init(&sc->bce_timeout); 495 } 496 497 /* handle media, and ethernet requests */ 498 static int 499 bce_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 500 { 501 struct bce_softc *sc = ifp->if_softc; 502 struct ifreq *ifr = (struct ifreq *) data; 503 int s, error; 504 505 s = splnet(); 506 switch (cmd) { 507 case SIOCSIFMEDIA: 508 case SIOCGIFMEDIA: 509 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 510 break; 511 default: 512 error = ether_ioctl(ifp, cmd, data); 513 if (error == ENETRESET) { 514 /* change multicast list */ 515 error = 0; 516 } 517 break; 518 } 519 520 /* Try to get more packets going. */ 521 bce_start(ifp); 522 523 splx(s); 524 return error; 525 } 526 527 /* Start packet transmission on the interface. */ 528 static void 529 bce_start(struct ifnet *ifp) 530 { 531 struct bce_softc *sc = ifp->if_softc; 532 struct mbuf *m0; 533 bus_dmamap_t dmamap; 534 int txstart; 535 int txsfree; 536 int newpkts = 0; 537 int error; 538 539 /* 540 * do not start another if currently transmitting, and more 541 * descriptors(tx slots) are needed for next packet. 542 */ 543 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 544 return; 545 546 /* determine number of descriptors available */ 547 if (sc->bce_txsnext >= sc->bce_txin) 548 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 549 else 550 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 551 552 /* 553 * Loop through the send queue, setting up transmit descriptors 554 * until we drain the queue, or use up all available transmit 555 * descriptors. 556 */ 557 while (txsfree > 0) { 558 int seg; 559 560 /* Grab a packet off the queue. */ 561 IFQ_POLL(&ifp->if_snd, m0); 562 if (m0 == NULL) 563 break; 564 565 /* get the transmit slot dma map */ 566 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 567 568 /* 569 * Load the DMA map. If this fails, the packet either 570 * didn't fit in the alloted number of segments, or we 571 * were short on resources. If the packet will not fit, 572 * it will be dropped. If short on resources, it will 573 * be tried again later. 574 */ 575 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 576 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 577 if (error == EFBIG) { 578 printf("%s: Tx packet consumes too many DMA segments, " 579 "dropping...\n", sc->bce_dev.dv_xname); 580 IFQ_DEQUEUE(&ifp->if_snd, m0); 581 m_freem(m0); 582 ifp->if_oerrors++; 583 continue; 584 } else if (error) { 585 /* short on resources, come back later */ 586 printf("%s: unable to load Tx buffer, error = %d\n", 587 sc->bce_dev.dv_xname, error); 588 break; 589 } 590 /* If not enough descriptors available, try again later */ 591 if (dmamap->dm_nsegs > txsfree) { 592 ifp->if_flags |= IFF_OACTIVE; 593 bus_dmamap_unload(sc->bce_dmatag, dmamap); 594 break; 595 } 596 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 597 598 /* So take it off the queue */ 599 IFQ_DEQUEUE(&ifp->if_snd, m0); 600 601 /* save the pointer so it can be freed later */ 602 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 603 604 /* Sync the data DMA map. */ 605 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 606 BUS_DMASYNC_PREWRITE); 607 608 /* Initialize the transmit descriptor(s). */ 609 txstart = sc->bce_txsnext; 610 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 611 u_int32_t ctrl; 612 613 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 614 if (seg == 0) 615 ctrl |= CTRL_SOF; 616 if (seg == dmamap->dm_nsegs - 1) 617 ctrl |= CTRL_EOF; 618 if (sc->bce_txsnext == BCE_NTXDESC - 1) 619 ctrl |= CTRL_EOT; 620 ctrl |= CTRL_IOC; 621 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 622 sc->bce_tx_ring[sc->bce_txsnext].addr = 623 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 624 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 625 sc->bce_txsnext = 0; 626 else 627 sc->bce_txsnext++; 628 txsfree--; 629 } 630 /* sync descriptors being used */ 631 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 632 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 633 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 634 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 635 636 /* Give the packet to the chip. */ 637 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 638 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 639 640 newpkts++; 641 642 #if NBPFILTER > 0 643 /* Pass the packet to any BPF listeners. */ 644 if (ifp->if_bpf) 645 bpf_mtap(ifp->if_bpf, m0); 646 #endif /* NBPFILTER > 0 */ 647 } 648 if (txsfree == 0) { 649 /* No more slots left; notify upper layer. */ 650 ifp->if_flags |= IFF_OACTIVE; 651 } 652 if (newpkts) { 653 /* Set a watchdog timer in case the chip flakes out. */ 654 ifp->if_timer = 5; 655 } 656 } 657 658 /* Watchdog timer handler. */ 659 static void 660 bce_watchdog(struct ifnet *ifp) 661 { 662 struct bce_softc *sc = ifp->if_softc; 663 664 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 665 ifp->if_oerrors++; 666 667 (void) bce_init(ifp); 668 669 /* Try to get more packets going. */ 670 bce_start(ifp); 671 } 672 673 int 674 bce_intr(void *xsc) 675 { 676 struct bce_softc *sc; 677 struct ifnet *ifp; 678 u_int32_t intstatus; 679 int wantinit; 680 int handled = 0; 681 682 sc = xsc; 683 ifp = &sc->ethercom.ec_if; 684 685 686 for (wantinit = 0; wantinit == 0;) { 687 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 688 BCE_INT_STS); 689 690 /* ignore if not ours, or unsolicited interrupts */ 691 intstatus &= sc->bce_intmask; 692 if (intstatus == 0) 693 break; 694 695 handled = 1; 696 697 /* Ack interrupt */ 698 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 699 intstatus); 700 701 /* Receive interrupts. */ 702 if (intstatus & I_RI) 703 bce_rxintr(sc); 704 /* Transmit interrupts. */ 705 if (intstatus & I_XI) 706 bce_txintr(sc); 707 /* Error interrupts */ 708 if (intstatus & ~(I_RI | I_XI)) { 709 if (intstatus & I_XU) 710 printf("%s: transmit fifo underflow\n", 711 sc->bce_dev.dv_xname); 712 if (intstatus & I_RO) { 713 printf("%s: receive fifo overflow\n", 714 sc->bce_dev.dv_xname); 715 ifp->if_ierrors++; 716 } 717 if (intstatus & I_RU) 718 printf("%s: receive descriptor underflow\n", 719 sc->bce_dev.dv_xname); 720 if (intstatus & I_DE) 721 printf("%s: descriptor protocol error\n", 722 sc->bce_dev.dv_xname); 723 if (intstatus & I_PD) 724 printf("%s: data error\n", 725 sc->bce_dev.dv_xname); 726 if (intstatus & I_PC) 727 printf("%s: descriptor error\n", 728 sc->bce_dev.dv_xname); 729 if (intstatus & I_TO) 730 printf("%s: general purpose timeout\n", 731 sc->bce_dev.dv_xname); 732 wantinit = 1; 733 } 734 } 735 736 if (handled) { 737 if (wantinit) 738 bce_init(ifp); 739 /* Try to get more packets going. */ 740 bce_start(ifp); 741 } 742 return (handled); 743 } 744 745 /* Receive interrupt handler */ 746 void 747 bce_rxintr(struct bce_softc *sc) 748 { 749 struct ifnet *ifp = &sc->ethercom.ec_if; 750 struct rx_pph *pph; 751 struct mbuf *m; 752 int curr; 753 int len; 754 int i; 755 756 /* get pointer to active receive slot */ 757 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 758 & RS_CD_MASK; 759 curr = curr / sizeof(struct bce_dma_slot); 760 if (curr >= BCE_NRXDESC) 761 curr = BCE_NRXDESC - 1; 762 763 /* process packets up to but not current packet being worked on */ 764 for (i = sc->bce_rxin; i != curr; 765 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 766 /* complete any post dma memory ops on packet */ 767 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 768 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 769 BUS_DMASYNC_POSTREAD); 770 771 /* 772 * If the packet had an error, simply recycle the buffer, 773 * resetting the len, and flags. 774 */ 775 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 776 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 777 ifp->if_ierrors++; 778 pph->len = 0; 779 pph->flags = 0; 780 continue; 781 } 782 /* receive the packet */ 783 len = pph->len; 784 if (len == 0) 785 continue; /* no packet if empty */ 786 pph->len = 0; 787 pph->flags = 0; 788 /* bump past pre header to packet */ 789 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 790 791 /* 792 * The chip includes the CRC with every packet. Trim 793 * it off here. 794 */ 795 len -= ETHER_CRC_LEN; 796 797 /* 798 * If the packet is small enough to fit in a 799 * single header mbuf, allocate one and copy 800 * the data into it. This greatly reduces 801 * memory consumption when receiving lots 802 * of small packets. 803 * 804 * Otherwise, add a new buffer to the receive 805 * chain. If this fails, drop the packet and 806 * recycle the old buffer. 807 */ 808 if (len <= (MHLEN - 2)) { 809 MGETHDR(m, M_DONTWAIT, MT_DATA); 810 if (m == NULL) 811 goto dropit; 812 m->m_data += 2; 813 memcpy(mtod(m, caddr_t), 814 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 815 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 816 } else { 817 m = sc->bce_cdata.bce_rx_chain[i]; 818 if (bce_add_rxbuf(sc, i) != 0) { 819 dropit: 820 ifp->if_ierrors++; 821 /* continue to use old buffer */ 822 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 823 bus_dmamap_sync(sc->bce_dmatag, 824 sc->bce_cdata.bce_rx_map[i], 0, 825 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 826 BUS_DMASYNC_PREREAD); 827 continue; 828 } 829 } 830 831 m->m_pkthdr.rcvif = ifp; 832 m->m_pkthdr.len = m->m_len = len; 833 ifp->if_ipackets++; 834 835 #if NBPFILTER > 0 836 /* 837 * Pass this up to any BPF listeners, but only 838 * pass it up the stack if it's for us. 839 */ 840 if (ifp->if_bpf) 841 bpf_mtap(ifp->if_bpf, m); 842 #endif /* NBPFILTER > 0 */ 843 844 /* Pass it on. */ 845 (*ifp->if_input) (ifp, m); 846 847 /* re-check current in case it changed */ 848 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 849 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 850 sizeof(struct bce_dma_slot); 851 if (curr >= BCE_NRXDESC) 852 curr = BCE_NRXDESC - 1; 853 } 854 sc->bce_rxin = curr; 855 } 856 857 /* Transmit interrupt handler */ 858 void 859 bce_txintr(struct bce_softc *sc) 860 { 861 struct ifnet *ifp = &sc->ethercom.ec_if; 862 int curr; 863 int i; 864 865 ifp->if_flags &= ~IFF_OACTIVE; 866 867 /* 868 * Go through the Tx list and free mbufs for those 869 * frames which have been transmitted. 870 */ 871 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 872 RS_CD_MASK; 873 curr = curr / sizeof(struct bce_dma_slot); 874 if (curr >= BCE_NTXDESC) 875 curr = BCE_NTXDESC - 1; 876 for (i = sc->bce_txin; i != curr; 877 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 878 /* do any post dma memory ops on transmit data */ 879 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 880 continue; 881 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 882 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 883 BUS_DMASYNC_POSTWRITE); 884 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 885 m_freem(sc->bce_cdata.bce_tx_chain[i]); 886 sc->bce_cdata.bce_tx_chain[i] = NULL; 887 ifp->if_opackets++; 888 } 889 sc->bce_txin = curr; 890 891 /* 892 * If there are no more pending transmissions, cancel the watchdog 893 * timer 894 */ 895 if (sc->bce_txsnext == sc->bce_txin) 896 ifp->if_timer = 0; 897 } 898 899 /* initialize the interface */ 900 static int 901 bce_init(struct ifnet *ifp) 902 { 903 struct bce_softc *sc = ifp->if_softc; 904 u_int32_t reg_win; 905 int error; 906 int i; 907 908 /* Cancel any pending I/O. */ 909 bce_stop(ifp, 0); 910 911 /* enable pci inerrupts, bursts, and prefetch */ 912 913 /* remap the pci registers to the Sonics config registers */ 914 915 /* save the current map, so it can be restored */ 916 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 917 BCE_REG_WIN); 918 919 /* set register window to Sonics registers */ 920 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 921 BCE_SONICS_WIN); 922 923 /* enable SB to PCI interrupt */ 924 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 925 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 926 SBIV_ENET0); 927 928 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 929 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 930 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 931 SBTOPCI_PREF | SBTOPCI_BURST); 932 933 /* restore to ethernet register space */ 934 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 935 reg_win); 936 937 /* Reset the chip to a known state. */ 938 bce_reset(sc); 939 940 /* Initialize transmit descriptors */ 941 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 942 sc->bce_txsnext = 0; 943 sc->bce_txin = 0; 944 945 /* enable crc32 generation */ 946 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 947 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 948 BCE_EMC_CG); 949 950 /* setup DMA interrupt control */ 951 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 952 953 /* setup packet filter */ 954 bce_set_filter(ifp); 955 956 /* set max frame length, account for possible vlan tag */ 957 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 958 ETHER_MAX_LEN + 32); 959 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 960 ETHER_MAX_LEN + 32); 961 962 /* set tx watermark */ 963 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 964 965 /* enable transmit */ 966 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 967 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 968 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 969 970 /* 971 * Give the receive ring to the chip, and 972 * start the receive DMA engine. 973 */ 974 sc->bce_rxin = 0; 975 976 /* clear the rx descriptor ring */ 977 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 978 /* enable receive */ 979 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 980 30 << 1 | 1); /* MAGIC */ 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 982 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 983 984 /* Initalize receive descriptors */ 985 for (i = 0; i < BCE_NRXDESC; i++) { 986 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 987 if ((error = bce_add_rxbuf(sc, i)) != 0) { 988 printf("%s: unable to allocate or map rx(%d) " 989 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 990 i, error); 991 bce_rxdrain(sc); 992 return (error); 993 } 994 } else 995 BCE_INIT_RXDESC(sc, i); 996 } 997 998 /* Enable interrupts */ 999 sc->bce_intmask = 1000 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 1001 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 1002 sc->bce_intmask); 1003 1004 /* start the receive dma */ 1005 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 1006 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1007 1008 /* set media */ 1009 mii_mediachg(&sc->bce_mii); 1010 1011 /* turn on the ethernet mac */ 1012 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1013 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1014 BCE_ENET_CTL) | EC_EE); 1015 1016 /* start timer */ 1017 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1018 1019 /* mark as running, and no outputs active */ 1020 ifp->if_flags |= IFF_RUNNING; 1021 ifp->if_flags &= ~IFF_OACTIVE; 1022 1023 return 0; 1024 } 1025 1026 /* add a mac address to packet filter */ 1027 void 1028 bce_add_mac(struct bce_softc *sc, u_int8_t *mac, u_long idx) 1029 { 1030 int i; 1031 u_int32_t rval; 1032 1033 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1034 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1035 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1036 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1037 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1038 idx << 16 | 8); /* MAGIC */ 1039 /* wait for write to complete */ 1040 for (i = 0; i < 100; i++) { 1041 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1042 BCE_FILT_CTL); 1043 if (!(rval & 0x80000000)) /* MAGIC */ 1044 break; 1045 delay(10); 1046 } 1047 if (i == 100) { 1048 printf("%s: timed out writing pkt filter ctl\n", 1049 sc->bce_dev.dv_xname); 1050 } 1051 } 1052 1053 /* Add a receive buffer to the indiciated descriptor. */ 1054 static int 1055 bce_add_rxbuf(struct bce_softc *sc, int idx) 1056 { 1057 struct mbuf *m; 1058 int error; 1059 1060 MGETHDR(m, M_DONTWAIT, MT_DATA); 1061 if (m == NULL) 1062 return (ENOBUFS); 1063 1064 MCLGET(m, M_DONTWAIT); 1065 if ((m->m_flags & M_EXT) == 0) { 1066 m_freem(m); 1067 return (ENOBUFS); 1068 } 1069 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1070 bus_dmamap_unload(sc->bce_dmatag, 1071 sc->bce_cdata.bce_rx_map[idx]); 1072 1073 sc->bce_cdata.bce_rx_chain[idx] = m; 1074 1075 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1076 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1077 BUS_DMA_READ | BUS_DMA_NOWAIT); 1078 if (error) 1079 return (error); 1080 1081 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1082 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1083 1084 BCE_INIT_RXDESC(sc, idx); 1085 1086 return (0); 1087 1088 } 1089 1090 /* Drain the receive queue. */ 1091 static void 1092 bce_rxdrain(struct bce_softc *sc) 1093 { 1094 int i; 1095 1096 for (i = 0; i < BCE_NRXDESC; i++) { 1097 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1098 bus_dmamap_unload(sc->bce_dmatag, 1099 sc->bce_cdata.bce_rx_map[i]); 1100 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1101 sc->bce_cdata.bce_rx_chain[i] = NULL; 1102 } 1103 } 1104 } 1105 1106 /* Stop transmission on the interface */ 1107 static void 1108 bce_stop(struct ifnet *ifp, int disable) 1109 { 1110 struct bce_softc *sc = ifp->if_softc; 1111 int i; 1112 u_int32_t val; 1113 1114 /* Stop the 1 second timer */ 1115 callout_stop(&sc->bce_timeout); 1116 1117 /* Down the MII. */ 1118 mii_down(&sc->bce_mii); 1119 1120 /* Disable interrupts. */ 1121 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1122 sc->bce_intmask = 0; 1123 delay(10); 1124 1125 /* Disable emac */ 1126 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1127 for (i = 0; i < 200; i++) { 1128 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1129 BCE_ENET_CTL); 1130 if (!(val & EC_ED)) 1131 break; 1132 delay(10); 1133 } 1134 1135 /* Stop the DMA */ 1136 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1137 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1138 delay(10); 1139 1140 /* Release any queued transmit buffers. */ 1141 for (i = 0; i < BCE_NTXDESC; i++) { 1142 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1143 bus_dmamap_unload(sc->bce_dmatag, 1144 sc->bce_cdata.bce_tx_map[i]); 1145 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1146 sc->bce_cdata.bce_tx_chain[i] = NULL; 1147 } 1148 } 1149 1150 /* drain receive queue */ 1151 if (disable) 1152 bce_rxdrain(sc); 1153 1154 /* Mark the interface down and cancel the watchdog timer. */ 1155 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1156 ifp->if_timer = 0; 1157 } 1158 1159 /* reset the chip */ 1160 static void 1161 bce_reset(struct bce_softc *sc) 1162 { 1163 u_int32_t val; 1164 u_int32_t sbval; 1165 int i; 1166 1167 /* if SB core is up */ 1168 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1169 BCE_SBTMSTATELOW); 1170 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1171 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1172 0); 1173 1174 /* disable emac */ 1175 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1176 EC_ED); 1177 for (i = 0; i < 200; i++) { 1178 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1179 BCE_ENET_CTL); 1180 if (!(val & EC_ED)) 1181 break; 1182 delay(10); 1183 } 1184 if (i == 200) 1185 printf("%s: timed out disabling ethernet mac\n", 1186 sc->bce_dev.dv_xname); 1187 1188 /* reset the dma engines */ 1189 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1190 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1191 /* if error on receive, wait to go idle */ 1192 if (val & RS_ERROR) { 1193 for (i = 0; i < 100; i++) { 1194 val = bus_space_read_4(sc->bce_btag, 1195 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1196 if (val & RS_DMA_IDLE) 1197 break; 1198 delay(10); 1199 } 1200 if (i == 100) 1201 printf("%s: receive dma did not go idle after" 1202 " error\n", sc->bce_dev.dv_xname); 1203 } 1204 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1205 BCE_DMA_RXSTATUS, 0); 1206 1207 /* reset ethernet mac */ 1208 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1209 EC_ES); 1210 for (i = 0; i < 200; i++) { 1211 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1212 BCE_ENET_CTL); 1213 if (!(val & EC_ES)) 1214 break; 1215 delay(10); 1216 } 1217 if (i == 200) 1218 printf("%s: timed out restting ethernet mac\n", 1219 sc->bce_dev.dv_xname); 1220 } else { 1221 u_int32_t reg_win; 1222 1223 /* remap the pci registers to the Sonics config registers */ 1224 1225 /* save the current map, so it can be restored */ 1226 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1227 BCE_REG_WIN); 1228 /* set register window to Sonics registers */ 1229 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1230 BCE_REG_WIN, BCE_SONICS_WIN); 1231 1232 /* enable SB to PCI interrupt */ 1233 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1234 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1235 BCE_SBINTVEC) | 1236 SBIV_ENET0); 1237 1238 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1239 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1240 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1241 BCE_SPCI_TR2) | 1242 SBTOPCI_PREF | SBTOPCI_BURST); 1243 1244 /* restore to ethernet register space */ 1245 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1246 reg_win); 1247 } 1248 1249 /* disable SB core if not in reset */ 1250 if (!(sbval & SBTML_RESET)) { 1251 1252 /* set the reject bit */ 1253 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1254 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1255 for (i = 0; i < 200; i++) { 1256 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1257 BCE_SBTMSTATELOW); 1258 if (val & SBTML_REJ) 1259 break; 1260 delay(1); 1261 } 1262 if (i == 200) 1263 printf("%s: while restting core, reject did not set\n", 1264 sc->bce_dev.dv_xname); 1265 /* wait until busy is clear */ 1266 for (i = 0; i < 200; i++) { 1267 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1268 BCE_SBTMSTATEHI); 1269 if (!(val & 0x4)) 1270 break; 1271 delay(1); 1272 } 1273 if (i == 200) 1274 printf("%s: while restting core, busy did not clear\n", 1275 sc->bce_dev.dv_xname); 1276 /* set reset and reject while enabling the clocks */ 1277 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1278 BCE_SBTMSTATELOW, 1279 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1280 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1281 BCE_SBTMSTATELOW); 1282 delay(10); 1283 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1284 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1285 delay(1); 1286 } 1287 /* enable clock */ 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1289 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1290 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1291 delay(1); 1292 1293 /* clear any error bits that may be on */ 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1295 if (val & 1) 1296 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1297 0); 1298 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1299 if (val & SBIM_MAGIC_ERRORBITS) 1300 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1301 val & ~SBIM_MAGIC_ERRORBITS); 1302 1303 /* clear reset and allow it to propagate throughout the core */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1305 SBTML_FGC | SBTML_CLK); 1306 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1307 delay(1); 1308 1309 /* leave clock enabled */ 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1311 SBTML_CLK); 1312 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1313 delay(1); 1314 1315 /* initialize MDC preamble, frequency */ 1316 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1317 1318 /* enable phy, differs for internal, and external */ 1319 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1320 if (!(val & BCE_DC_IP)) { 1321 /* select external phy */ 1322 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1323 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1324 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1325 val & ~BCE_DC_ER); 1326 delay(100); 1327 } 1328 } 1329 1330 /* Set up the receive filter. */ 1331 void 1332 bce_set_filter(struct ifnet *ifp) 1333 { 1334 struct bce_softc *sc = ifp->if_softc; 1335 1336 if (ifp->if_flags & IFF_PROMISC) { 1337 ifp->if_flags |= IFF_ALLMULTI; 1338 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1339 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1340 | ERC_PE); 1341 } else { 1342 ifp->if_flags &= ~IFF_ALLMULTI; 1343 1344 /* turn off promiscuous */ 1345 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1346 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1347 BCE_RX_CTL) & ~ERC_PE); 1348 1349 /* enable/disable broadcast */ 1350 if (ifp->if_flags & IFF_BROADCAST) 1351 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1352 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1353 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1354 else 1355 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1356 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1357 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1358 1359 /* disable the filter */ 1360 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1361 0); 1362 1363 /* add our own address */ 1364 bce_add_mac(sc, sc->enaddr, 0); 1365 1366 /* for now accept all multicast */ 1367 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1368 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1369 ERC_AM); 1370 ifp->if_flags |= IFF_ALLMULTI; 1371 1372 /* enable the filter */ 1373 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1374 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1375 BCE_FILT_CTL) | 1); 1376 } 1377 } 1378 1379 /* Read a PHY register on the MII. */ 1380 int 1381 bce_mii_read(struct device *self, int phy, int reg) 1382 { 1383 struct bce_softc *sc = (struct bce_softc *) self; 1384 int i; 1385 u_int32_t val; 1386 1387 /* clear mii_int */ 1388 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1389 1390 /* Read the PHY register */ 1391 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1392 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1393 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1394 1395 for (i = 0; i < BCE_TIMEOUT; i++) { 1396 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1397 if (val & BCE_MIINTR) 1398 break; 1399 delay(10); 1400 } 1401 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1402 if (i == BCE_TIMEOUT) { 1403 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1404 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1405 return (0); 1406 } 1407 return (val & BCE_MICOMM_DATA); 1408 } 1409 1410 /* Write a PHY register on the MII */ 1411 void 1412 bce_mii_write(struct device *self, int phy, int reg, int val) 1413 { 1414 struct bce_softc *sc = (struct bce_softc *) self; 1415 int i; 1416 u_int32_t rval; 1417 1418 /* clear mii_int */ 1419 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1420 BCE_MIINTR); 1421 1422 /* Write the PHY register */ 1423 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1424 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1425 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1426 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1427 1428 /* wait for write to complete */ 1429 for (i = 0; i < BCE_TIMEOUT; i++) { 1430 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1431 BCE_MI_STS); 1432 if (rval & BCE_MIINTR) 1433 break; 1434 delay(10); 1435 } 1436 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1437 if (i == BCE_TIMEOUT) { 1438 printf("%s: PHY timed out writing phy %d, reg %d, val " 1439 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1440 } 1441 } 1442 1443 /* sync hardware duplex mode to software state */ 1444 void 1445 bce_statchg(struct device *self) 1446 { 1447 struct bce_softc *sc = (struct bce_softc *) self; 1448 u_int32_t reg; 1449 1450 /* if needed, change register to match duplex mode */ 1451 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1452 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1453 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1454 reg | EXC_FD); 1455 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1456 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1457 reg & ~EXC_FD); 1458 1459 /* 1460 * Enable activity led. 1461 * XXX This should be in a phy driver, but not currently. 1462 */ 1463 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1464 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1465 /* enable traffic meter led mode */ 1466 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1467 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1468 } 1469 1470 /* Set hardware to newly-selected media */ 1471 int 1472 bce_mediachange(struct ifnet *ifp) 1473 { 1474 struct bce_softc *sc = ifp->if_softc; 1475 1476 if (ifp->if_flags & IFF_UP) 1477 mii_mediachg(&sc->bce_mii); 1478 return (0); 1479 } 1480 1481 /* Get the current interface media status */ 1482 static void 1483 bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1484 { 1485 struct bce_softc *sc = ifp->if_softc; 1486 1487 mii_pollstat(&sc->bce_mii); 1488 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1489 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1490 } 1491 1492 /* One second timer, checks link status */ 1493 static void 1494 bce_tick(void *v) 1495 { 1496 struct bce_softc *sc = v; 1497 1498 /* Tick the MII. */ 1499 mii_tick(&sc->bce_mii); 1500 1501 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1502 } 1503
Indexes created Tue Sep 30 20:09:53 GMT 2025