if_bce.c revision 1.22
1 /* $NetBSD: if_bce.c,v 1.22 2008/02/22 23:21:01 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.22 2008/02/22 23:21:01 dyoung Exp $"); 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include <dev/mii/miidevs.h> 73 #include <dev/mii/brgphyreg.h> 74 75 #include <dev/pci/if_bcereg.h> 76 77 #include <uvm/uvm_extern.h> 78 79 /* transmit buffer max frags allowed */ 80 #define BCE_NTXFRAGS 16 81 82 /* ring descriptor */ 83 struct bce_dma_slot { 84 uint32_t ctrl; 85 uint32_t addr; 86 }; 87 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 88 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 89 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 90 #define CTRL_EOF 0x40000000 /* end of frame */ 91 #define CTRL_SOF 0x80000000 /* start of frame */ 92 93 /* Packet status is returned in a pre-packet header */ 94 struct rx_pph { 95 uint16_t len; 96 uint16_t flags; 97 uint16_t pad[12]; 98 }; 99 100 /* packet status flags bits */ 101 #define RXF_NO 0x8 /* odd number of nibbles */ 102 #define RXF_RXER 0x4 /* receive symbol error */ 103 #define RXF_CRC 0x2 /* crc error */ 104 #define RXF_OV 0x1 /* fifo overflow */ 105 106 /* number of descriptors used in a ring */ 107 #define BCE_NRXDESC 128 108 #define BCE_NTXDESC 128 109 110 /* 111 * Mbuf pointers. We need these to keep track of the virtual addresses 112 * of our mbuf chains since we can only convert from physical to virtual, 113 * not the other way around. 114 */ 115 struct bce_chain_data { 116 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 117 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 118 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 119 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 120 }; 121 122 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 123 124 struct bce_softc { 125 struct device bce_dev; 126 bus_space_tag_t bce_btag; 127 bus_space_handle_t bce_bhandle; 128 bus_dma_tag_t bce_dmatag; 129 struct ethercom ethercom; /* interface info */ 130 void *bce_intrhand; 131 struct pci_attach_args bce_pa; 132 struct mii_data bce_mii; 133 uint32_t bce_phy; /* eeprom indicated phy */ 134 struct ifmedia bce_ifmedia; /* media info *//* Check */ 135 uint8_t enaddr[ETHER_ADDR_LEN]; 136 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 137 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 138 struct bce_chain_data bce_cdata; /* mbufs */ 139 bus_dmamap_t bce_ring_map; 140 uint32_t bce_intmask; /* current intr mask */ 141 uint32_t bce_rxin; /* last rx descriptor seen */ 142 uint32_t bce_txin; /* last tx descriptor seen */ 143 int bce_txsfree; /* no. tx slots available */ 144 int bce_txsnext; /* next available tx slot */ 145 callout_t bce_timeout; 146 #if NRND > 0 147 rndsource_element_t rnd_source; 148 #endif 149 }; 150 151 /* for ring descriptors */ 152 #define BCE_RXBUF_LEN (MCLBYTES - 4) 153 #define BCE_INIT_RXDESC(sc, x) \ 154 do { \ 155 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 156 \ 157 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 158 __bced->addr = \ 159 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 160 + 0x40000000); \ 161 if (x != (BCE_NRXDESC - 1)) \ 162 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 163 else \ 164 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 165 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 166 sizeof(struct bce_dma_slot) * x, \ 167 sizeof(struct bce_dma_slot), \ 168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 169 } while (/* CONSTCOND */ 0) 170 171 static int bce_probe(device_t, struct cfdata *, void *); 172 static void bce_attach(device_t, device_t, void *); 173 static int bce_ioctl(struct ifnet *, u_long, void *); 174 static void bce_start(struct ifnet *); 175 static void bce_watchdog(struct ifnet *); 176 static int bce_intr(void *); 177 static void bce_rxintr(struct bce_softc *); 178 static void bce_txintr(struct bce_softc *); 179 static int bce_init(struct ifnet *); 180 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 181 static int bce_add_rxbuf(struct bce_softc *, int); 182 static void bce_rxdrain(struct bce_softc *); 183 static void bce_stop(struct ifnet *, int); 184 static void bce_reset(struct bce_softc *); 185 static bool bce_resume(device_t PMF_FN_PROTO); 186 static void bce_set_filter(struct ifnet *); 187 static int bce_mii_read(device_t, int, int); 188 static void bce_mii_write(device_t, int, int, int); 189 static void bce_statchg(device_t); 190 static void bce_tick(void *); 191 192 CFATTACH_DECL(bce, sizeof(struct bce_softc), bce_probe, bce_attach, NULL, NULL); 193 194 static const struct bce_product { 195 pci_vendor_id_t bp_vendor; 196 pci_product_id_t bp_product; 197 const char *bp_name; 198 } bce_products[] = { 199 { 200 PCI_VENDOR_BROADCOM, 201 PCI_PRODUCT_BROADCOM_BCM4401, 202 "Broadcom BCM4401 10/100 Ethernet" 203 }, 204 { 205 PCI_VENDOR_BROADCOM, 206 PCI_PRODUCT_BROADCOM_BCM4401_B0, 207 "Broadcom BCM4401-B0 10/100 Ethernet" 208 }, 209 { 210 211 0, 212 0, 213 NULL 214 }, 215 }; 216 217 static const struct bce_product * 218 bce_lookup(const struct pci_attach_args * pa) 219 { 220 const struct bce_product *bp; 221 222 for (bp = bce_products; bp->bp_name != NULL; bp++) { 223 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 224 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 225 return (bp); 226 } 227 228 return (NULL); 229 } 230 231 /* 232 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 233 * against drivers product list, and return its name if a match is found. 234 */ 235 static int 236 bce_probe(device_t parent, struct cfdata *match, void *aux) 237 { 238 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 239 240 if (bce_lookup(pa) != NULL) 241 return (1); 242 243 return (0); 244 } 245 246 static void 247 bce_attach(device_t parent, device_t self, void *aux) 248 { 249 struct bce_softc *sc = device_private(self); 250 struct pci_attach_args *pa = aux; 251 const struct bce_product *bp; 252 pci_chipset_tag_t pc = pa->pa_pc; 253 pci_intr_handle_t ih; 254 const char *intrstr = NULL; 255 uint32_t command; 256 pcireg_t memtype, pmode; 257 bus_addr_t memaddr; 258 bus_size_t memsize; 259 void *kva; 260 bus_dma_segment_t seg; 261 int error, i, pmreg, rseg; 262 struct ifnet *ifp; 263 264 bp = bce_lookup(pa); 265 KASSERT(bp != NULL); 266 267 sc->bce_pa = *pa; 268 269 /* BCM440x can only address 30 bits (1GB) */ 270 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 271 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 272 aprint_error_dev(self, 273 "WARNING: failed to restrict dma range," 274 " falling back to parent bus dma range\n"); 275 sc->bce_dmatag = pa->pa_dmat; 276 } 277 278 aprint_naive(": Ethernet controller\n"); 279 aprint_normal(": %s\n", bp->bp_name); 280 281 /* 282 * Map control/status registers. 283 */ 284 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 285 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 286 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 287 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 288 289 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 290 aprint_error_dev(self, "failed to enable memory mapping!\n"); 291 return; 292 } 293 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 294 switch (memtype) { 295 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 296 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 297 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 298 &sc->bce_bhandle, &memaddr, &memsize) == 0) 299 break; 300 default: 301 aprint_error_dev(self, "unable to find mem space\n"); 302 return; 303 } 304 305 /* Get it out of power save mode if needed. */ 306 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 307 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 308 if (pmode == 3) { 309 /* 310 * The card has lost all configuration data in 311 * this state, so punt. 312 */ 313 aprint_error_dev(self, 314 "unable to wake up from power state D3\n"); 315 return; 316 } 317 if (pmode != 0) { 318 aprint_normal_dev(self, 319 "waking up from power state D%d\n", pmode); 320 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 321 } 322 } 323 if (pci_intr_map(pa, &ih)) { 324 aprint_error_dev(self, "couldn't map interrupt\n"); 325 return; 326 } 327 intrstr = pci_intr_string(pc, ih); 328 329 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 330 331 if (sc->bce_intrhand == NULL) { 332 aprint_error_dev(self, "couldn't establish interrupt\n"); 333 if (intrstr != NULL) 334 aprint_normal(" at %s", intrstr); 335 aprint_normal("\n"); 336 return; 337 } 338 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 339 340 /* reset the chip */ 341 bce_reset(sc); 342 343 /* 344 * Allocate DMA-safe memory for ring descriptors. 345 * The receive, and transmit rings can not share the same 346 * 4k space, however both are allocated at once here. 347 */ 348 /* 349 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 350 * due to the limition above. ?? 351 */ 352 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 353 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 354 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 355 aprint_error_dev(self, 356 "unable to alloc space for ring descriptors, error = %d\n", 357 error); 358 return; 359 } 360 /* map ring space to kernel */ 361 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 362 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 363 aprint_error_dev(self, 364 "unable to map DMA buffers, error = %d\n", error); 365 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 366 return; 367 } 368 /* create a dma map for the ring */ 369 if ((error = bus_dmamap_create(sc->bce_dmatag, 370 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 371 &sc->bce_ring_map))) { 372 aprint_error_dev(self, 373 "unable to create ring DMA map, error = %d\n", error); 374 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 375 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 376 return; 377 } 378 /* connect the ring space to the dma map */ 379 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 380 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 381 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 382 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 383 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 384 return; 385 } 386 /* save the ring space in softc */ 387 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 388 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 389 390 /* Create the transmit buffer DMA maps. */ 391 for (i = 0; i < BCE_NTXDESC; i++) { 392 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 393 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 394 aprint_error_dev(self, 395 "unable to create tx DMA map, error = %d\n", error); 396 } 397 sc->bce_cdata.bce_tx_chain[i] = NULL; 398 } 399 400 /* Create the receive buffer DMA maps. */ 401 for (i = 0; i < BCE_NRXDESC; i++) { 402 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 403 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 404 aprint_error_dev(self, 405 "unable to create rx DMA map, error = %d\n", error); 406 } 407 sc->bce_cdata.bce_rx_chain[i] = NULL; 408 } 409 410 /* Set up ifnet structure */ 411 ifp = &sc->ethercom.ec_if; 412 strcpy(ifp->if_xname, device_xname(self)); 413 ifp->if_softc = sc; 414 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 415 ifp->if_ioctl = bce_ioctl; 416 ifp->if_start = bce_start; 417 ifp->if_watchdog = bce_watchdog; 418 ifp->if_init = bce_init; 419 ifp->if_stop = bce_stop; 420 IFQ_SET_READY(&ifp->if_snd); 421 422 /* Initialize our media structures and probe the MII. */ 423 424 sc->bce_mii.mii_ifp = ifp; 425 sc->bce_mii.mii_readreg = bce_mii_read; 426 sc->bce_mii.mii_writereg = bce_mii_write; 427 sc->bce_mii.mii_statchg = bce_statchg; 428 429 sc->ethercom.ec_mii = &sc->bce_mii; 430 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 431 ether_mediastatus); 432 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 433 MII_OFFSET_ANY, 0); 434 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 435 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 436 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 437 } else 438 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 439 /* get the phy */ 440 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 441 BCE_MAGIC_PHY) & 0x1f; 442 /* 443 * Enable activity led. 444 * XXX This should be in a phy driver, but not currently. 445 */ 446 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 447 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 448 /* enable traffic meter led mode */ 449 bce_mii_write(&sc->bce_dev, 1, 27, /* MAGIC */ 450 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 451 452 /* Attach the interface */ 453 if_attach(ifp); 454 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 455 BCE_MAGIC_ENET0); 456 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 457 BCE_MAGIC_ENET1); 458 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 459 BCE_MAGIC_ENET2); 460 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET3); 462 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 463 BCE_MAGIC_ENET4); 464 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET5); 466 aprint_normal_dev(self, "Ethernet address %s\n", 467 ether_sprintf(sc->enaddr)); 468 ether_ifattach(ifp, sc->enaddr); 469 #if NRND > 0 470 rnd_attach_source(&sc->rnd_source, device_xname(self), 471 RND_TYPE_NET, 0); 472 #endif 473 callout_init(&sc->bce_timeout, 0); 474 475 if (!pmf_device_register(self, NULL, bce_resume)) { 476 aprint_error_dev(self, "couldn't establish power handler\n"); 477 } else 478 pmf_class_network_register(self, ifp); 479 } 480 481 /* handle media, and ethernet requests */ 482 static int 483 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 484 { 485 int s, error; 486 487 s = splnet(); 488 error = ether_ioctl(ifp, cmd, data); 489 if (error == ENETRESET) { 490 /* change multicast list */ 491 error = 0; 492 } 493 494 /* Try to get more packets going. */ 495 bce_start(ifp); 496 497 splx(s); 498 return error; 499 } 500 501 /* Start packet transmission on the interface. */ 502 static void 503 bce_start(struct ifnet *ifp) 504 { 505 struct bce_softc *sc = ifp->if_softc; 506 struct mbuf *m0; 507 bus_dmamap_t dmamap; 508 int txstart; 509 int txsfree; 510 int newpkts = 0; 511 int error; 512 513 /* 514 * do not start another if currently transmitting, and more 515 * descriptors(tx slots) are needed for next packet. 516 */ 517 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 518 return; 519 520 /* determine number of descriptors available */ 521 if (sc->bce_txsnext >= sc->bce_txin) 522 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 523 else 524 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 525 526 /* 527 * Loop through the send queue, setting up transmit descriptors 528 * until we drain the queue, or use up all available transmit 529 * descriptors. 530 */ 531 while (txsfree > 0) { 532 int seg; 533 534 /* Grab a packet off the queue. */ 535 IFQ_POLL(&ifp->if_snd, m0); 536 if (m0 == NULL) 537 break; 538 539 /* get the transmit slot dma map */ 540 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 541 542 /* 543 * Load the DMA map. If this fails, the packet either 544 * didn't fit in the alloted number of segments, or we 545 * were short on resources. If the packet will not fit, 546 * it will be dropped. If short on resources, it will 547 * be tried again later. 548 */ 549 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 550 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 551 if (error == EFBIG) { 552 aprint_error_dev(&sc->bce_dev, 553 "Tx packet consumes too many DMA segments, " 554 "dropping...\n"); 555 IFQ_DEQUEUE(&ifp->if_snd, m0); 556 m_freem(m0); 557 ifp->if_oerrors++; 558 continue; 559 } else if (error) { 560 /* short on resources, come back later */ 561 aprint_error_dev(&sc->bce_dev, 562 "unable to load Tx buffer, error = %d\n", 563 error); 564 break; 565 } 566 /* If not enough descriptors available, try again later */ 567 if (dmamap->dm_nsegs > txsfree) { 568 ifp->if_flags |= IFF_OACTIVE; 569 bus_dmamap_unload(sc->bce_dmatag, dmamap); 570 break; 571 } 572 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 573 574 /* So take it off the queue */ 575 IFQ_DEQUEUE(&ifp->if_snd, m0); 576 577 /* save the pointer so it can be freed later */ 578 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 579 580 /* Sync the data DMA map. */ 581 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 582 BUS_DMASYNC_PREWRITE); 583 584 /* Initialize the transmit descriptor(s). */ 585 txstart = sc->bce_txsnext; 586 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 587 uint32_t ctrl; 588 589 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 590 if (seg == 0) 591 ctrl |= CTRL_SOF; 592 if (seg == dmamap->dm_nsegs - 1) 593 ctrl |= CTRL_EOF; 594 if (sc->bce_txsnext == BCE_NTXDESC - 1) 595 ctrl |= CTRL_EOT; 596 ctrl |= CTRL_IOC; 597 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 598 sc->bce_tx_ring[sc->bce_txsnext].addr = 599 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 600 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 601 sc->bce_txsnext = 0; 602 else 603 sc->bce_txsnext++; 604 txsfree--; 605 } 606 /* sync descriptors being used */ 607 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 608 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 609 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 610 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 611 612 /* Give the packet to the chip. */ 613 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 614 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 615 616 newpkts++; 617 618 #if NBPFILTER > 0 619 /* Pass the packet to any BPF listeners. */ 620 if (ifp->if_bpf) 621 bpf_mtap(ifp->if_bpf, m0); 622 #endif /* NBPFILTER > 0 */ 623 } 624 if (txsfree == 0) { 625 /* No more slots left; notify upper layer. */ 626 ifp->if_flags |= IFF_OACTIVE; 627 } 628 if (newpkts) { 629 /* Set a watchdog timer in case the chip flakes out. */ 630 ifp->if_timer = 5; 631 } 632 } 633 634 /* Watchdog timer handler. */ 635 static void 636 bce_watchdog(struct ifnet *ifp) 637 { 638 struct bce_softc *sc = ifp->if_softc; 639 640 aprint_error_dev(&sc->bce_dev, "device timeout\n"); 641 ifp->if_oerrors++; 642 643 (void) bce_init(ifp); 644 645 /* Try to get more packets going. */ 646 bce_start(ifp); 647 } 648 649 int 650 bce_intr(void *xsc) 651 { 652 struct bce_softc *sc; 653 struct ifnet *ifp; 654 uint32_t intstatus; 655 int wantinit; 656 int handled = 0; 657 658 sc = xsc; 659 ifp = &sc->ethercom.ec_if; 660 661 for (wantinit = 0; wantinit == 0;) { 662 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 663 BCE_INT_STS); 664 665 /* ignore if not ours, or unsolicited interrupts */ 666 intstatus &= sc->bce_intmask; 667 if (intstatus == 0) 668 break; 669 670 handled = 1; 671 672 /* Ack interrupt */ 673 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 674 intstatus); 675 676 /* Receive interrupts. */ 677 if (intstatus & I_RI) 678 bce_rxintr(sc); 679 /* Transmit interrupts. */ 680 if (intstatus & I_XI) 681 bce_txintr(sc); 682 /* Error interrupts */ 683 if (intstatus & ~(I_RI | I_XI)) { 684 const char *msg = NULL; 685 if (intstatus & I_XU) 686 msg = "transmit fifo underflow"; 687 if (intstatus & I_RO) { 688 msg = "receive fifo overflow"; 689 ifp->if_ierrors++; 690 } 691 if (intstatus & I_RU) 692 msg = "receive descriptor underflow"; 693 if (intstatus & I_DE) 694 msg = "descriptor protocol error"; 695 if (intstatus & I_PD) 696 msg = "data error"; 697 if (intstatus & I_PC) 698 msg = "descriptor error"; 699 if (intstatus & I_TO) 700 msg = "general purpose timeout"; 701 if (msg != NULL) 702 aprint_error_dev(&sc->bce_dev, "%s\n", msg); 703 wantinit = 1; 704 } 705 } 706 707 if (handled) { 708 if (wantinit) 709 bce_init(ifp); 710 #if NRND > 0 711 if (RND_ENABLED(&sc->rnd_source)) 712 rnd_add_uint32(&sc->rnd_source, intstatus); 713 #endif 714 /* Try to get more packets going. */ 715 bce_start(ifp); 716 } 717 return (handled); 718 } 719 720 /* Receive interrupt handler */ 721 void 722 bce_rxintr(struct bce_softc *sc) 723 { 724 struct ifnet *ifp = &sc->ethercom.ec_if; 725 struct rx_pph *pph; 726 struct mbuf *m; 727 int curr; 728 int len; 729 int i; 730 731 /* get pointer to active receive slot */ 732 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 733 & RS_CD_MASK; 734 curr = curr / sizeof(struct bce_dma_slot); 735 if (curr >= BCE_NRXDESC) 736 curr = BCE_NRXDESC - 1; 737 738 /* process packets up to but not current packet being worked on */ 739 for (i = sc->bce_rxin; i != curr; 740 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 741 /* complete any post dma memory ops on packet */ 742 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 743 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 744 BUS_DMASYNC_POSTREAD); 745 746 /* 747 * If the packet had an error, simply recycle the buffer, 748 * resetting the len, and flags. 749 */ 750 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 751 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 752 ifp->if_ierrors++; 753 pph->len = 0; 754 pph->flags = 0; 755 continue; 756 } 757 /* receive the packet */ 758 len = pph->len; 759 if (len == 0) 760 continue; /* no packet if empty */ 761 pph->len = 0; 762 pph->flags = 0; 763 /* bump past pre header to packet */ 764 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 765 766 /* 767 * The chip includes the CRC with every packet. Trim 768 * it off here. 769 */ 770 len -= ETHER_CRC_LEN; 771 772 /* 773 * If the packet is small enough to fit in a 774 * single header mbuf, allocate one and copy 775 * the data into it. This greatly reduces 776 * memory consumption when receiving lots 777 * of small packets. 778 * 779 * Otherwise, add a new buffer to the receive 780 * chain. If this fails, drop the packet and 781 * recycle the old buffer. 782 */ 783 if (len <= (MHLEN - 2)) { 784 MGETHDR(m, M_DONTWAIT, MT_DATA); 785 if (m == NULL) 786 goto dropit; 787 m->m_data += 2; 788 memcpy(mtod(m, void *), 789 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 790 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 791 } else { 792 m = sc->bce_cdata.bce_rx_chain[i]; 793 if (bce_add_rxbuf(sc, i) != 0) { 794 dropit: 795 ifp->if_ierrors++; 796 /* continue to use old buffer */ 797 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 798 bus_dmamap_sync(sc->bce_dmatag, 799 sc->bce_cdata.bce_rx_map[i], 0, 800 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 801 BUS_DMASYNC_PREREAD); 802 continue; 803 } 804 } 805 806 m->m_pkthdr.rcvif = ifp; 807 m->m_pkthdr.len = m->m_len = len; 808 ifp->if_ipackets++; 809 810 #if NBPFILTER > 0 811 /* 812 * Pass this up to any BPF listeners, but only 813 * pass it up the stack if it's for us. 814 */ 815 if (ifp->if_bpf) 816 bpf_mtap(ifp->if_bpf, m); 817 #endif /* NBPFILTER > 0 */ 818 819 /* Pass it on. */ 820 (*ifp->if_input) (ifp, m); 821 822 /* re-check current in case it changed */ 823 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 824 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 825 sizeof(struct bce_dma_slot); 826 if (curr >= BCE_NRXDESC) 827 curr = BCE_NRXDESC - 1; 828 } 829 sc->bce_rxin = curr; 830 } 831 832 /* Transmit interrupt handler */ 833 void 834 bce_txintr(struct bce_softc *sc) 835 { 836 struct ifnet *ifp = &sc->ethercom.ec_if; 837 int curr; 838 int i; 839 840 ifp->if_flags &= ~IFF_OACTIVE; 841 842 /* 843 * Go through the Tx list and free mbufs for those 844 * frames which have been transmitted. 845 */ 846 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 847 RS_CD_MASK; 848 curr = curr / sizeof(struct bce_dma_slot); 849 if (curr >= BCE_NTXDESC) 850 curr = BCE_NTXDESC - 1; 851 for (i = sc->bce_txin; i != curr; 852 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 853 /* do any post dma memory ops on transmit data */ 854 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 855 continue; 856 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 857 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 858 BUS_DMASYNC_POSTWRITE); 859 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 860 m_freem(sc->bce_cdata.bce_tx_chain[i]); 861 sc->bce_cdata.bce_tx_chain[i] = NULL; 862 ifp->if_opackets++; 863 } 864 sc->bce_txin = curr; 865 866 /* 867 * If there are no more pending transmissions, cancel the watchdog 868 * timer 869 */ 870 if (sc->bce_txsnext == sc->bce_txin) 871 ifp->if_timer = 0; 872 } 873 874 /* initialize the interface */ 875 static int 876 bce_init(struct ifnet *ifp) 877 { 878 struct bce_softc *sc = ifp->if_softc; 879 uint32_t reg_win; 880 int error; 881 int i; 882 883 /* Cancel any pending I/O. */ 884 bce_stop(ifp, 0); 885 886 /* enable pci inerrupts, bursts, and prefetch */ 887 888 /* remap the pci registers to the Sonics config registers */ 889 890 /* save the current map, so it can be restored */ 891 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 892 BCE_REG_WIN); 893 894 /* set register window to Sonics registers */ 895 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 896 BCE_SONICS_WIN); 897 898 /* enable SB to PCI interrupt */ 899 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 900 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 901 SBIV_ENET0); 902 903 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 904 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 905 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 906 SBTOPCI_PREF | SBTOPCI_BURST); 907 908 /* restore to ethernet register space */ 909 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 910 reg_win); 911 912 /* Reset the chip to a known state. */ 913 bce_reset(sc); 914 915 /* Initialize transmit descriptors */ 916 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 917 sc->bce_txsnext = 0; 918 sc->bce_txin = 0; 919 920 /* enable crc32 generation */ 921 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 922 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 923 BCE_EMC_CG); 924 925 /* setup DMA interrupt control */ 926 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 927 928 /* setup packet filter */ 929 bce_set_filter(ifp); 930 931 /* set max frame length, account for possible vlan tag */ 932 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 933 ETHER_MAX_LEN + 32); 934 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 935 ETHER_MAX_LEN + 32); 936 937 /* set tx watermark */ 938 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 939 940 /* enable transmit */ 941 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 942 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 943 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 944 945 /* 946 * Give the receive ring to the chip, and 947 * start the receive DMA engine. 948 */ 949 sc->bce_rxin = 0; 950 951 /* clear the rx descriptor ring */ 952 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 953 /* enable receive */ 954 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 955 30 << 1 | 1); /* MAGIC */ 956 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 957 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 958 959 /* Initalize receive descriptors */ 960 for (i = 0; i < BCE_NRXDESC; i++) { 961 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 962 if ((error = bce_add_rxbuf(sc, i)) != 0) { 963 aprint_error_dev(&sc->bce_dev, 964 "unable to allocate or map rx(%d) " 965 "mbuf, error = %d\n", i, error); 966 bce_rxdrain(sc); 967 return (error); 968 } 969 } else 970 BCE_INIT_RXDESC(sc, i); 971 } 972 973 /* Enable interrupts */ 974 sc->bce_intmask = 975 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 976 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 977 sc->bce_intmask); 978 979 /* start the receive dma */ 980 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 981 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 982 983 /* set media */ 984 if ((error = ether_mediachange(ifp)) != 0) 985 return error; 986 987 /* turn on the ethernet mac */ 988 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 989 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 990 BCE_ENET_CTL) | EC_EE); 991 992 /* start timer */ 993 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 994 995 /* mark as running, and no outputs active */ 996 ifp->if_flags |= IFF_RUNNING; 997 ifp->if_flags &= ~IFF_OACTIVE; 998 999 return 0; 1000 } 1001 1002 /* add a mac address to packet filter */ 1003 void 1004 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1005 { 1006 int i; 1007 uint32_t rval; 1008 1009 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1010 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1011 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1012 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1013 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1014 idx << 16 | 8); /* MAGIC */ 1015 /* wait for write to complete */ 1016 for (i = 0; i < 100; i++) { 1017 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1018 BCE_FILT_CTL); 1019 if (!(rval & 0x80000000)) /* MAGIC */ 1020 break; 1021 delay(10); 1022 } 1023 if (i == 100) { 1024 aprint_error_dev(&sc->bce_dev, 1025 "timed out writing pkt filter ctl\n"); 1026 } 1027 } 1028 1029 /* Add a receive buffer to the indiciated descriptor. */ 1030 static int 1031 bce_add_rxbuf(struct bce_softc *sc, int idx) 1032 { 1033 struct mbuf *m; 1034 int error; 1035 1036 MGETHDR(m, M_DONTWAIT, MT_DATA); 1037 if (m == NULL) 1038 return (ENOBUFS); 1039 1040 MCLGET(m, M_DONTWAIT); 1041 if ((m->m_flags & M_EXT) == 0) { 1042 m_freem(m); 1043 return (ENOBUFS); 1044 } 1045 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1046 bus_dmamap_unload(sc->bce_dmatag, 1047 sc->bce_cdata.bce_rx_map[idx]); 1048 1049 sc->bce_cdata.bce_rx_chain[idx] = m; 1050 1051 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1052 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1053 BUS_DMA_READ | BUS_DMA_NOWAIT); 1054 if (error) 1055 return (error); 1056 1057 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1058 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1059 1060 BCE_INIT_RXDESC(sc, idx); 1061 1062 return (0); 1063 1064 } 1065 1066 /* Drain the receive queue. */ 1067 static void 1068 bce_rxdrain(struct bce_softc *sc) 1069 { 1070 int i; 1071 1072 for (i = 0; i < BCE_NRXDESC; i++) { 1073 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1074 bus_dmamap_unload(sc->bce_dmatag, 1075 sc->bce_cdata.bce_rx_map[i]); 1076 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1077 sc->bce_cdata.bce_rx_chain[i] = NULL; 1078 } 1079 } 1080 } 1081 1082 /* Stop transmission on the interface */ 1083 static void 1084 bce_stop(struct ifnet *ifp, int disable) 1085 { 1086 struct bce_softc *sc = ifp->if_softc; 1087 int i; 1088 uint32_t val; 1089 1090 /* Stop the 1 second timer */ 1091 callout_stop(&sc->bce_timeout); 1092 1093 /* Down the MII. */ 1094 mii_down(&sc->bce_mii); 1095 1096 /* Disable interrupts. */ 1097 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1098 sc->bce_intmask = 0; 1099 delay(10); 1100 1101 /* Disable emac */ 1102 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1103 for (i = 0; i < 200; i++) { 1104 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1105 BCE_ENET_CTL); 1106 if (!(val & EC_ED)) 1107 break; 1108 delay(10); 1109 } 1110 1111 /* Stop the DMA */ 1112 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1113 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1114 delay(10); 1115 1116 /* Release any queued transmit buffers. */ 1117 for (i = 0; i < BCE_NTXDESC; i++) { 1118 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1119 bus_dmamap_unload(sc->bce_dmatag, 1120 sc->bce_cdata.bce_tx_map[i]); 1121 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1122 sc->bce_cdata.bce_tx_chain[i] = NULL; 1123 } 1124 } 1125 1126 /* drain receive queue */ 1127 if (disable) 1128 bce_rxdrain(sc); 1129 1130 /* Mark the interface down and cancel the watchdog timer. */ 1131 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1132 ifp->if_timer = 0; 1133 } 1134 1135 /* reset the chip */ 1136 static void 1137 bce_reset(struct bce_softc *sc) 1138 { 1139 uint32_t val; 1140 uint32_t sbval; 1141 int i; 1142 1143 /* if SB core is up */ 1144 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1145 BCE_SBTMSTATELOW); 1146 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1147 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1148 0); 1149 1150 /* disable emac */ 1151 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1152 EC_ED); 1153 for (i = 0; i < 200; i++) { 1154 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1155 BCE_ENET_CTL); 1156 if (!(val & EC_ED)) 1157 break; 1158 delay(10); 1159 } 1160 if (i == 200) { 1161 aprint_error_dev(&sc->bce_dev, 1162 "timed out disabling ethernet mac\n"); 1163 } 1164 1165 /* reset the dma engines */ 1166 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1167 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1168 /* if error on receive, wait to go idle */ 1169 if (val & RS_ERROR) { 1170 for (i = 0; i < 100; i++) { 1171 val = bus_space_read_4(sc->bce_btag, 1172 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1173 if (val & RS_DMA_IDLE) 1174 break; 1175 delay(10); 1176 } 1177 if (i == 100) { 1178 aprint_error_dev(&sc->bce_dev, 1179 "receive dma did not go idle after" 1180 " error\n"); 1181 } 1182 } 1183 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1184 BCE_DMA_RXSTATUS, 0); 1185 1186 /* reset ethernet mac */ 1187 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1188 EC_ES); 1189 for (i = 0; i < 200; i++) { 1190 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1191 BCE_ENET_CTL); 1192 if (!(val & EC_ES)) 1193 break; 1194 delay(10); 1195 } 1196 if (i == 200) { 1197 aprint_error_dev(&sc->bce_dev, 1198 "timed out resetting ethernet mac\n"); 1199 } 1200 } else { 1201 uint32_t reg_win; 1202 1203 /* remap the pci registers to the Sonics config registers */ 1204 1205 /* save the current map, so it can be restored */ 1206 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1207 BCE_REG_WIN); 1208 /* set register window to Sonics registers */ 1209 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1210 BCE_REG_WIN, BCE_SONICS_WIN); 1211 1212 /* enable SB to PCI interrupt */ 1213 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1214 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1215 BCE_SBINTVEC) | 1216 SBIV_ENET0); 1217 1218 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1219 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1220 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1221 BCE_SPCI_TR2) | 1222 SBTOPCI_PREF | SBTOPCI_BURST); 1223 1224 /* restore to ethernet register space */ 1225 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1226 reg_win); 1227 } 1228 1229 /* disable SB core if not in reset */ 1230 if (!(sbval & SBTML_RESET)) { 1231 1232 /* set the reject bit */ 1233 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1234 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1235 for (i = 0; i < 200; i++) { 1236 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1237 BCE_SBTMSTATELOW); 1238 if (val & SBTML_REJ) 1239 break; 1240 delay(1); 1241 } 1242 if (i == 200) { 1243 aprint_error_dev(&sc->bce_dev, 1244 "while resetting core, reject did not set\n"); 1245 } 1246 /* wait until busy is clear */ 1247 for (i = 0; i < 200; i++) { 1248 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1249 BCE_SBTMSTATEHI); 1250 if (!(val & 0x4)) 1251 break; 1252 delay(1); 1253 } 1254 if (i == 200) { 1255 aprint_error_dev(&sc->bce_dev, 1256 "while resetting core, busy did not clear\n"); 1257 } 1258 /* set reset and reject while enabling the clocks */ 1259 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1260 BCE_SBTMSTATELOW, 1261 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1262 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1263 BCE_SBTMSTATELOW); 1264 delay(10); 1265 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1266 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1267 delay(1); 1268 } 1269 /* enable clock */ 1270 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1271 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1272 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1273 delay(1); 1274 1275 /* clear any error bits that may be on */ 1276 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1277 if (val & 1) 1278 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1279 0); 1280 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1281 if (val & SBIM_MAGIC_ERRORBITS) 1282 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1283 val & ~SBIM_MAGIC_ERRORBITS); 1284 1285 /* clear reset and allow it to propagate throughout the core */ 1286 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1287 SBTML_FGC | SBTML_CLK); 1288 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1289 delay(1); 1290 1291 /* leave clock enabled */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1293 SBTML_CLK); 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1295 delay(1); 1296 1297 /* initialize MDC preamble, frequency */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1299 1300 /* enable phy, differs for internal, and external */ 1301 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1302 if (!(val & BCE_DC_IP)) { 1303 /* select external phy */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1305 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1306 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1307 val & ~BCE_DC_ER); 1308 delay(100); 1309 } 1310 } 1311 1312 /* Set up the receive filter. */ 1313 void 1314 bce_set_filter(struct ifnet *ifp) 1315 { 1316 struct bce_softc *sc = ifp->if_softc; 1317 1318 if (ifp->if_flags & IFF_PROMISC) { 1319 ifp->if_flags |= IFF_ALLMULTI; 1320 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1321 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1322 | ERC_PE); 1323 } else { 1324 ifp->if_flags &= ~IFF_ALLMULTI; 1325 1326 /* turn off promiscuous */ 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1328 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1329 BCE_RX_CTL) & ~ERC_PE); 1330 1331 /* enable/disable broadcast */ 1332 if (ifp->if_flags & IFF_BROADCAST) 1333 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1334 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1335 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1336 else 1337 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1338 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1339 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1340 1341 /* disable the filter */ 1342 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1343 0); 1344 1345 /* add our own address */ 1346 bce_add_mac(sc, sc->enaddr, 0); 1347 1348 /* for now accept all multicast */ 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1350 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1351 ERC_AM); 1352 ifp->if_flags |= IFF_ALLMULTI; 1353 1354 /* enable the filter */ 1355 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1356 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1357 BCE_FILT_CTL) | 1); 1358 } 1359 } 1360 1361 static bool 1362 bce_resume(device_t self PMF_FN_ARGS) 1363 { 1364 struct bce_softc *sc = device_private(self); 1365 1366 bce_reset(sc); 1367 1368 return true; 1369 } 1370 1371 /* Read a PHY register on the MII. */ 1372 int 1373 bce_mii_read(device_t self, int phy, int reg) 1374 { 1375 struct bce_softc *sc = device_private(self); 1376 int i; 1377 uint32_t val; 1378 1379 /* clear mii_int */ 1380 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1381 1382 /* Read the PHY register */ 1383 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1384 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1385 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1386 1387 for (i = 0; i < BCE_TIMEOUT; i++) { 1388 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1389 if (val & BCE_MIINTR) 1390 break; 1391 delay(10); 1392 } 1393 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1394 if (i == BCE_TIMEOUT) { 1395 aprint_error_dev(&sc->bce_dev, 1396 "PHY read timed out reading phy %d, reg %d, val = " 1397 "0x%08x\n", phy, reg, val); 1398 return (0); 1399 } 1400 return (val & BCE_MICOMM_DATA); 1401 } 1402 1403 /* Write a PHY register on the MII */ 1404 void 1405 bce_mii_write(device_t self, int phy, int reg, int val) 1406 { 1407 struct bce_softc *sc = device_private(self); 1408 int i; 1409 uint32_t rval; 1410 1411 /* clear mii_int */ 1412 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1413 BCE_MIINTR); 1414 1415 /* Write the PHY register */ 1416 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1417 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1418 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1419 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1420 1421 /* wait for write to complete */ 1422 for (i = 0; i < BCE_TIMEOUT; i++) { 1423 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1424 BCE_MI_STS); 1425 if (rval & BCE_MIINTR) 1426 break; 1427 delay(10); 1428 } 1429 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1430 if (i == BCE_TIMEOUT) { 1431 aprint_error_dev(&sc->bce_dev, 1432 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1433 reg, val); 1434 } 1435 } 1436 1437 /* sync hardware duplex mode to software state */ 1438 void 1439 bce_statchg(device_t self) 1440 { 1441 struct bce_softc *sc = device_private(self); 1442 uint32_t reg; 1443 1444 /* if needed, change register to match duplex mode */ 1445 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1446 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1447 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1448 reg | EXC_FD); 1449 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1450 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1451 reg & ~EXC_FD); 1452 1453 /* 1454 * Enable activity led. 1455 * XXX This should be in a phy driver, but not currently. 1456 */ 1457 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1458 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1459 /* enable traffic meter led mode */ 1460 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1461 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1462 } 1463 1464 /* One second timer, checks link status */ 1465 static void 1466 bce_tick(void *v) 1467 { 1468 struct bce_softc *sc = v; 1469 1470 /* Tick the MII. */ 1471 mii_tick(&sc->bce_mii); 1472 1473 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1474 } 1475
Indexes created Tue Sep 30 11:09:46 GMT 2025