if_bce.c revision 1.31
1 /* $NetBSD: if_bce.c,v 1.31 2010/02/24 22:38:00 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.31 2010/02/24 22:38:00 dyoung Exp $"); 39 40 #include "vlan.h" 41 #include "rnd.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 #if NRND > 0 60 #include <sys/rnd.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/mii/miidevs.h> 70 #include <dev/mii/brgphyreg.h> 71 72 #include <dev/pci/if_bcereg.h> 73 74 #include <uvm/uvm_extern.h> 75 76 /* transmit buffer max frags allowed */ 77 #define BCE_NTXFRAGS 16 78 79 /* ring descriptor */ 80 struct bce_dma_slot { 81 uint32_t ctrl; 82 uint32_t addr; 83 }; 84 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 85 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 86 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 87 #define CTRL_EOF 0x40000000 /* end of frame */ 88 #define CTRL_SOF 0x80000000 /* start of frame */ 89 90 /* Packet status is returned in a pre-packet header */ 91 struct rx_pph { 92 uint16_t len; 93 uint16_t flags; 94 uint16_t pad[12]; 95 }; 96 97 /* packet status flags bits */ 98 #define RXF_NO 0x8 /* odd number of nibbles */ 99 #define RXF_RXER 0x4 /* receive symbol error */ 100 #define RXF_CRC 0x2 /* crc error */ 101 #define RXF_OV 0x1 /* fifo overflow */ 102 103 /* number of descriptors used in a ring */ 104 #define BCE_NRXDESC 128 105 #define BCE_NTXDESC 128 106 107 /* 108 * Mbuf pointers. We need these to keep track of the virtual addresses 109 * of our mbuf chains since we can only convert from physical to virtual, 110 * not the other way around. 111 */ 112 struct bce_chain_data { 113 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 114 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 115 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 116 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 117 }; 118 119 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 120 121 struct bce_softc { 122 struct device bce_dev; 123 bus_space_tag_t bce_btag; 124 bus_space_handle_t bce_bhandle; 125 bus_dma_tag_t bce_dmatag; 126 struct ethercom ethercom; /* interface info */ 127 void *bce_intrhand; 128 struct pci_attach_args bce_pa; 129 struct mii_data bce_mii; 130 uint32_t bce_phy; /* eeprom indicated phy */ 131 struct ifmedia bce_ifmedia; /* media info *//* Check */ 132 uint8_t enaddr[ETHER_ADDR_LEN]; 133 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 134 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 135 struct bce_chain_data bce_cdata; /* mbufs */ 136 bus_dmamap_t bce_ring_map; 137 uint32_t bce_intmask; /* current intr mask */ 138 uint32_t bce_rxin; /* last rx descriptor seen */ 139 uint32_t bce_txin; /* last tx descriptor seen */ 140 int bce_txsfree; /* no. tx slots available */ 141 int bce_txsnext; /* next available tx slot */ 142 callout_t bce_timeout; 143 #if NRND > 0 144 rndsource_element_t rnd_source; 145 #endif 146 }; 147 148 /* for ring descriptors */ 149 #define BCE_RXBUF_LEN (MCLBYTES - 4) 150 #define BCE_INIT_RXDESC(sc, x) \ 151 do { \ 152 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 153 \ 154 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 155 __bced->addr = \ 156 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 157 + 0x40000000); \ 158 if (x != (BCE_NRXDESC - 1)) \ 159 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 160 else \ 161 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 162 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 163 sizeof(struct bce_dma_slot) * x, \ 164 sizeof(struct bce_dma_slot), \ 165 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 166 } while (/* CONSTCOND */ 0) 167 168 static int bce_probe(device_t, cfdata_t, void *); 169 static void bce_attach(device_t, device_t, void *); 170 static int bce_ioctl(struct ifnet *, u_long, void *); 171 static void bce_start(struct ifnet *); 172 static void bce_watchdog(struct ifnet *); 173 static int bce_intr(void *); 174 static void bce_rxintr(struct bce_softc *); 175 static void bce_txintr(struct bce_softc *); 176 static int bce_init(struct ifnet *); 177 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 178 static int bce_add_rxbuf(struct bce_softc *, int); 179 static void bce_rxdrain(struct bce_softc *); 180 static void bce_stop(struct ifnet *, int); 181 static void bce_reset(struct bce_softc *); 182 static bool bce_resume(device_t, const pmf_qual_t *); 183 static void bce_set_filter(struct ifnet *); 184 static int bce_mii_read(device_t, int, int); 185 static void bce_mii_write(device_t, int, int, int); 186 static void bce_statchg(device_t); 187 static void bce_tick(void *); 188 189 CFATTACH_DECL(bce, sizeof(struct bce_softc), bce_probe, bce_attach, NULL, NULL); 190 191 static const struct bce_product { 192 pci_vendor_id_t bp_vendor; 193 pci_product_id_t bp_product; 194 const char *bp_name; 195 } bce_products[] = { 196 { 197 PCI_VENDOR_BROADCOM, 198 PCI_PRODUCT_BROADCOM_BCM4401, 199 "Broadcom BCM4401 10/100 Ethernet" 200 }, 201 { 202 PCI_VENDOR_BROADCOM, 203 PCI_PRODUCT_BROADCOM_BCM4401_B0, 204 "Broadcom BCM4401-B0 10/100 Ethernet" 205 }, 206 { 207 208 0, 209 0, 210 NULL 211 }, 212 }; 213 214 static const struct bce_product * 215 bce_lookup(const struct pci_attach_args * pa) 216 { 217 const struct bce_product *bp; 218 219 for (bp = bce_products; bp->bp_name != NULL; bp++) { 220 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 221 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 222 return (bp); 223 } 224 225 return (NULL); 226 } 227 228 /* 229 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 230 * against drivers product list, and return its name if a match is found. 231 */ 232 static int 233 bce_probe(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 236 237 if (bce_lookup(pa) != NULL) 238 return (1); 239 240 return (0); 241 } 242 243 static void 244 bce_attach(device_t parent, device_t self, void *aux) 245 { 246 struct bce_softc *sc = device_private(self); 247 struct pci_attach_args *pa = aux; 248 const struct bce_product *bp; 249 pci_chipset_tag_t pc = pa->pa_pc; 250 pci_intr_handle_t ih; 251 const char *intrstr = NULL; 252 uint32_t command; 253 pcireg_t memtype, pmode; 254 bus_addr_t memaddr; 255 bus_size_t memsize; 256 void *kva; 257 bus_dma_segment_t seg; 258 int error, i, pmreg, rseg; 259 struct ifnet *ifp; 260 261 bp = bce_lookup(pa); 262 KASSERT(bp != NULL); 263 264 sc->bce_pa = *pa; 265 266 /* BCM440x can only address 30 bits (1GB) */ 267 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 268 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 269 aprint_error_dev(self, 270 "WARNING: failed to restrict dma range," 271 " falling back to parent bus dma range\n"); 272 sc->bce_dmatag = pa->pa_dmat; 273 } 274 275 aprint_naive(": Ethernet controller\n"); 276 aprint_normal(": %s\n", bp->bp_name); 277 278 /* 279 * Map control/status registers. 280 */ 281 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 282 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 283 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 284 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 285 286 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 287 aprint_error_dev(self, "failed to enable memory mapping!\n"); 288 return; 289 } 290 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 291 switch (memtype) { 292 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 293 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 294 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 295 &sc->bce_bhandle, &memaddr, &memsize) == 0) 296 break; 297 default: 298 aprint_error_dev(self, "unable to find mem space\n"); 299 return; 300 } 301 302 /* Get it out of power save mode if needed. */ 303 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 304 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 305 if (pmode == 3) { 306 /* 307 * The card has lost all configuration data in 308 * this state, so punt. 309 */ 310 aprint_error_dev(self, 311 "unable to wake up from power state D3\n"); 312 return; 313 } 314 if (pmode != 0) { 315 aprint_normal_dev(self, 316 "waking up from power state D%d\n", pmode); 317 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 318 } 319 } 320 if (pci_intr_map(pa, &ih)) { 321 aprint_error_dev(self, "couldn't map interrupt\n"); 322 return; 323 } 324 intrstr = pci_intr_string(pc, ih); 325 326 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 327 328 if (sc->bce_intrhand == NULL) { 329 aprint_error_dev(self, "couldn't establish interrupt\n"); 330 if (intrstr != NULL) 331 aprint_error(" at %s", intrstr); 332 aprint_error("\n"); 333 return; 334 } 335 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 336 337 /* reset the chip */ 338 bce_reset(sc); 339 340 /* 341 * Allocate DMA-safe memory for ring descriptors. 342 * The receive, and transmit rings can not share the same 343 * 4k space, however both are allocated at once here. 344 */ 345 /* 346 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 347 * due to the limition above. ?? 348 */ 349 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 350 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 351 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 352 aprint_error_dev(self, 353 "unable to alloc space for ring descriptors, error = %d\n", 354 error); 355 return; 356 } 357 /* map ring space to kernel */ 358 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 359 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 360 aprint_error_dev(self, 361 "unable to map DMA buffers, error = %d\n", error); 362 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 363 return; 364 } 365 /* create a dma map for the ring */ 366 if ((error = bus_dmamap_create(sc->bce_dmatag, 367 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 368 &sc->bce_ring_map))) { 369 aprint_error_dev(self, 370 "unable to create ring DMA map, error = %d\n", error); 371 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 372 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 373 return; 374 } 375 /* connect the ring space to the dma map */ 376 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 377 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 378 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 379 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 380 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 381 return; 382 } 383 /* save the ring space in softc */ 384 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 385 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 386 387 /* Create the transmit buffer DMA maps. */ 388 for (i = 0; i < BCE_NTXDESC; i++) { 389 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 390 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 391 aprint_error_dev(self, 392 "unable to create tx DMA map, error = %d\n", error); 393 } 394 sc->bce_cdata.bce_tx_chain[i] = NULL; 395 } 396 397 /* Create the receive buffer DMA maps. */ 398 for (i = 0; i < BCE_NRXDESC; i++) { 399 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 400 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 401 aprint_error_dev(self, 402 "unable to create rx DMA map, error = %d\n", error); 403 } 404 sc->bce_cdata.bce_rx_chain[i] = NULL; 405 } 406 407 /* Set up ifnet structure */ 408 ifp = &sc->ethercom.ec_if; 409 strcpy(ifp->if_xname, device_xname(self)); 410 ifp->if_softc = sc; 411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 412 ifp->if_ioctl = bce_ioctl; 413 ifp->if_start = bce_start; 414 ifp->if_watchdog = bce_watchdog; 415 ifp->if_init = bce_init; 416 ifp->if_stop = bce_stop; 417 IFQ_SET_READY(&ifp->if_snd); 418 419 /* Initialize our media structures and probe the MII. */ 420 421 sc->bce_mii.mii_ifp = ifp; 422 sc->bce_mii.mii_readreg = bce_mii_read; 423 sc->bce_mii.mii_writereg = bce_mii_write; 424 sc->bce_mii.mii_statchg = bce_statchg; 425 426 sc->ethercom.ec_mii = &sc->bce_mii; 427 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 428 ether_mediastatus); 429 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 431 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 432 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 433 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 434 } else 435 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 436 /* get the phy */ 437 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 438 BCE_MAGIC_PHY) & 0x1f; 439 /* 440 * Enable activity led. 441 * XXX This should be in a phy driver, but not currently. 442 */ 443 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 444 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 445 /* enable traffic meter led mode */ 446 bce_mii_write(&sc->bce_dev, 1, 27, /* MAGIC */ 447 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 448 449 /* Attach the interface */ 450 if_attach(ifp); 451 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 452 BCE_MAGIC_ENET0); 453 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 454 BCE_MAGIC_ENET1); 455 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 456 BCE_MAGIC_ENET2); 457 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 458 BCE_MAGIC_ENET3); 459 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 460 BCE_MAGIC_ENET4); 461 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 462 BCE_MAGIC_ENET5); 463 aprint_normal_dev(self, "Ethernet address %s\n", 464 ether_sprintf(sc->enaddr)); 465 ether_ifattach(ifp, sc->enaddr); 466 #if NRND > 0 467 rnd_attach_source(&sc->rnd_source, device_xname(self), 468 RND_TYPE_NET, 0); 469 #endif 470 callout_init(&sc->bce_timeout, 0); 471 472 if (pmf_device_register(self, NULL, bce_resume)) 473 pmf_class_network_register(self, ifp); 474 else 475 aprint_error_dev(self, "couldn't establish power handler\n"); 476 } 477 478 /* handle media, and ethernet requests */ 479 static int 480 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 481 { 482 int s, error; 483 484 s = splnet(); 485 error = ether_ioctl(ifp, cmd, data); 486 if (error == ENETRESET) { 487 /* change multicast list */ 488 error = 0; 489 } 490 491 /* Try to get more packets going. */ 492 bce_start(ifp); 493 494 splx(s); 495 return error; 496 } 497 498 /* Start packet transmission on the interface. */ 499 static void 500 bce_start(struct ifnet *ifp) 501 { 502 struct bce_softc *sc = ifp->if_softc; 503 struct mbuf *m0; 504 bus_dmamap_t dmamap; 505 int txstart; 506 int txsfree; 507 int newpkts = 0; 508 int error; 509 510 /* 511 * do not start another if currently transmitting, and more 512 * descriptors(tx slots) are needed for next packet. 513 */ 514 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 515 return; 516 517 /* determine number of descriptors available */ 518 if (sc->bce_txsnext >= sc->bce_txin) 519 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 520 else 521 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 522 523 /* 524 * Loop through the send queue, setting up transmit descriptors 525 * until we drain the queue, or use up all available transmit 526 * descriptors. 527 */ 528 while (txsfree > 0) { 529 int seg; 530 531 /* Grab a packet off the queue. */ 532 IFQ_POLL(&ifp->if_snd, m0); 533 if (m0 == NULL) 534 break; 535 536 /* get the transmit slot dma map */ 537 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 538 539 /* 540 * Load the DMA map. If this fails, the packet either 541 * didn't fit in the alloted number of segments, or we 542 * were short on resources. If the packet will not fit, 543 * it will be dropped. If short on resources, it will 544 * be tried again later. 545 */ 546 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 547 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 548 if (error == EFBIG) { 549 aprint_error_dev(&sc->bce_dev, 550 "Tx packet consumes too many DMA segments, " 551 "dropping...\n"); 552 IFQ_DEQUEUE(&ifp->if_snd, m0); 553 m_freem(m0); 554 ifp->if_oerrors++; 555 continue; 556 } else if (error) { 557 /* short on resources, come back later */ 558 aprint_error_dev(&sc->bce_dev, 559 "unable to load Tx buffer, error = %d\n", 560 error); 561 break; 562 } 563 /* If not enough descriptors available, try again later */ 564 if (dmamap->dm_nsegs > txsfree) { 565 ifp->if_flags |= IFF_OACTIVE; 566 bus_dmamap_unload(sc->bce_dmatag, dmamap); 567 break; 568 } 569 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 570 571 /* So take it off the queue */ 572 IFQ_DEQUEUE(&ifp->if_snd, m0); 573 574 /* save the pointer so it can be freed later */ 575 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 576 577 /* Sync the data DMA map. */ 578 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 579 BUS_DMASYNC_PREWRITE); 580 581 /* Initialize the transmit descriptor(s). */ 582 txstart = sc->bce_txsnext; 583 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 584 uint32_t ctrl; 585 586 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 587 if (seg == 0) 588 ctrl |= CTRL_SOF; 589 if (seg == dmamap->dm_nsegs - 1) 590 ctrl |= CTRL_EOF; 591 if (sc->bce_txsnext == BCE_NTXDESC - 1) 592 ctrl |= CTRL_EOT; 593 ctrl |= CTRL_IOC; 594 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 595 sc->bce_tx_ring[sc->bce_txsnext].addr = 596 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 597 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 598 sc->bce_txsnext = 0; 599 else 600 sc->bce_txsnext++; 601 txsfree--; 602 } 603 /* sync descriptors being used */ 604 if ( sc->bce_txsnext > txstart ) { 605 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 606 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 607 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 609 } else { 610 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 611 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 612 sizeof(struct bce_dma_slot) * 613 (BCE_NTXDESC - txstart), 614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 615 if ( sc->bce_txsnext != 0 ) { 616 bus_dmamap_sync(sc->bce_dmatag, 617 sc->bce_ring_map, PAGE_SIZE, 618 sc->bce_txsnext * 619 sizeof(struct bce_dma_slot), 620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 621 } 622 } 623 624 /* Give the packet to the chip. */ 625 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 626 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 627 628 newpkts++; 629 630 /* Pass the packet to any BPF listeners. */ 631 if (ifp->if_bpf) 632 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 633 } 634 if (txsfree == 0) { 635 /* No more slots left; notify upper layer. */ 636 ifp->if_flags |= IFF_OACTIVE; 637 } 638 if (newpkts) { 639 /* Set a watchdog timer in case the chip flakes out. */ 640 ifp->if_timer = 5; 641 } 642 } 643 644 /* Watchdog timer handler. */ 645 static void 646 bce_watchdog(struct ifnet *ifp) 647 { 648 struct bce_softc *sc = ifp->if_softc; 649 650 aprint_error_dev(&sc->bce_dev, "device timeout\n"); 651 ifp->if_oerrors++; 652 653 (void) bce_init(ifp); 654 655 /* Try to get more packets going. */ 656 bce_start(ifp); 657 } 658 659 int 660 bce_intr(void *xsc) 661 { 662 struct bce_softc *sc; 663 struct ifnet *ifp; 664 uint32_t intstatus; 665 int wantinit; 666 int handled = 0; 667 668 sc = xsc; 669 ifp = &sc->ethercom.ec_if; 670 671 for (wantinit = 0; wantinit == 0;) { 672 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 673 BCE_INT_STS); 674 675 /* ignore if not ours, or unsolicited interrupts */ 676 intstatus &= sc->bce_intmask; 677 if (intstatus == 0) 678 break; 679 680 handled = 1; 681 682 /* Ack interrupt */ 683 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 684 intstatus); 685 686 /* Receive interrupts. */ 687 if (intstatus & I_RI) 688 bce_rxintr(sc); 689 /* Transmit interrupts. */ 690 if (intstatus & I_XI) 691 bce_txintr(sc); 692 /* Error interrupts */ 693 if (intstatus & ~(I_RI | I_XI)) { 694 const char *msg = NULL; 695 if (intstatus & I_XU) 696 msg = "transmit fifo underflow"; 697 if (intstatus & I_RO) { 698 msg = "receive fifo overflow"; 699 ifp->if_ierrors++; 700 } 701 if (intstatus & I_RU) 702 msg = "receive descriptor underflow"; 703 if (intstatus & I_DE) 704 msg = "descriptor protocol error"; 705 if (intstatus & I_PD) 706 msg = "data error"; 707 if (intstatus & I_PC) 708 msg = "descriptor error"; 709 if (intstatus & I_TO) 710 msg = "general purpose timeout"; 711 if (msg != NULL) 712 aprint_error_dev(&sc->bce_dev, "%s\n", msg); 713 wantinit = 1; 714 } 715 } 716 717 if (handled) { 718 if (wantinit) 719 bce_init(ifp); 720 #if NRND > 0 721 if (RND_ENABLED(&sc->rnd_source)) 722 rnd_add_uint32(&sc->rnd_source, intstatus); 723 #endif 724 /* Try to get more packets going. */ 725 bce_start(ifp); 726 } 727 return (handled); 728 } 729 730 /* Receive interrupt handler */ 731 void 732 bce_rxintr(struct bce_softc *sc) 733 { 734 struct ifnet *ifp = &sc->ethercom.ec_if; 735 struct rx_pph *pph; 736 struct mbuf *m; 737 int curr; 738 int len; 739 int i; 740 741 /* get pointer to active receive slot */ 742 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 743 & RS_CD_MASK; 744 curr = curr / sizeof(struct bce_dma_slot); 745 if (curr >= BCE_NRXDESC) 746 curr = BCE_NRXDESC - 1; 747 748 /* process packets up to but not current packet being worked on */ 749 for (i = sc->bce_rxin; i != curr; 750 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 751 /* complete any post dma memory ops on packet */ 752 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 753 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 754 BUS_DMASYNC_POSTREAD); 755 756 /* 757 * If the packet had an error, simply recycle the buffer, 758 * resetting the len, and flags. 759 */ 760 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 761 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 762 ifp->if_ierrors++; 763 pph->len = 0; 764 pph->flags = 0; 765 continue; 766 } 767 /* receive the packet */ 768 len = pph->len; 769 if (len == 0) 770 continue; /* no packet if empty */ 771 pph->len = 0; 772 pph->flags = 0; 773 /* bump past pre header to packet */ 774 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 775 776 /* 777 * The chip includes the CRC with every packet. Trim 778 * it off here. 779 */ 780 len -= ETHER_CRC_LEN; 781 782 /* 783 * If the packet is small enough to fit in a 784 * single header mbuf, allocate one and copy 785 * the data into it. This greatly reduces 786 * memory consumption when receiving lots 787 * of small packets. 788 * 789 * Otherwise, add a new buffer to the receive 790 * chain. If this fails, drop the packet and 791 * recycle the old buffer. 792 */ 793 if (len <= (MHLEN - 2)) { 794 MGETHDR(m, M_DONTWAIT, MT_DATA); 795 if (m == NULL) 796 goto dropit; 797 m->m_data += 2; 798 memcpy(mtod(m, void *), 799 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 800 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 801 } else { 802 m = sc->bce_cdata.bce_rx_chain[i]; 803 if (bce_add_rxbuf(sc, i) != 0) { 804 dropit: 805 ifp->if_ierrors++; 806 /* continue to use old buffer */ 807 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 808 bus_dmamap_sync(sc->bce_dmatag, 809 sc->bce_cdata.bce_rx_map[i], 0, 810 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 811 BUS_DMASYNC_PREREAD); 812 continue; 813 } 814 } 815 816 m->m_pkthdr.rcvif = ifp; 817 m->m_pkthdr.len = m->m_len = len; 818 ifp->if_ipackets++; 819 820 /* 821 * Pass this up to any BPF listeners, but only 822 * pass it up the stack if it's for us. 823 */ 824 if (ifp->if_bpf) 825 bpf_ops->bpf_mtap(ifp->if_bpf, m); 826 827 /* Pass it on. */ 828 (*ifp->if_input) (ifp, m); 829 830 /* re-check current in case it changed */ 831 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 832 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 833 sizeof(struct bce_dma_slot); 834 if (curr >= BCE_NRXDESC) 835 curr = BCE_NRXDESC - 1; 836 } 837 sc->bce_rxin = curr; 838 } 839 840 /* Transmit interrupt handler */ 841 void 842 bce_txintr(struct bce_softc *sc) 843 { 844 struct ifnet *ifp = &sc->ethercom.ec_if; 845 int curr; 846 int i; 847 848 ifp->if_flags &= ~IFF_OACTIVE; 849 850 /* 851 * Go through the Tx list and free mbufs for those 852 * frames which have been transmitted. 853 */ 854 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 855 RS_CD_MASK; 856 curr = curr / sizeof(struct bce_dma_slot); 857 if (curr >= BCE_NTXDESC) 858 curr = BCE_NTXDESC - 1; 859 for (i = sc->bce_txin; i != curr; 860 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 861 /* do any post dma memory ops on transmit data */ 862 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 863 continue; 864 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 865 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 866 BUS_DMASYNC_POSTWRITE); 867 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 868 m_freem(sc->bce_cdata.bce_tx_chain[i]); 869 sc->bce_cdata.bce_tx_chain[i] = NULL; 870 ifp->if_opackets++; 871 } 872 sc->bce_txin = curr; 873 874 /* 875 * If there are no more pending transmissions, cancel the watchdog 876 * timer 877 */ 878 if (sc->bce_txsnext == sc->bce_txin) 879 ifp->if_timer = 0; 880 } 881 882 /* initialize the interface */ 883 static int 884 bce_init(struct ifnet *ifp) 885 { 886 struct bce_softc *sc = ifp->if_softc; 887 uint32_t reg_win; 888 int error; 889 int i; 890 891 /* Cancel any pending I/O. */ 892 bce_stop(ifp, 0); 893 894 /* enable pci inerrupts, bursts, and prefetch */ 895 896 /* remap the pci registers to the Sonics config registers */ 897 898 /* save the current map, so it can be restored */ 899 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 900 BCE_REG_WIN); 901 902 /* set register window to Sonics registers */ 903 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 904 BCE_SONICS_WIN); 905 906 /* enable SB to PCI interrupt */ 907 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 908 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 909 SBIV_ENET0); 910 911 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 912 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 913 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 914 SBTOPCI_PREF | SBTOPCI_BURST); 915 916 /* restore to ethernet register space */ 917 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 918 reg_win); 919 920 /* Reset the chip to a known state. */ 921 bce_reset(sc); 922 923 /* Initialize transmit descriptors */ 924 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 925 sc->bce_txsnext = 0; 926 sc->bce_txin = 0; 927 928 /* enable crc32 generation */ 929 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 930 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 931 BCE_EMC_CG); 932 933 /* setup DMA interrupt control */ 934 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 935 936 /* setup packet filter */ 937 bce_set_filter(ifp); 938 939 /* set max frame length, account for possible vlan tag */ 940 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 941 ETHER_MAX_LEN + 32); 942 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 943 ETHER_MAX_LEN + 32); 944 945 /* set tx watermark */ 946 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 947 948 /* enable transmit */ 949 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 951 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 952 953 /* 954 * Give the receive ring to the chip, and 955 * start the receive DMA engine. 956 */ 957 sc->bce_rxin = 0; 958 959 /* clear the rx descriptor ring */ 960 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 961 /* enable receive */ 962 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 963 30 << 1 | 1); /* MAGIC */ 964 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 965 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 966 967 /* Initalize receive descriptors */ 968 for (i = 0; i < BCE_NRXDESC; i++) { 969 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 970 if ((error = bce_add_rxbuf(sc, i)) != 0) { 971 aprint_error_dev(&sc->bce_dev, 972 "unable to allocate or map rx(%d) " 973 "mbuf, error = %d\n", i, error); 974 bce_rxdrain(sc); 975 return (error); 976 } 977 } else 978 BCE_INIT_RXDESC(sc, i); 979 } 980 981 /* Enable interrupts */ 982 sc->bce_intmask = 983 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 984 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 985 sc->bce_intmask); 986 987 /* start the receive dma */ 988 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 989 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 990 991 /* set media */ 992 if ((error = ether_mediachange(ifp)) != 0) 993 return error; 994 995 /* turn on the ethernet mac */ 996 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 997 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 998 BCE_ENET_CTL) | EC_EE); 999 1000 /* start timer */ 1001 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1002 1003 /* mark as running, and no outputs active */ 1004 ifp->if_flags |= IFF_RUNNING; 1005 ifp->if_flags &= ~IFF_OACTIVE; 1006 1007 return 0; 1008 } 1009 1010 /* add a mac address to packet filter */ 1011 void 1012 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1013 { 1014 int i; 1015 uint32_t rval; 1016 1017 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1018 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1019 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1020 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1021 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1022 idx << 16 | 8); /* MAGIC */ 1023 /* wait for write to complete */ 1024 for (i = 0; i < 100; i++) { 1025 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1026 BCE_FILT_CTL); 1027 if (!(rval & 0x80000000)) /* MAGIC */ 1028 break; 1029 delay(10); 1030 } 1031 if (i == 100) { 1032 aprint_error_dev(&sc->bce_dev, 1033 "timed out writing pkt filter ctl\n"); 1034 } 1035 } 1036 1037 /* Add a receive buffer to the indiciated descriptor. */ 1038 static int 1039 bce_add_rxbuf(struct bce_softc *sc, int idx) 1040 { 1041 struct mbuf *m; 1042 int error; 1043 1044 MGETHDR(m, M_DONTWAIT, MT_DATA); 1045 if (m == NULL) 1046 return (ENOBUFS); 1047 1048 MCLGET(m, M_DONTWAIT); 1049 if ((m->m_flags & M_EXT) == 0) { 1050 m_freem(m); 1051 return (ENOBUFS); 1052 } 1053 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1054 bus_dmamap_unload(sc->bce_dmatag, 1055 sc->bce_cdata.bce_rx_map[idx]); 1056 1057 sc->bce_cdata.bce_rx_chain[idx] = m; 1058 1059 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1060 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1061 BUS_DMA_READ | BUS_DMA_NOWAIT); 1062 if (error) 1063 return (error); 1064 1065 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1066 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1067 1068 BCE_INIT_RXDESC(sc, idx); 1069 1070 return (0); 1071 1072 } 1073 1074 /* Drain the receive queue. */ 1075 static void 1076 bce_rxdrain(struct bce_softc *sc) 1077 { 1078 int i; 1079 1080 for (i = 0; i < BCE_NRXDESC; i++) { 1081 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1082 bus_dmamap_unload(sc->bce_dmatag, 1083 sc->bce_cdata.bce_rx_map[i]); 1084 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1085 sc->bce_cdata.bce_rx_chain[i] = NULL; 1086 } 1087 } 1088 } 1089 1090 /* Stop transmission on the interface */ 1091 static void 1092 bce_stop(struct ifnet *ifp, int disable) 1093 { 1094 struct bce_softc *sc = ifp->if_softc; 1095 int i; 1096 uint32_t val; 1097 1098 /* Stop the 1 second timer */ 1099 callout_stop(&sc->bce_timeout); 1100 1101 /* Down the MII. */ 1102 mii_down(&sc->bce_mii); 1103 1104 /* Disable interrupts. */ 1105 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1106 sc->bce_intmask = 0; 1107 delay(10); 1108 1109 /* Disable emac */ 1110 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1111 for (i = 0; i < 200; i++) { 1112 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1113 BCE_ENET_CTL); 1114 if (!(val & EC_ED)) 1115 break; 1116 delay(10); 1117 } 1118 1119 /* Stop the DMA */ 1120 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1121 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1122 delay(10); 1123 1124 /* Release any queued transmit buffers. */ 1125 for (i = 0; i < BCE_NTXDESC; i++) { 1126 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1127 bus_dmamap_unload(sc->bce_dmatag, 1128 sc->bce_cdata.bce_tx_map[i]); 1129 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1130 sc->bce_cdata.bce_tx_chain[i] = NULL; 1131 } 1132 } 1133 1134 /* Mark the interface down and cancel the watchdog timer. */ 1135 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1136 ifp->if_timer = 0; 1137 1138 /* drain receive queue */ 1139 if (disable) 1140 bce_rxdrain(sc); 1141 } 1142 1143 /* reset the chip */ 1144 static void 1145 bce_reset(struct bce_softc *sc) 1146 { 1147 uint32_t val; 1148 uint32_t sbval; 1149 int i; 1150 1151 /* if SB core is up */ 1152 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1153 BCE_SBTMSTATELOW); 1154 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1155 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1156 0); 1157 1158 /* disable emac */ 1159 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1160 EC_ED); 1161 for (i = 0; i < 200; i++) { 1162 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1163 BCE_ENET_CTL); 1164 if (!(val & EC_ED)) 1165 break; 1166 delay(10); 1167 } 1168 if (i == 200) { 1169 aprint_error_dev(&sc->bce_dev, 1170 "timed out disabling ethernet mac\n"); 1171 } 1172 1173 /* reset the dma engines */ 1174 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1175 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1176 /* if error on receive, wait to go idle */ 1177 if (val & RS_ERROR) { 1178 for (i = 0; i < 100; i++) { 1179 val = bus_space_read_4(sc->bce_btag, 1180 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1181 if (val & RS_DMA_IDLE) 1182 break; 1183 delay(10); 1184 } 1185 if (i == 100) { 1186 aprint_error_dev(&sc->bce_dev, 1187 "receive dma did not go idle after" 1188 " error\n"); 1189 } 1190 } 1191 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1192 BCE_DMA_RXSTATUS, 0); 1193 1194 /* reset ethernet mac */ 1195 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1196 EC_ES); 1197 for (i = 0; i < 200; i++) { 1198 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1199 BCE_ENET_CTL); 1200 if (!(val & EC_ES)) 1201 break; 1202 delay(10); 1203 } 1204 if (i == 200) { 1205 aprint_error_dev(&sc->bce_dev, 1206 "timed out resetting ethernet mac\n"); 1207 } 1208 } else { 1209 uint32_t reg_win; 1210 1211 /* remap the pci registers to the Sonics config registers */ 1212 1213 /* save the current map, so it can be restored */ 1214 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1215 BCE_REG_WIN); 1216 /* set register window to Sonics registers */ 1217 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1218 BCE_REG_WIN, BCE_SONICS_WIN); 1219 1220 /* enable SB to PCI interrupt */ 1221 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1222 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1223 BCE_SBINTVEC) | 1224 SBIV_ENET0); 1225 1226 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1227 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1228 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1229 BCE_SPCI_TR2) | 1230 SBTOPCI_PREF | SBTOPCI_BURST); 1231 1232 /* restore to ethernet register space */ 1233 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1234 reg_win); 1235 } 1236 1237 /* disable SB core if not in reset */ 1238 if (!(sbval & SBTML_RESET)) { 1239 1240 /* set the reject bit */ 1241 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1242 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1243 for (i = 0; i < 200; i++) { 1244 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1245 BCE_SBTMSTATELOW); 1246 if (val & SBTML_REJ) 1247 break; 1248 delay(1); 1249 } 1250 if (i == 200) { 1251 aprint_error_dev(&sc->bce_dev, 1252 "while resetting core, reject did not set\n"); 1253 } 1254 /* wait until busy is clear */ 1255 for (i = 0; i < 200; i++) { 1256 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1257 BCE_SBTMSTATEHI); 1258 if (!(val & 0x4)) 1259 break; 1260 delay(1); 1261 } 1262 if (i == 200) { 1263 aprint_error_dev(&sc->bce_dev, 1264 "while resetting core, busy did not clear\n"); 1265 } 1266 /* set reset and reject while enabling the clocks */ 1267 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1268 BCE_SBTMSTATELOW, 1269 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1270 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1271 BCE_SBTMSTATELOW); 1272 delay(10); 1273 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1274 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1275 delay(1); 1276 } 1277 /* enable clock */ 1278 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1279 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1280 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1281 delay(1); 1282 1283 /* clear any error bits that may be on */ 1284 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1285 if (val & 1) 1286 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1287 0); 1288 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1289 if (val & SBIM_MAGIC_ERRORBITS) 1290 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1291 val & ~SBIM_MAGIC_ERRORBITS); 1292 1293 /* clear reset and allow it to propagate throughout the core */ 1294 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1295 SBTML_FGC | SBTML_CLK); 1296 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1297 delay(1); 1298 1299 /* leave clock enabled */ 1300 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1301 SBTML_CLK); 1302 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1303 delay(1); 1304 1305 /* initialize MDC preamble, frequency */ 1306 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1307 1308 /* enable phy, differs for internal, and external */ 1309 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1310 if (!(val & BCE_DC_IP)) { 1311 /* select external phy */ 1312 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1313 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1314 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1315 val & ~BCE_DC_ER); 1316 delay(100); 1317 } 1318 } 1319 1320 /* Set up the receive filter. */ 1321 void 1322 bce_set_filter(struct ifnet *ifp) 1323 { 1324 struct bce_softc *sc = ifp->if_softc; 1325 1326 if (ifp->if_flags & IFF_PROMISC) { 1327 ifp->if_flags |= IFF_ALLMULTI; 1328 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1329 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1330 | ERC_PE); 1331 } else { 1332 ifp->if_flags &= ~IFF_ALLMULTI; 1333 1334 /* turn off promiscuous */ 1335 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1336 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1337 BCE_RX_CTL) & ~ERC_PE); 1338 1339 /* enable/disable broadcast */ 1340 if (ifp->if_flags & IFF_BROADCAST) 1341 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1342 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1343 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1344 else 1345 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1346 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1347 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1348 1349 /* disable the filter */ 1350 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1351 0); 1352 1353 /* add our own address */ 1354 bce_add_mac(sc, sc->enaddr, 0); 1355 1356 /* for now accept all multicast */ 1357 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1358 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1359 ERC_AM); 1360 ifp->if_flags |= IFF_ALLMULTI; 1361 1362 /* enable the filter */ 1363 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1364 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1365 BCE_FILT_CTL) | 1); 1366 } 1367 } 1368 1369 static bool 1370 bce_resume(device_t self, const pmf_qual_t *qual) 1371 { 1372 struct bce_softc *sc = device_private(self); 1373 1374 bce_reset(sc); 1375 1376 return true; 1377 } 1378 1379 /* Read a PHY register on the MII. */ 1380 int 1381 bce_mii_read(device_t self, int phy, int reg) 1382 { 1383 struct bce_softc *sc = device_private(self); 1384 int i; 1385 uint32_t val; 1386 1387 /* clear mii_int */ 1388 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1389 1390 /* Read the PHY register */ 1391 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1392 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1393 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1394 1395 for (i = 0; i < BCE_TIMEOUT; i++) { 1396 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1397 if (val & BCE_MIINTR) 1398 break; 1399 delay(10); 1400 } 1401 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1402 if (i == BCE_TIMEOUT) { 1403 aprint_error_dev(&sc->bce_dev, 1404 "PHY read timed out reading phy %d, reg %d, val = " 1405 "0x%08x\n", phy, reg, val); 1406 return (0); 1407 } 1408 return (val & BCE_MICOMM_DATA); 1409 } 1410 1411 /* Write a PHY register on the MII */ 1412 void 1413 bce_mii_write(device_t self, int phy, int reg, int val) 1414 { 1415 struct bce_softc *sc = device_private(self); 1416 int i; 1417 uint32_t rval; 1418 1419 /* clear mii_int */ 1420 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1421 BCE_MIINTR); 1422 1423 /* Write the PHY register */ 1424 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1425 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1426 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1427 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1428 1429 /* wait for write to complete */ 1430 for (i = 0; i < BCE_TIMEOUT; i++) { 1431 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1432 BCE_MI_STS); 1433 if (rval & BCE_MIINTR) 1434 break; 1435 delay(10); 1436 } 1437 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1438 if (i == BCE_TIMEOUT) { 1439 aprint_error_dev(&sc->bce_dev, 1440 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1441 reg, val); 1442 } 1443 } 1444 1445 /* sync hardware duplex mode to software state */ 1446 void 1447 bce_statchg(device_t self) 1448 { 1449 struct bce_softc *sc = device_private(self); 1450 uint32_t reg; 1451 1452 /* if needed, change register to match duplex mode */ 1453 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1454 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1455 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1456 reg | EXC_FD); 1457 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1458 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1459 reg & ~EXC_FD); 1460 1461 /* 1462 * Enable activity led. 1463 * XXX This should be in a phy driver, but not currently. 1464 */ 1465 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1466 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1467 /* enable traffic meter led mode */ 1468 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1469 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1470 } 1471 1472 /* One second timer, checks link status */ 1473 static void 1474 bce_tick(void *v) 1475 { 1476 struct bce_softc *sc = v; 1477 1478 /* Tick the MII. */ 1479 mii_tick(&sc->bce_mii); 1480 1481 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1482 } 1483
Indexes created Tue Sep 30 17:09:57 GMT 2025