if_bce.c revision 1.32
1 /* $NetBSD: if_bce.c,v 1.32 2010/04/05 07:20:25 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.32 2010/04/05 07:20:25 joerg Exp $"); 39 40 #include "vlan.h" 41 #include "rnd.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 #if NRND > 0 60 #include <sys/rnd.h> 61 #endif 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/mii/miidevs.h> 70 #include <dev/mii/brgphyreg.h> 71 72 #include <dev/pci/if_bcereg.h> 73 74 #include <uvm/uvm_extern.h> 75 76 /* transmit buffer max frags allowed */ 77 #define BCE_NTXFRAGS 16 78 79 /* ring descriptor */ 80 struct bce_dma_slot { 81 uint32_t ctrl; 82 uint32_t addr; 83 }; 84 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 85 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 86 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 87 #define CTRL_EOF 0x40000000 /* end of frame */ 88 #define CTRL_SOF 0x80000000 /* start of frame */ 89 90 /* Packet status is returned in a pre-packet header */ 91 struct rx_pph { 92 uint16_t len; 93 uint16_t flags; 94 uint16_t pad[12]; 95 }; 96 97 /* packet status flags bits */ 98 #define RXF_NO 0x8 /* odd number of nibbles */ 99 #define RXF_RXER 0x4 /* receive symbol error */ 100 #define RXF_CRC 0x2 /* crc error */ 101 #define RXF_OV 0x1 /* fifo overflow */ 102 103 /* number of descriptors used in a ring */ 104 #define BCE_NRXDESC 128 105 #define BCE_NTXDESC 128 106 107 /* 108 * Mbuf pointers. We need these to keep track of the virtual addresses 109 * of our mbuf chains since we can only convert from physical to virtual, 110 * not the other way around. 111 */ 112 struct bce_chain_data { 113 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 114 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 115 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 116 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 117 }; 118 119 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 120 121 struct bce_softc { 122 struct device bce_dev; 123 bus_space_tag_t bce_btag; 124 bus_space_handle_t bce_bhandle; 125 bus_dma_tag_t bce_dmatag; 126 struct ethercom ethercom; /* interface info */ 127 void *bce_intrhand; 128 struct pci_attach_args bce_pa; 129 struct mii_data bce_mii; 130 uint32_t bce_phy; /* eeprom indicated phy */ 131 struct ifmedia bce_ifmedia; /* media info *//* Check */ 132 uint8_t enaddr[ETHER_ADDR_LEN]; 133 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 134 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 135 struct bce_chain_data bce_cdata; /* mbufs */ 136 bus_dmamap_t bce_ring_map; 137 uint32_t bce_intmask; /* current intr mask */ 138 uint32_t bce_rxin; /* last rx descriptor seen */ 139 uint32_t bce_txin; /* last tx descriptor seen */ 140 int bce_txsfree; /* no. tx slots available */ 141 int bce_txsnext; /* next available tx slot */ 142 callout_t bce_timeout; 143 #if NRND > 0 144 rndsource_element_t rnd_source; 145 #endif 146 }; 147 148 /* for ring descriptors */ 149 #define BCE_RXBUF_LEN (MCLBYTES - 4) 150 #define BCE_INIT_RXDESC(sc, x) \ 151 do { \ 152 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 153 \ 154 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 155 __bced->addr = \ 156 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 157 + 0x40000000); \ 158 if (x != (BCE_NRXDESC - 1)) \ 159 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 160 else \ 161 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 162 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 163 sizeof(struct bce_dma_slot) * x, \ 164 sizeof(struct bce_dma_slot), \ 165 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 166 } while (/* CONSTCOND */ 0) 167 168 static int bce_probe(device_t, cfdata_t, void *); 169 static void bce_attach(device_t, device_t, void *); 170 static int bce_ioctl(struct ifnet *, u_long, void *); 171 static void bce_start(struct ifnet *); 172 static void bce_watchdog(struct ifnet *); 173 static int bce_intr(void *); 174 static void bce_rxintr(struct bce_softc *); 175 static void bce_txintr(struct bce_softc *); 176 static int bce_init(struct ifnet *); 177 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 178 static int bce_add_rxbuf(struct bce_softc *, int); 179 static void bce_rxdrain(struct bce_softc *); 180 static void bce_stop(struct ifnet *, int); 181 static void bce_reset(struct bce_softc *); 182 static bool bce_resume(device_t, const pmf_qual_t *); 183 static void bce_set_filter(struct ifnet *); 184 static int bce_mii_read(device_t, int, int); 185 static void bce_mii_write(device_t, int, int, int); 186 static void bce_statchg(device_t); 187 static void bce_tick(void *); 188 189 CFATTACH_DECL(bce, sizeof(struct bce_softc), bce_probe, bce_attach, NULL, NULL); 190 191 static const struct bce_product { 192 pci_vendor_id_t bp_vendor; 193 pci_product_id_t bp_product; 194 const char *bp_name; 195 } bce_products[] = { 196 { 197 PCI_VENDOR_BROADCOM, 198 PCI_PRODUCT_BROADCOM_BCM4401, 199 "Broadcom BCM4401 10/100 Ethernet" 200 }, 201 { 202 PCI_VENDOR_BROADCOM, 203 PCI_PRODUCT_BROADCOM_BCM4401_B0, 204 "Broadcom BCM4401-B0 10/100 Ethernet" 205 }, 206 { 207 208 0, 209 0, 210 NULL 211 }, 212 }; 213 214 static const struct bce_product * 215 bce_lookup(const struct pci_attach_args * pa) 216 { 217 const struct bce_product *bp; 218 219 for (bp = bce_products; bp->bp_name != NULL; bp++) { 220 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 221 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 222 return (bp); 223 } 224 225 return (NULL); 226 } 227 228 /* 229 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 230 * against drivers product list, and return its name if a match is found. 231 */ 232 static int 233 bce_probe(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 236 237 if (bce_lookup(pa) != NULL) 238 return (1); 239 240 return (0); 241 } 242 243 static void 244 bce_attach(device_t parent, device_t self, void *aux) 245 { 246 struct bce_softc *sc = device_private(self); 247 struct pci_attach_args *pa = aux; 248 const struct bce_product *bp; 249 pci_chipset_tag_t pc = pa->pa_pc; 250 pci_intr_handle_t ih; 251 const char *intrstr = NULL; 252 uint32_t command; 253 pcireg_t memtype, pmode; 254 bus_addr_t memaddr; 255 bus_size_t memsize; 256 void *kva; 257 bus_dma_segment_t seg; 258 int error, i, pmreg, rseg; 259 struct ifnet *ifp; 260 261 bp = bce_lookup(pa); 262 KASSERT(bp != NULL); 263 264 sc->bce_pa = *pa; 265 266 /* BCM440x can only address 30 bits (1GB) */ 267 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 268 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 269 aprint_error_dev(self, 270 "WARNING: failed to restrict dma range," 271 " falling back to parent bus dma range\n"); 272 sc->bce_dmatag = pa->pa_dmat; 273 } 274 275 aprint_naive(": Ethernet controller\n"); 276 aprint_normal(": %s\n", bp->bp_name); 277 278 /* 279 * Map control/status registers. 280 */ 281 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 282 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 283 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 284 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 285 286 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 287 aprint_error_dev(self, "failed to enable memory mapping!\n"); 288 return; 289 } 290 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 291 switch (memtype) { 292 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 293 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 294 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 295 &sc->bce_bhandle, &memaddr, &memsize) == 0) 296 break; 297 default: 298 aprint_error_dev(self, "unable to find mem space\n"); 299 return; 300 } 301 302 /* Get it out of power save mode if needed. */ 303 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 304 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 305 if (pmode == 3) { 306 /* 307 * The card has lost all configuration data in 308 * this state, so punt. 309 */ 310 aprint_error_dev(self, 311 "unable to wake up from power state D3\n"); 312 return; 313 } 314 if (pmode != 0) { 315 aprint_normal_dev(self, 316 "waking up from power state D%d\n", pmode); 317 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 318 } 319 } 320 if (pci_intr_map(pa, &ih)) { 321 aprint_error_dev(self, "couldn't map interrupt\n"); 322 return; 323 } 324 intrstr = pci_intr_string(pc, ih); 325 326 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 327 328 if (sc->bce_intrhand == NULL) { 329 aprint_error_dev(self, "couldn't establish interrupt\n"); 330 if (intrstr != NULL) 331 aprint_error(" at %s", intrstr); 332 aprint_error("\n"); 333 return; 334 } 335 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 336 337 /* reset the chip */ 338 bce_reset(sc); 339 340 /* 341 * Allocate DMA-safe memory for ring descriptors. 342 * The receive, and transmit rings can not share the same 343 * 4k space, however both are allocated at once here. 344 */ 345 /* 346 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 347 * due to the limition above. ?? 348 */ 349 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 350 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 351 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 352 aprint_error_dev(self, 353 "unable to alloc space for ring descriptors, error = %d\n", 354 error); 355 return; 356 } 357 /* map ring space to kernel */ 358 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 359 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 360 aprint_error_dev(self, 361 "unable to map DMA buffers, error = %d\n", error); 362 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 363 return; 364 } 365 /* create a dma map for the ring */ 366 if ((error = bus_dmamap_create(sc->bce_dmatag, 367 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 368 &sc->bce_ring_map))) { 369 aprint_error_dev(self, 370 "unable to create ring DMA map, error = %d\n", error); 371 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 372 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 373 return; 374 } 375 /* connect the ring space to the dma map */ 376 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 377 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 378 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 379 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 380 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 381 return; 382 } 383 /* save the ring space in softc */ 384 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 385 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 386 387 /* Create the transmit buffer DMA maps. */ 388 for (i = 0; i < BCE_NTXDESC; i++) { 389 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 390 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 391 aprint_error_dev(self, 392 "unable to create tx DMA map, error = %d\n", error); 393 } 394 sc->bce_cdata.bce_tx_chain[i] = NULL; 395 } 396 397 /* Create the receive buffer DMA maps. */ 398 for (i = 0; i < BCE_NRXDESC; i++) { 399 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 400 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 401 aprint_error_dev(self, 402 "unable to create rx DMA map, error = %d\n", error); 403 } 404 sc->bce_cdata.bce_rx_chain[i] = NULL; 405 } 406 407 /* Set up ifnet structure */ 408 ifp = &sc->ethercom.ec_if; 409 strcpy(ifp->if_xname, device_xname(self)); 410 ifp->if_softc = sc; 411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 412 ifp->if_ioctl = bce_ioctl; 413 ifp->if_start = bce_start; 414 ifp->if_watchdog = bce_watchdog; 415 ifp->if_init = bce_init; 416 ifp->if_stop = bce_stop; 417 IFQ_SET_READY(&ifp->if_snd); 418 419 /* Initialize our media structures and probe the MII. */ 420 421 sc->bce_mii.mii_ifp = ifp; 422 sc->bce_mii.mii_readreg = bce_mii_read; 423 sc->bce_mii.mii_writereg = bce_mii_write; 424 sc->bce_mii.mii_statchg = bce_statchg; 425 426 sc->ethercom.ec_mii = &sc->bce_mii; 427 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 428 ether_mediastatus); 429 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 431 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 432 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 433 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 434 } else 435 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 436 /* get the phy */ 437 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 438 BCE_MAGIC_PHY) & 0x1f; 439 /* 440 * Enable activity led. 441 * XXX This should be in a phy driver, but not currently. 442 */ 443 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 444 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 445 /* enable traffic meter led mode */ 446 bce_mii_write(&sc->bce_dev, 1, 27, /* MAGIC */ 447 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 448 449 /* Attach the interface */ 450 if_attach(ifp); 451 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 452 BCE_MAGIC_ENET0); 453 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 454 BCE_MAGIC_ENET1); 455 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 456 BCE_MAGIC_ENET2); 457 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 458 BCE_MAGIC_ENET3); 459 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 460 BCE_MAGIC_ENET4); 461 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 462 BCE_MAGIC_ENET5); 463 aprint_normal_dev(self, "Ethernet address %s\n", 464 ether_sprintf(sc->enaddr)); 465 ether_ifattach(ifp, sc->enaddr); 466 #if NRND > 0 467 rnd_attach_source(&sc->rnd_source, device_xname(self), 468 RND_TYPE_NET, 0); 469 #endif 470 callout_init(&sc->bce_timeout, 0); 471 472 if (pmf_device_register(self, NULL, bce_resume)) 473 pmf_class_network_register(self, ifp); 474 else 475 aprint_error_dev(self, "couldn't establish power handler\n"); 476 } 477 478 /* handle media, and ethernet requests */ 479 static int 480 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 481 { 482 int s, error; 483 484 s = splnet(); 485 error = ether_ioctl(ifp, cmd, data); 486 if (error == ENETRESET) { 487 /* change multicast list */ 488 error = 0; 489 } 490 491 /* Try to get more packets going. */ 492 bce_start(ifp); 493 494 splx(s); 495 return error; 496 } 497 498 /* Start packet transmission on the interface. */ 499 static void 500 bce_start(struct ifnet *ifp) 501 { 502 struct bce_softc *sc = ifp->if_softc; 503 struct mbuf *m0; 504 bus_dmamap_t dmamap; 505 int txstart; 506 int txsfree; 507 int newpkts = 0; 508 int error; 509 510 /* 511 * do not start another if currently transmitting, and more 512 * descriptors(tx slots) are needed for next packet. 513 */ 514 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 515 return; 516 517 /* determine number of descriptors available */ 518 if (sc->bce_txsnext >= sc->bce_txin) 519 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 520 else 521 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 522 523 /* 524 * Loop through the send queue, setting up transmit descriptors 525 * until we drain the queue, or use up all available transmit 526 * descriptors. 527 */ 528 while (txsfree > 0) { 529 int seg; 530 531 /* Grab a packet off the queue. */ 532 IFQ_POLL(&ifp->if_snd, m0); 533 if (m0 == NULL) 534 break; 535 536 /* get the transmit slot dma map */ 537 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 538 539 /* 540 * Load the DMA map. If this fails, the packet either 541 * didn't fit in the alloted number of segments, or we 542 * were short on resources. If the packet will not fit, 543 * it will be dropped. If short on resources, it will 544 * be tried again later. 545 */ 546 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 547 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 548 if (error == EFBIG) { 549 aprint_error_dev(&sc->bce_dev, 550 "Tx packet consumes too many DMA segments, " 551 "dropping...\n"); 552 IFQ_DEQUEUE(&ifp->if_snd, m0); 553 m_freem(m0); 554 ifp->if_oerrors++; 555 continue; 556 } else if (error) { 557 /* short on resources, come back later */ 558 aprint_error_dev(&sc->bce_dev, 559 "unable to load Tx buffer, error = %d\n", 560 error); 561 break; 562 } 563 /* If not enough descriptors available, try again later */ 564 if (dmamap->dm_nsegs > txsfree) { 565 ifp->if_flags |= IFF_OACTIVE; 566 bus_dmamap_unload(sc->bce_dmatag, dmamap); 567 break; 568 } 569 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 570 571 /* So take it off the queue */ 572 IFQ_DEQUEUE(&ifp->if_snd, m0); 573 574 /* save the pointer so it can be freed later */ 575 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 576 577 /* Sync the data DMA map. */ 578 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 579 BUS_DMASYNC_PREWRITE); 580 581 /* Initialize the transmit descriptor(s). */ 582 txstart = sc->bce_txsnext; 583 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 584 uint32_t ctrl; 585 586 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 587 if (seg == 0) 588 ctrl |= CTRL_SOF; 589 if (seg == dmamap->dm_nsegs - 1) 590 ctrl |= CTRL_EOF; 591 if (sc->bce_txsnext == BCE_NTXDESC - 1) 592 ctrl |= CTRL_EOT; 593 ctrl |= CTRL_IOC; 594 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 595 sc->bce_tx_ring[sc->bce_txsnext].addr = 596 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 597 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 598 sc->bce_txsnext = 0; 599 else 600 sc->bce_txsnext++; 601 txsfree--; 602 } 603 /* sync descriptors being used */ 604 if ( sc->bce_txsnext > txstart ) { 605 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 606 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 607 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 609 } else { 610 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 611 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 612 sizeof(struct bce_dma_slot) * 613 (BCE_NTXDESC - txstart), 614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 615 if ( sc->bce_txsnext != 0 ) { 616 bus_dmamap_sync(sc->bce_dmatag, 617 sc->bce_ring_map, PAGE_SIZE, 618 sc->bce_txsnext * 619 sizeof(struct bce_dma_slot), 620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 621 } 622 } 623 624 /* Give the packet to the chip. */ 625 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 626 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 627 628 newpkts++; 629 630 /* Pass the packet to any BPF listeners. */ 631 bpf_mtap(ifp, m0); 632 } 633 if (txsfree == 0) { 634 /* No more slots left; notify upper layer. */ 635 ifp->if_flags |= IFF_OACTIVE; 636 } 637 if (newpkts) { 638 /* Set a watchdog timer in case the chip flakes out. */ 639 ifp->if_timer = 5; 640 } 641 } 642 643 /* Watchdog timer handler. */ 644 static void 645 bce_watchdog(struct ifnet *ifp) 646 { 647 struct bce_softc *sc = ifp->if_softc; 648 649 aprint_error_dev(&sc->bce_dev, "device timeout\n"); 650 ifp->if_oerrors++; 651 652 (void) bce_init(ifp); 653 654 /* Try to get more packets going. */ 655 bce_start(ifp); 656 } 657 658 int 659 bce_intr(void *xsc) 660 { 661 struct bce_softc *sc; 662 struct ifnet *ifp; 663 uint32_t intstatus; 664 int wantinit; 665 int handled = 0; 666 667 sc = xsc; 668 ifp = &sc->ethercom.ec_if; 669 670 for (wantinit = 0; wantinit == 0;) { 671 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 672 BCE_INT_STS); 673 674 /* ignore if not ours, or unsolicited interrupts */ 675 intstatus &= sc->bce_intmask; 676 if (intstatus == 0) 677 break; 678 679 handled = 1; 680 681 /* Ack interrupt */ 682 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 683 intstatus); 684 685 /* Receive interrupts. */ 686 if (intstatus & I_RI) 687 bce_rxintr(sc); 688 /* Transmit interrupts. */ 689 if (intstatus & I_XI) 690 bce_txintr(sc); 691 /* Error interrupts */ 692 if (intstatus & ~(I_RI | I_XI)) { 693 const char *msg = NULL; 694 if (intstatus & I_XU) 695 msg = "transmit fifo underflow"; 696 if (intstatus & I_RO) { 697 msg = "receive fifo overflow"; 698 ifp->if_ierrors++; 699 } 700 if (intstatus & I_RU) 701 msg = "receive descriptor underflow"; 702 if (intstatus & I_DE) 703 msg = "descriptor protocol error"; 704 if (intstatus & I_PD) 705 msg = "data error"; 706 if (intstatus & I_PC) 707 msg = "descriptor error"; 708 if (intstatus & I_TO) 709 msg = "general purpose timeout"; 710 if (msg != NULL) 711 aprint_error_dev(&sc->bce_dev, "%s\n", msg); 712 wantinit = 1; 713 } 714 } 715 716 if (handled) { 717 if (wantinit) 718 bce_init(ifp); 719 #if NRND > 0 720 if (RND_ENABLED(&sc->rnd_source)) 721 rnd_add_uint32(&sc->rnd_source, intstatus); 722 #endif 723 /* Try to get more packets going. */ 724 bce_start(ifp); 725 } 726 return (handled); 727 } 728 729 /* Receive interrupt handler */ 730 void 731 bce_rxintr(struct bce_softc *sc) 732 { 733 struct ifnet *ifp = &sc->ethercom.ec_if; 734 struct rx_pph *pph; 735 struct mbuf *m; 736 int curr; 737 int len; 738 int i; 739 740 /* get pointer to active receive slot */ 741 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 742 & RS_CD_MASK; 743 curr = curr / sizeof(struct bce_dma_slot); 744 if (curr >= BCE_NRXDESC) 745 curr = BCE_NRXDESC - 1; 746 747 /* process packets up to but not current packet being worked on */ 748 for (i = sc->bce_rxin; i != curr; 749 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 750 /* complete any post dma memory ops on packet */ 751 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 752 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 753 BUS_DMASYNC_POSTREAD); 754 755 /* 756 * If the packet had an error, simply recycle the buffer, 757 * resetting the len, and flags. 758 */ 759 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 760 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 761 ifp->if_ierrors++; 762 pph->len = 0; 763 pph->flags = 0; 764 continue; 765 } 766 /* receive the packet */ 767 len = pph->len; 768 if (len == 0) 769 continue; /* no packet if empty */ 770 pph->len = 0; 771 pph->flags = 0; 772 /* bump past pre header to packet */ 773 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 774 775 /* 776 * The chip includes the CRC with every packet. Trim 777 * it off here. 778 */ 779 len -= ETHER_CRC_LEN; 780 781 /* 782 * If the packet is small enough to fit in a 783 * single header mbuf, allocate one and copy 784 * the data into it. This greatly reduces 785 * memory consumption when receiving lots 786 * of small packets. 787 * 788 * Otherwise, add a new buffer to the receive 789 * chain. If this fails, drop the packet and 790 * recycle the old buffer. 791 */ 792 if (len <= (MHLEN - 2)) { 793 MGETHDR(m, M_DONTWAIT, MT_DATA); 794 if (m == NULL) 795 goto dropit; 796 m->m_data += 2; 797 memcpy(mtod(m, void *), 798 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 799 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 800 } else { 801 m = sc->bce_cdata.bce_rx_chain[i]; 802 if (bce_add_rxbuf(sc, i) != 0) { 803 dropit: 804 ifp->if_ierrors++; 805 /* continue to use old buffer */ 806 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 807 bus_dmamap_sync(sc->bce_dmatag, 808 sc->bce_cdata.bce_rx_map[i], 0, 809 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 810 BUS_DMASYNC_PREREAD); 811 continue; 812 } 813 } 814 815 m->m_pkthdr.rcvif = ifp; 816 m->m_pkthdr.len = m->m_len = len; 817 ifp->if_ipackets++; 818 819 /* 820 * Pass this up to any BPF listeners, but only 821 * pass it up the stack if it's for us. 822 */ 823 bpf_mtap(ifp, m); 824 825 /* Pass it on. */ 826 (*ifp->if_input) (ifp, m); 827 828 /* re-check current in case it changed */ 829 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 830 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 831 sizeof(struct bce_dma_slot); 832 if (curr >= BCE_NRXDESC) 833 curr = BCE_NRXDESC - 1; 834 } 835 sc->bce_rxin = curr; 836 } 837 838 /* Transmit interrupt handler */ 839 void 840 bce_txintr(struct bce_softc *sc) 841 { 842 struct ifnet *ifp = &sc->ethercom.ec_if; 843 int curr; 844 int i; 845 846 ifp->if_flags &= ~IFF_OACTIVE; 847 848 /* 849 * Go through the Tx list and free mbufs for those 850 * frames which have been transmitted. 851 */ 852 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 853 RS_CD_MASK; 854 curr = curr / sizeof(struct bce_dma_slot); 855 if (curr >= BCE_NTXDESC) 856 curr = BCE_NTXDESC - 1; 857 for (i = sc->bce_txin; i != curr; 858 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 859 /* do any post dma memory ops on transmit data */ 860 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 861 continue; 862 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 863 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 864 BUS_DMASYNC_POSTWRITE); 865 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 866 m_freem(sc->bce_cdata.bce_tx_chain[i]); 867 sc->bce_cdata.bce_tx_chain[i] = NULL; 868 ifp->if_opackets++; 869 } 870 sc->bce_txin = curr; 871 872 /* 873 * If there are no more pending transmissions, cancel the watchdog 874 * timer 875 */ 876 if (sc->bce_txsnext == sc->bce_txin) 877 ifp->if_timer = 0; 878 } 879 880 /* initialize the interface */ 881 static int 882 bce_init(struct ifnet *ifp) 883 { 884 struct bce_softc *sc = ifp->if_softc; 885 uint32_t reg_win; 886 int error; 887 int i; 888 889 /* Cancel any pending I/O. */ 890 bce_stop(ifp, 0); 891 892 /* enable pci inerrupts, bursts, and prefetch */ 893 894 /* remap the pci registers to the Sonics config registers */ 895 896 /* save the current map, so it can be restored */ 897 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 898 BCE_REG_WIN); 899 900 /* set register window to Sonics registers */ 901 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 902 BCE_SONICS_WIN); 903 904 /* enable SB to PCI interrupt */ 905 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 906 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 907 SBIV_ENET0); 908 909 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 910 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 911 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 912 SBTOPCI_PREF | SBTOPCI_BURST); 913 914 /* restore to ethernet register space */ 915 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 916 reg_win); 917 918 /* Reset the chip to a known state. */ 919 bce_reset(sc); 920 921 /* Initialize transmit descriptors */ 922 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 923 sc->bce_txsnext = 0; 924 sc->bce_txin = 0; 925 926 /* enable crc32 generation */ 927 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 928 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 929 BCE_EMC_CG); 930 931 /* setup DMA interrupt control */ 932 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 933 934 /* setup packet filter */ 935 bce_set_filter(ifp); 936 937 /* set max frame length, account for possible vlan tag */ 938 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 939 ETHER_MAX_LEN + 32); 940 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 941 ETHER_MAX_LEN + 32); 942 943 /* set tx watermark */ 944 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 945 946 /* enable transmit */ 947 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 948 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 949 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 950 951 /* 952 * Give the receive ring to the chip, and 953 * start the receive DMA engine. 954 */ 955 sc->bce_rxin = 0; 956 957 /* clear the rx descriptor ring */ 958 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 959 /* enable receive */ 960 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 961 30 << 1 | 1); /* MAGIC */ 962 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 963 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 964 965 /* Initalize receive descriptors */ 966 for (i = 0; i < BCE_NRXDESC; i++) { 967 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 968 if ((error = bce_add_rxbuf(sc, i)) != 0) { 969 aprint_error_dev(&sc->bce_dev, 970 "unable to allocate or map rx(%d) " 971 "mbuf, error = %d\n", i, error); 972 bce_rxdrain(sc); 973 return (error); 974 } 975 } else 976 BCE_INIT_RXDESC(sc, i); 977 } 978 979 /* Enable interrupts */ 980 sc->bce_intmask = 981 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 982 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 983 sc->bce_intmask); 984 985 /* start the receive dma */ 986 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 987 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 988 989 /* set media */ 990 if ((error = ether_mediachange(ifp)) != 0) 991 return error; 992 993 /* turn on the ethernet mac */ 994 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 995 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 996 BCE_ENET_CTL) | EC_EE); 997 998 /* start timer */ 999 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1000 1001 /* mark as running, and no outputs active */ 1002 ifp->if_flags |= IFF_RUNNING; 1003 ifp->if_flags &= ~IFF_OACTIVE; 1004 1005 return 0; 1006 } 1007 1008 /* add a mac address to packet filter */ 1009 void 1010 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1011 { 1012 int i; 1013 uint32_t rval; 1014 1015 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1016 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1017 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1018 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1019 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1020 idx << 16 | 8); /* MAGIC */ 1021 /* wait for write to complete */ 1022 for (i = 0; i < 100; i++) { 1023 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1024 BCE_FILT_CTL); 1025 if (!(rval & 0x80000000)) /* MAGIC */ 1026 break; 1027 delay(10); 1028 } 1029 if (i == 100) { 1030 aprint_error_dev(&sc->bce_dev, 1031 "timed out writing pkt filter ctl\n"); 1032 } 1033 } 1034 1035 /* Add a receive buffer to the indiciated descriptor. */ 1036 static int 1037 bce_add_rxbuf(struct bce_softc *sc, int idx) 1038 { 1039 struct mbuf *m; 1040 int error; 1041 1042 MGETHDR(m, M_DONTWAIT, MT_DATA); 1043 if (m == NULL) 1044 return (ENOBUFS); 1045 1046 MCLGET(m, M_DONTWAIT); 1047 if ((m->m_flags & M_EXT) == 0) { 1048 m_freem(m); 1049 return (ENOBUFS); 1050 } 1051 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1052 bus_dmamap_unload(sc->bce_dmatag, 1053 sc->bce_cdata.bce_rx_map[idx]); 1054 1055 sc->bce_cdata.bce_rx_chain[idx] = m; 1056 1057 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1058 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1059 BUS_DMA_READ | BUS_DMA_NOWAIT); 1060 if (error) 1061 return (error); 1062 1063 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1064 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1065 1066 BCE_INIT_RXDESC(sc, idx); 1067 1068 return (0); 1069 1070 } 1071 1072 /* Drain the receive queue. */ 1073 static void 1074 bce_rxdrain(struct bce_softc *sc) 1075 { 1076 int i; 1077 1078 for (i = 0; i < BCE_NRXDESC; i++) { 1079 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1080 bus_dmamap_unload(sc->bce_dmatag, 1081 sc->bce_cdata.bce_rx_map[i]); 1082 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1083 sc->bce_cdata.bce_rx_chain[i] = NULL; 1084 } 1085 } 1086 } 1087 1088 /* Stop transmission on the interface */ 1089 static void 1090 bce_stop(struct ifnet *ifp, int disable) 1091 { 1092 struct bce_softc *sc = ifp->if_softc; 1093 int i; 1094 uint32_t val; 1095 1096 /* Stop the 1 second timer */ 1097 callout_stop(&sc->bce_timeout); 1098 1099 /* Down the MII. */ 1100 mii_down(&sc->bce_mii); 1101 1102 /* Disable interrupts. */ 1103 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1104 sc->bce_intmask = 0; 1105 delay(10); 1106 1107 /* Disable emac */ 1108 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1109 for (i = 0; i < 200; i++) { 1110 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1111 BCE_ENET_CTL); 1112 if (!(val & EC_ED)) 1113 break; 1114 delay(10); 1115 } 1116 1117 /* Stop the DMA */ 1118 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1119 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1120 delay(10); 1121 1122 /* Release any queued transmit buffers. */ 1123 for (i = 0; i < BCE_NTXDESC; i++) { 1124 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1125 bus_dmamap_unload(sc->bce_dmatag, 1126 sc->bce_cdata.bce_tx_map[i]); 1127 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1128 sc->bce_cdata.bce_tx_chain[i] = NULL; 1129 } 1130 } 1131 1132 /* Mark the interface down and cancel the watchdog timer. */ 1133 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1134 ifp->if_timer = 0; 1135 1136 /* drain receive queue */ 1137 if (disable) 1138 bce_rxdrain(sc); 1139 } 1140 1141 /* reset the chip */ 1142 static void 1143 bce_reset(struct bce_softc *sc) 1144 { 1145 uint32_t val; 1146 uint32_t sbval; 1147 int i; 1148 1149 /* if SB core is up */ 1150 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1151 BCE_SBTMSTATELOW); 1152 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1153 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1154 0); 1155 1156 /* disable emac */ 1157 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1158 EC_ED); 1159 for (i = 0; i < 200; i++) { 1160 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1161 BCE_ENET_CTL); 1162 if (!(val & EC_ED)) 1163 break; 1164 delay(10); 1165 } 1166 if (i == 200) { 1167 aprint_error_dev(&sc->bce_dev, 1168 "timed out disabling ethernet mac\n"); 1169 } 1170 1171 /* reset the dma engines */ 1172 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1173 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1174 /* if error on receive, wait to go idle */ 1175 if (val & RS_ERROR) { 1176 for (i = 0; i < 100; i++) { 1177 val = bus_space_read_4(sc->bce_btag, 1178 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1179 if (val & RS_DMA_IDLE) 1180 break; 1181 delay(10); 1182 } 1183 if (i == 100) { 1184 aprint_error_dev(&sc->bce_dev, 1185 "receive dma did not go idle after" 1186 " error\n"); 1187 } 1188 } 1189 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1190 BCE_DMA_RXSTATUS, 0); 1191 1192 /* reset ethernet mac */ 1193 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1194 EC_ES); 1195 for (i = 0; i < 200; i++) { 1196 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1197 BCE_ENET_CTL); 1198 if (!(val & EC_ES)) 1199 break; 1200 delay(10); 1201 } 1202 if (i == 200) { 1203 aprint_error_dev(&sc->bce_dev, 1204 "timed out resetting ethernet mac\n"); 1205 } 1206 } else { 1207 uint32_t reg_win; 1208 1209 /* remap the pci registers to the Sonics config registers */ 1210 1211 /* save the current map, so it can be restored */ 1212 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1213 BCE_REG_WIN); 1214 /* set register window to Sonics registers */ 1215 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1216 BCE_REG_WIN, BCE_SONICS_WIN); 1217 1218 /* enable SB to PCI interrupt */ 1219 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1220 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1221 BCE_SBINTVEC) | 1222 SBIV_ENET0); 1223 1224 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1225 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1226 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1227 BCE_SPCI_TR2) | 1228 SBTOPCI_PREF | SBTOPCI_BURST); 1229 1230 /* restore to ethernet register space */ 1231 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1232 reg_win); 1233 } 1234 1235 /* disable SB core if not in reset */ 1236 if (!(sbval & SBTML_RESET)) { 1237 1238 /* set the reject bit */ 1239 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1240 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1241 for (i = 0; i < 200; i++) { 1242 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1243 BCE_SBTMSTATELOW); 1244 if (val & SBTML_REJ) 1245 break; 1246 delay(1); 1247 } 1248 if (i == 200) { 1249 aprint_error_dev(&sc->bce_dev, 1250 "while resetting core, reject did not set\n"); 1251 } 1252 /* wait until busy is clear */ 1253 for (i = 0; i < 200; i++) { 1254 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1255 BCE_SBTMSTATEHI); 1256 if (!(val & 0x4)) 1257 break; 1258 delay(1); 1259 } 1260 if (i == 200) { 1261 aprint_error_dev(&sc->bce_dev, 1262 "while resetting core, busy did not clear\n"); 1263 } 1264 /* set reset and reject while enabling the clocks */ 1265 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1266 BCE_SBTMSTATELOW, 1267 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1268 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1269 BCE_SBTMSTATELOW); 1270 delay(10); 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1272 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1273 delay(1); 1274 } 1275 /* enable clock */ 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1277 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1278 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1279 delay(1); 1280 1281 /* clear any error bits that may be on */ 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1283 if (val & 1) 1284 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1285 0); 1286 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1287 if (val & SBIM_MAGIC_ERRORBITS) 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1289 val & ~SBIM_MAGIC_ERRORBITS); 1290 1291 /* clear reset and allow it to propagate throughout the core */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1293 SBTML_FGC | SBTML_CLK); 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1295 delay(1); 1296 1297 /* leave clock enabled */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1299 SBTML_CLK); 1300 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1301 delay(1); 1302 1303 /* initialize MDC preamble, frequency */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1305 1306 /* enable phy, differs for internal, and external */ 1307 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1308 if (!(val & BCE_DC_IP)) { 1309 /* select external phy */ 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1311 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1312 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1313 val & ~BCE_DC_ER); 1314 delay(100); 1315 } 1316 } 1317 1318 /* Set up the receive filter. */ 1319 void 1320 bce_set_filter(struct ifnet *ifp) 1321 { 1322 struct bce_softc *sc = ifp->if_softc; 1323 1324 if (ifp->if_flags & IFF_PROMISC) { 1325 ifp->if_flags |= IFF_ALLMULTI; 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1327 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1328 | ERC_PE); 1329 } else { 1330 ifp->if_flags &= ~IFF_ALLMULTI; 1331 1332 /* turn off promiscuous */ 1333 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1334 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1335 BCE_RX_CTL) & ~ERC_PE); 1336 1337 /* enable/disable broadcast */ 1338 if (ifp->if_flags & IFF_BROADCAST) 1339 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1340 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1341 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1342 else 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1344 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1345 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1346 1347 /* disable the filter */ 1348 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1349 0); 1350 1351 /* add our own address */ 1352 bce_add_mac(sc, sc->enaddr, 0); 1353 1354 /* for now accept all multicast */ 1355 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1356 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1357 ERC_AM); 1358 ifp->if_flags |= IFF_ALLMULTI; 1359 1360 /* enable the filter */ 1361 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1362 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1363 BCE_FILT_CTL) | 1); 1364 } 1365 } 1366 1367 static bool 1368 bce_resume(device_t self, const pmf_qual_t *qual) 1369 { 1370 struct bce_softc *sc = device_private(self); 1371 1372 bce_reset(sc); 1373 1374 return true; 1375 } 1376 1377 /* Read a PHY register on the MII. */ 1378 int 1379 bce_mii_read(device_t self, int phy, int reg) 1380 { 1381 struct bce_softc *sc = device_private(self); 1382 int i; 1383 uint32_t val; 1384 1385 /* clear mii_int */ 1386 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1387 1388 /* Read the PHY register */ 1389 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1390 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1391 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1392 1393 for (i = 0; i < BCE_TIMEOUT; i++) { 1394 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1395 if (val & BCE_MIINTR) 1396 break; 1397 delay(10); 1398 } 1399 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1400 if (i == BCE_TIMEOUT) { 1401 aprint_error_dev(&sc->bce_dev, 1402 "PHY read timed out reading phy %d, reg %d, val = " 1403 "0x%08x\n", phy, reg, val); 1404 return (0); 1405 } 1406 return (val & BCE_MICOMM_DATA); 1407 } 1408 1409 /* Write a PHY register on the MII */ 1410 void 1411 bce_mii_write(device_t self, int phy, int reg, int val) 1412 { 1413 struct bce_softc *sc = device_private(self); 1414 int i; 1415 uint32_t rval; 1416 1417 /* clear mii_int */ 1418 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1419 BCE_MIINTR); 1420 1421 /* Write the PHY register */ 1422 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1423 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1424 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1425 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1426 1427 /* wait for write to complete */ 1428 for (i = 0; i < BCE_TIMEOUT; i++) { 1429 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1430 BCE_MI_STS); 1431 if (rval & BCE_MIINTR) 1432 break; 1433 delay(10); 1434 } 1435 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1436 if (i == BCE_TIMEOUT) { 1437 aprint_error_dev(&sc->bce_dev, 1438 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1439 reg, val); 1440 } 1441 } 1442 1443 /* sync hardware duplex mode to software state */ 1444 void 1445 bce_statchg(device_t self) 1446 { 1447 struct bce_softc *sc = device_private(self); 1448 uint32_t reg; 1449 1450 /* if needed, change register to match duplex mode */ 1451 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1452 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1453 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1454 reg | EXC_FD); 1455 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1456 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1457 reg & ~EXC_FD); 1458 1459 /* 1460 * Enable activity led. 1461 * XXX This should be in a phy driver, but not currently. 1462 */ 1463 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1464 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1465 /* enable traffic meter led mode */ 1466 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1467 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1468 } 1469 1470 /* One second timer, checks link status */ 1471 static void 1472 bce_tick(void *v) 1473 { 1474 struct bce_softc *sc = v; 1475 1476 /* Tick the MII. */ 1477 mii_tick(&sc->bce_mii); 1478 1479 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1480 } 1481
Indexes created Tue Sep 30 20:09:53 GMT 2025