if_bce.c revision 1.35
1 /* $NetBSD: if_bce.c,v 1.35 2012/02/02 19:43:05 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.35 2012/02/02 19:43:05 tls Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rnd.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 struct device bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int); 178 static void bce_mii_write(device_t, int, int, int); 179 static void bce_statchg(device_t); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL(bce, sizeof(struct bce_softc), bce_probe, bce_attach, NULL, NULL); 183 184 static const struct bce_product { 185 pci_vendor_id_t bp_vendor; 186 pci_product_id_t bp_product; 187 const char *bp_name; 188 } bce_products[] = { 189 { 190 PCI_VENDOR_BROADCOM, 191 PCI_PRODUCT_BROADCOM_BCM4401, 192 "Broadcom BCM4401 10/100 Ethernet" 193 }, 194 { 195 PCI_VENDOR_BROADCOM, 196 PCI_PRODUCT_BROADCOM_BCM4401_B0, 197 "Broadcom BCM4401-B0 10/100 Ethernet" 198 }, 199 { 200 201 0, 202 0, 203 NULL 204 }, 205 }; 206 207 static const struct bce_product * 208 bce_lookup(const struct pci_attach_args * pa) 209 { 210 const struct bce_product *bp; 211 212 for (bp = bce_products; bp->bp_name != NULL; bp++) { 213 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 214 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 215 return (bp); 216 } 217 218 return (NULL); 219 } 220 221 /* 222 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 223 * against drivers product list, and return its name if a match is found. 224 */ 225 static int 226 bce_probe(device_t parent, cfdata_t match, void *aux) 227 { 228 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 229 230 if (bce_lookup(pa) != NULL) 231 return (1); 232 233 return (0); 234 } 235 236 static void 237 bce_attach(device_t parent, device_t self, void *aux) 238 { 239 struct bce_softc *sc = device_private(self); 240 struct pci_attach_args *pa = aux; 241 const struct bce_product *bp; 242 pci_chipset_tag_t pc = pa->pa_pc; 243 pci_intr_handle_t ih; 244 const char *intrstr = NULL; 245 uint32_t command; 246 pcireg_t memtype, pmode; 247 bus_addr_t memaddr; 248 bus_size_t memsize; 249 void *kva; 250 bus_dma_segment_t seg; 251 int error, i, pmreg, rseg; 252 struct ifnet *ifp; 253 254 bp = bce_lookup(pa); 255 KASSERT(bp != NULL); 256 257 sc->bce_pa = *pa; 258 259 /* BCM440x can only address 30 bits (1GB) */ 260 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 261 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 262 aprint_error_dev(self, 263 "WARNING: failed to restrict dma range," 264 " falling back to parent bus dma range\n"); 265 sc->bce_dmatag = pa->pa_dmat; 266 } 267 268 aprint_naive(": Ethernet controller\n"); 269 aprint_normal(": %s\n", bp->bp_name); 270 271 /* 272 * Map control/status registers. 273 */ 274 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 275 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 276 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 277 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 278 279 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 280 aprint_error_dev(self, "failed to enable memory mapping!\n"); 281 return; 282 } 283 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 284 switch (memtype) { 285 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 286 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 287 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 288 &sc->bce_bhandle, &memaddr, &memsize) == 0) 289 break; 290 default: 291 aprint_error_dev(self, "unable to find mem space\n"); 292 return; 293 } 294 295 /* Get it out of power save mode if needed. */ 296 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 297 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 298 if (pmode == 3) { 299 /* 300 * The card has lost all configuration data in 301 * this state, so punt. 302 */ 303 aprint_error_dev(self, 304 "unable to wake up from power state D3\n"); 305 return; 306 } 307 if (pmode != 0) { 308 aprint_normal_dev(self, 309 "waking up from power state D%d\n", pmode); 310 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 311 } 312 } 313 if (pci_intr_map(pa, &ih)) { 314 aprint_error_dev(self, "couldn't map interrupt\n"); 315 return; 316 } 317 intrstr = pci_intr_string(pc, ih); 318 319 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 320 321 if (sc->bce_intrhand == NULL) { 322 aprint_error_dev(self, "couldn't establish interrupt\n"); 323 if (intrstr != NULL) 324 aprint_error(" at %s", intrstr); 325 aprint_error("\n"); 326 return; 327 } 328 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 329 330 /* reset the chip */ 331 bce_reset(sc); 332 333 /* 334 * Allocate DMA-safe memory for ring descriptors. 335 * The receive, and transmit rings can not share the same 336 * 4k space, however both are allocated at once here. 337 */ 338 /* 339 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 340 * due to the limition above. ?? 341 */ 342 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 343 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 344 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 345 aprint_error_dev(self, 346 "unable to alloc space for ring descriptors, error = %d\n", 347 error); 348 return; 349 } 350 /* map ring space to kernel */ 351 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 352 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 353 aprint_error_dev(self, 354 "unable to map DMA buffers, error = %d\n", error); 355 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 356 return; 357 } 358 /* create a dma map for the ring */ 359 if ((error = bus_dmamap_create(sc->bce_dmatag, 360 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 361 &sc->bce_ring_map))) { 362 aprint_error_dev(self, 363 "unable to create ring DMA map, error = %d\n", error); 364 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 365 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 366 return; 367 } 368 /* connect the ring space to the dma map */ 369 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 370 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 371 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 372 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 373 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 374 return; 375 } 376 /* save the ring space in softc */ 377 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 378 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 379 380 /* Create the transmit buffer DMA maps. */ 381 for (i = 0; i < BCE_NTXDESC; i++) { 382 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 383 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 384 aprint_error_dev(self, 385 "unable to create tx DMA map, error = %d\n", error); 386 } 387 sc->bce_cdata.bce_tx_chain[i] = NULL; 388 } 389 390 /* Create the receive buffer DMA maps. */ 391 for (i = 0; i < BCE_NRXDESC; i++) { 392 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 393 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 394 aprint_error_dev(self, 395 "unable to create rx DMA map, error = %d\n", error); 396 } 397 sc->bce_cdata.bce_rx_chain[i] = NULL; 398 } 399 400 /* Set up ifnet structure */ 401 ifp = &sc->ethercom.ec_if; 402 strcpy(ifp->if_xname, device_xname(self)); 403 ifp->if_softc = sc; 404 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 405 ifp->if_ioctl = bce_ioctl; 406 ifp->if_start = bce_start; 407 ifp->if_watchdog = bce_watchdog; 408 ifp->if_init = bce_init; 409 ifp->if_stop = bce_stop; 410 IFQ_SET_READY(&ifp->if_snd); 411 412 /* Initialize our media structures and probe the MII. */ 413 414 sc->bce_mii.mii_ifp = ifp; 415 sc->bce_mii.mii_readreg = bce_mii_read; 416 sc->bce_mii.mii_writereg = bce_mii_write; 417 sc->bce_mii.mii_statchg = bce_statchg; 418 419 sc->ethercom.ec_mii = &sc->bce_mii; 420 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 421 ether_mediastatus); 422 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 423 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 424 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 425 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 426 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 427 } else 428 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 429 /* get the phy */ 430 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 431 BCE_MAGIC_PHY) & 0x1f; 432 /* 433 * Enable activity led. 434 * XXX This should be in a phy driver, but not currently. 435 */ 436 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 437 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 438 /* enable traffic meter led mode */ 439 bce_mii_write(&sc->bce_dev, 1, 27, /* MAGIC */ 440 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 441 442 /* Attach the interface */ 443 if_attach(ifp); 444 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 445 BCE_MAGIC_ENET0); 446 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 447 BCE_MAGIC_ENET1); 448 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 449 BCE_MAGIC_ENET2); 450 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 451 BCE_MAGIC_ENET3); 452 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 453 BCE_MAGIC_ENET4); 454 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 455 BCE_MAGIC_ENET5); 456 aprint_normal_dev(self, "Ethernet address %s\n", 457 ether_sprintf(sc->enaddr)); 458 ether_ifattach(ifp, sc->enaddr); 459 rnd_attach_source(&sc->rnd_source, device_xname(self), 460 RND_TYPE_NET, 0); 461 callout_init(&sc->bce_timeout, 0); 462 463 if (pmf_device_register(self, NULL, bce_resume)) 464 pmf_class_network_register(self, ifp); 465 else 466 aprint_error_dev(self, "couldn't establish power handler\n"); 467 } 468 469 /* handle media, and ethernet requests */ 470 static int 471 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 472 { 473 int s, error; 474 475 s = splnet(); 476 error = ether_ioctl(ifp, cmd, data); 477 if (error == ENETRESET) { 478 /* change multicast list */ 479 error = 0; 480 } 481 482 /* Try to get more packets going. */ 483 bce_start(ifp); 484 485 splx(s); 486 return error; 487 } 488 489 /* Start packet transmission on the interface. */ 490 static void 491 bce_start(struct ifnet *ifp) 492 { 493 struct bce_softc *sc = ifp->if_softc; 494 struct mbuf *m0; 495 bus_dmamap_t dmamap; 496 int txstart; 497 int txsfree; 498 int newpkts = 0; 499 int error; 500 501 /* 502 * do not start another if currently transmitting, and more 503 * descriptors(tx slots) are needed for next packet. 504 */ 505 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 506 return; 507 508 /* determine number of descriptors available */ 509 if (sc->bce_txsnext >= sc->bce_txin) 510 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 511 else 512 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 513 514 /* 515 * Loop through the send queue, setting up transmit descriptors 516 * until we drain the queue, or use up all available transmit 517 * descriptors. 518 */ 519 while (txsfree > 0) { 520 int seg; 521 522 /* Grab a packet off the queue. */ 523 IFQ_POLL(&ifp->if_snd, m0); 524 if (m0 == NULL) 525 break; 526 527 /* get the transmit slot dma map */ 528 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 529 530 /* 531 * Load the DMA map. If this fails, the packet either 532 * didn't fit in the alloted number of segments, or we 533 * were short on resources. If the packet will not fit, 534 * it will be dropped. If short on resources, it will 535 * be tried again later. 536 */ 537 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 538 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 539 if (error == EFBIG) { 540 aprint_error_dev(&sc->bce_dev, 541 "Tx packet consumes too many DMA segments, " 542 "dropping...\n"); 543 IFQ_DEQUEUE(&ifp->if_snd, m0); 544 m_freem(m0); 545 ifp->if_oerrors++; 546 continue; 547 } else if (error) { 548 /* short on resources, come back later */ 549 aprint_error_dev(&sc->bce_dev, 550 "unable to load Tx buffer, error = %d\n", 551 error); 552 break; 553 } 554 /* If not enough descriptors available, try again later */ 555 if (dmamap->dm_nsegs > txsfree) { 556 ifp->if_flags |= IFF_OACTIVE; 557 bus_dmamap_unload(sc->bce_dmatag, dmamap); 558 break; 559 } 560 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 561 562 /* So take it off the queue */ 563 IFQ_DEQUEUE(&ifp->if_snd, m0); 564 565 /* save the pointer so it can be freed later */ 566 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 567 568 /* Sync the data DMA map. */ 569 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 570 BUS_DMASYNC_PREWRITE); 571 572 /* Initialize the transmit descriptor(s). */ 573 txstart = sc->bce_txsnext; 574 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 575 uint32_t ctrl; 576 577 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 578 if (seg == 0) 579 ctrl |= CTRL_SOF; 580 if (seg == dmamap->dm_nsegs - 1) 581 ctrl |= CTRL_EOF; 582 if (sc->bce_txsnext == BCE_NTXDESC - 1) 583 ctrl |= CTRL_EOT; 584 ctrl |= CTRL_IOC; 585 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 586 sc->bce_tx_ring[sc->bce_txsnext].addr = 587 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 588 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 589 sc->bce_txsnext = 0; 590 else 591 sc->bce_txsnext++; 592 txsfree--; 593 } 594 /* sync descriptors being used */ 595 if ( sc->bce_txsnext > txstart ) { 596 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 597 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 598 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 599 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 600 } else { 601 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 602 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 603 sizeof(struct bce_dma_slot) * 604 (BCE_NTXDESC - txstart), 605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 606 if ( sc->bce_txsnext != 0 ) { 607 bus_dmamap_sync(sc->bce_dmatag, 608 sc->bce_ring_map, PAGE_SIZE, 609 sc->bce_txsnext * 610 sizeof(struct bce_dma_slot), 611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 612 } 613 } 614 615 /* Give the packet to the chip. */ 616 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 617 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 618 619 newpkts++; 620 621 /* Pass the packet to any BPF listeners. */ 622 bpf_mtap(ifp, m0); 623 } 624 if (txsfree == 0) { 625 /* No more slots left; notify upper layer. */ 626 ifp->if_flags |= IFF_OACTIVE; 627 } 628 if (newpkts) { 629 /* Set a watchdog timer in case the chip flakes out. */ 630 ifp->if_timer = 5; 631 } 632 } 633 634 /* Watchdog timer handler. */ 635 static void 636 bce_watchdog(struct ifnet *ifp) 637 { 638 struct bce_softc *sc = ifp->if_softc; 639 640 aprint_error_dev(&sc->bce_dev, "device timeout\n"); 641 ifp->if_oerrors++; 642 643 (void) bce_init(ifp); 644 645 /* Try to get more packets going. */ 646 bce_start(ifp); 647 } 648 649 int 650 bce_intr(void *xsc) 651 { 652 struct bce_softc *sc; 653 struct ifnet *ifp; 654 uint32_t intstatus; 655 int wantinit; 656 int handled = 0; 657 658 sc = xsc; 659 ifp = &sc->ethercom.ec_if; 660 661 for (wantinit = 0; wantinit == 0;) { 662 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 663 BCE_INT_STS); 664 665 /* ignore if not ours, or unsolicited interrupts */ 666 intstatus &= sc->bce_intmask; 667 if (intstatus == 0) 668 break; 669 670 handled = 1; 671 672 /* Ack interrupt */ 673 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 674 intstatus); 675 676 /* Receive interrupts. */ 677 if (intstatus & I_RI) 678 bce_rxintr(sc); 679 /* Transmit interrupts. */ 680 if (intstatus & I_XI) 681 bce_txintr(sc); 682 /* Error interrupts */ 683 if (intstatus & ~(I_RI | I_XI)) { 684 const char *msg = NULL; 685 if (intstatus & I_XU) 686 msg = "transmit fifo underflow"; 687 if (intstatus & I_RO) { 688 msg = "receive fifo overflow"; 689 ifp->if_ierrors++; 690 } 691 if (intstatus & I_RU) 692 msg = "receive descriptor underflow"; 693 if (intstatus & I_DE) 694 msg = "descriptor protocol error"; 695 if (intstatus & I_PD) 696 msg = "data error"; 697 if (intstatus & I_PC) 698 msg = "descriptor error"; 699 if (intstatus & I_TO) 700 msg = "general purpose timeout"; 701 if (msg != NULL) 702 aprint_error_dev(&sc->bce_dev, "%s\n", msg); 703 wantinit = 1; 704 } 705 } 706 707 if (handled) { 708 if (wantinit) 709 bce_init(ifp); 710 rnd_add_uint32(&sc->rnd_source, intstatus); 711 /* Try to get more packets going. */ 712 bce_start(ifp); 713 } 714 return (handled); 715 } 716 717 /* Receive interrupt handler */ 718 void 719 bce_rxintr(struct bce_softc *sc) 720 { 721 struct ifnet *ifp = &sc->ethercom.ec_if; 722 struct rx_pph *pph; 723 struct mbuf *m; 724 int curr; 725 int len; 726 int i; 727 728 /* get pointer to active receive slot */ 729 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 730 & RS_CD_MASK; 731 curr = curr / sizeof(struct bce_dma_slot); 732 if (curr >= BCE_NRXDESC) 733 curr = BCE_NRXDESC - 1; 734 735 /* process packets up to but not current packet being worked on */ 736 for (i = sc->bce_rxin; i != curr; 737 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 738 /* complete any post dma memory ops on packet */ 739 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 740 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 741 BUS_DMASYNC_POSTREAD); 742 743 /* 744 * If the packet had an error, simply recycle the buffer, 745 * resetting the len, and flags. 746 */ 747 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 748 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 749 ifp->if_ierrors++; 750 pph->len = 0; 751 pph->flags = 0; 752 continue; 753 } 754 /* receive the packet */ 755 len = pph->len; 756 if (len == 0) 757 continue; /* no packet if empty */ 758 pph->len = 0; 759 pph->flags = 0; 760 /* bump past pre header to packet */ 761 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 762 763 /* 764 * The chip includes the CRC with every packet. Trim 765 * it off here. 766 */ 767 len -= ETHER_CRC_LEN; 768 769 /* 770 * If the packet is small enough to fit in a 771 * single header mbuf, allocate one and copy 772 * the data into it. This greatly reduces 773 * memory consumption when receiving lots 774 * of small packets. 775 * 776 * Otherwise, add a new buffer to the receive 777 * chain. If this fails, drop the packet and 778 * recycle the old buffer. 779 */ 780 if (len <= (MHLEN - 2)) { 781 MGETHDR(m, M_DONTWAIT, MT_DATA); 782 if (m == NULL) 783 goto dropit; 784 m->m_data += 2; 785 memcpy(mtod(m, void *), 786 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 787 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 788 } else { 789 m = sc->bce_cdata.bce_rx_chain[i]; 790 if (bce_add_rxbuf(sc, i) != 0) { 791 dropit: 792 ifp->if_ierrors++; 793 /* continue to use old buffer */ 794 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 795 bus_dmamap_sync(sc->bce_dmatag, 796 sc->bce_cdata.bce_rx_map[i], 0, 797 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 798 BUS_DMASYNC_PREREAD); 799 continue; 800 } 801 } 802 803 m->m_pkthdr.rcvif = ifp; 804 m->m_pkthdr.len = m->m_len = len; 805 ifp->if_ipackets++; 806 807 /* 808 * Pass this up to any BPF listeners, but only 809 * pass it up the stack if it's for us. 810 */ 811 bpf_mtap(ifp, m); 812 813 /* Pass it on. */ 814 (*ifp->if_input) (ifp, m); 815 816 /* re-check current in case it changed */ 817 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 818 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 819 sizeof(struct bce_dma_slot); 820 if (curr >= BCE_NRXDESC) 821 curr = BCE_NRXDESC - 1; 822 } 823 sc->bce_rxin = curr; 824 } 825 826 /* Transmit interrupt handler */ 827 void 828 bce_txintr(struct bce_softc *sc) 829 { 830 struct ifnet *ifp = &sc->ethercom.ec_if; 831 int curr; 832 int i; 833 834 ifp->if_flags &= ~IFF_OACTIVE; 835 836 /* 837 * Go through the Tx list and free mbufs for those 838 * frames which have been transmitted. 839 */ 840 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 841 RS_CD_MASK; 842 curr = curr / sizeof(struct bce_dma_slot); 843 if (curr >= BCE_NTXDESC) 844 curr = BCE_NTXDESC - 1; 845 for (i = sc->bce_txin; i != curr; 846 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 847 /* do any post dma memory ops on transmit data */ 848 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 849 continue; 850 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 851 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 852 BUS_DMASYNC_POSTWRITE); 853 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 854 m_freem(sc->bce_cdata.bce_tx_chain[i]); 855 sc->bce_cdata.bce_tx_chain[i] = NULL; 856 ifp->if_opackets++; 857 } 858 sc->bce_txin = curr; 859 860 /* 861 * If there are no more pending transmissions, cancel the watchdog 862 * timer 863 */ 864 if (sc->bce_txsnext == sc->bce_txin) 865 ifp->if_timer = 0; 866 } 867 868 /* initialize the interface */ 869 static int 870 bce_init(struct ifnet *ifp) 871 { 872 struct bce_softc *sc = ifp->if_softc; 873 uint32_t reg_win; 874 int error; 875 int i; 876 877 /* Cancel any pending I/O. */ 878 bce_stop(ifp, 0); 879 880 /* enable pci inerrupts, bursts, and prefetch */ 881 882 /* remap the pci registers to the Sonics config registers */ 883 884 /* save the current map, so it can be restored */ 885 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 886 BCE_REG_WIN); 887 888 /* set register window to Sonics registers */ 889 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 890 BCE_SONICS_WIN); 891 892 /* enable SB to PCI interrupt */ 893 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 894 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 895 SBIV_ENET0); 896 897 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 898 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 899 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 900 SBTOPCI_PREF | SBTOPCI_BURST); 901 902 /* restore to ethernet register space */ 903 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 904 reg_win); 905 906 /* Reset the chip to a known state. */ 907 bce_reset(sc); 908 909 /* Initialize transmit descriptors */ 910 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 911 sc->bce_txsnext = 0; 912 sc->bce_txin = 0; 913 914 /* enable crc32 generation */ 915 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 916 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 917 BCE_EMC_CG); 918 919 /* setup DMA interrupt control */ 920 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 921 922 /* setup packet filter */ 923 bce_set_filter(ifp); 924 925 /* set max frame length, account for possible vlan tag */ 926 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 927 ETHER_MAX_LEN + 32); 928 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 929 ETHER_MAX_LEN + 32); 930 931 /* set tx watermark */ 932 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 933 934 /* enable transmit */ 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 936 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 937 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 938 939 /* 940 * Give the receive ring to the chip, and 941 * start the receive DMA engine. 942 */ 943 sc->bce_rxin = 0; 944 945 /* clear the rx descriptor ring */ 946 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 947 /* enable receive */ 948 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 949 30 << 1 | 1); /* MAGIC */ 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 951 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 952 953 /* Initalize receive descriptors */ 954 for (i = 0; i < BCE_NRXDESC; i++) { 955 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 956 if ((error = bce_add_rxbuf(sc, i)) != 0) { 957 aprint_error_dev(&sc->bce_dev, 958 "unable to allocate or map rx(%d) " 959 "mbuf, error = %d\n", i, error); 960 bce_rxdrain(sc); 961 return (error); 962 } 963 } else 964 BCE_INIT_RXDESC(sc, i); 965 } 966 967 /* Enable interrupts */ 968 sc->bce_intmask = 969 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 970 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 971 sc->bce_intmask); 972 973 /* start the receive dma */ 974 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 975 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 976 977 /* set media */ 978 if ((error = ether_mediachange(ifp)) != 0) 979 return error; 980 981 /* turn on the ethernet mac */ 982 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 983 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 984 BCE_ENET_CTL) | EC_EE); 985 986 /* start timer */ 987 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 988 989 /* mark as running, and no outputs active */ 990 ifp->if_flags |= IFF_RUNNING; 991 ifp->if_flags &= ~IFF_OACTIVE; 992 993 return 0; 994 } 995 996 /* add a mac address to packet filter */ 997 void 998 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 999 { 1000 int i; 1001 uint32_t rval; 1002 1003 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1004 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1005 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1006 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1007 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1008 idx << 16 | 8); /* MAGIC */ 1009 /* wait for write to complete */ 1010 for (i = 0; i < 100; i++) { 1011 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1012 BCE_FILT_CTL); 1013 if (!(rval & 0x80000000)) /* MAGIC */ 1014 break; 1015 delay(10); 1016 } 1017 if (i == 100) { 1018 aprint_error_dev(&sc->bce_dev, 1019 "timed out writing pkt filter ctl\n"); 1020 } 1021 } 1022 1023 /* Add a receive buffer to the indiciated descriptor. */ 1024 static int 1025 bce_add_rxbuf(struct bce_softc *sc, int idx) 1026 { 1027 struct mbuf *m; 1028 int error; 1029 1030 MGETHDR(m, M_DONTWAIT, MT_DATA); 1031 if (m == NULL) 1032 return (ENOBUFS); 1033 1034 MCLGET(m, M_DONTWAIT); 1035 if ((m->m_flags & M_EXT) == 0) { 1036 m_freem(m); 1037 return (ENOBUFS); 1038 } 1039 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1040 bus_dmamap_unload(sc->bce_dmatag, 1041 sc->bce_cdata.bce_rx_map[idx]); 1042 1043 sc->bce_cdata.bce_rx_chain[idx] = m; 1044 1045 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1046 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1047 BUS_DMA_READ | BUS_DMA_NOWAIT); 1048 if (error) 1049 return (error); 1050 1051 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1052 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1053 1054 BCE_INIT_RXDESC(sc, idx); 1055 1056 return (0); 1057 1058 } 1059 1060 /* Drain the receive queue. */ 1061 static void 1062 bce_rxdrain(struct bce_softc *sc) 1063 { 1064 int i; 1065 1066 for (i = 0; i < BCE_NRXDESC; i++) { 1067 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1068 bus_dmamap_unload(sc->bce_dmatag, 1069 sc->bce_cdata.bce_rx_map[i]); 1070 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1071 sc->bce_cdata.bce_rx_chain[i] = NULL; 1072 } 1073 } 1074 } 1075 1076 /* Stop transmission on the interface */ 1077 static void 1078 bce_stop(struct ifnet *ifp, int disable) 1079 { 1080 struct bce_softc *sc = ifp->if_softc; 1081 int i; 1082 uint32_t val; 1083 1084 /* Stop the 1 second timer */ 1085 callout_stop(&sc->bce_timeout); 1086 1087 /* Down the MII. */ 1088 mii_down(&sc->bce_mii); 1089 1090 /* Disable interrupts. */ 1091 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1092 sc->bce_intmask = 0; 1093 delay(10); 1094 1095 /* Disable emac */ 1096 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1097 for (i = 0; i < 200; i++) { 1098 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1099 BCE_ENET_CTL); 1100 if (!(val & EC_ED)) 1101 break; 1102 delay(10); 1103 } 1104 1105 /* Stop the DMA */ 1106 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1107 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1108 delay(10); 1109 1110 /* Release any queued transmit buffers. */ 1111 for (i = 0; i < BCE_NTXDESC; i++) { 1112 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1113 bus_dmamap_unload(sc->bce_dmatag, 1114 sc->bce_cdata.bce_tx_map[i]); 1115 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1116 sc->bce_cdata.bce_tx_chain[i] = NULL; 1117 } 1118 } 1119 1120 /* Mark the interface down and cancel the watchdog timer. */ 1121 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1122 ifp->if_timer = 0; 1123 1124 /* drain receive queue */ 1125 if (disable) 1126 bce_rxdrain(sc); 1127 } 1128 1129 /* reset the chip */ 1130 static void 1131 bce_reset(struct bce_softc *sc) 1132 { 1133 uint32_t val; 1134 uint32_t sbval; 1135 int i; 1136 1137 /* if SB core is up */ 1138 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1139 BCE_SBTMSTATELOW); 1140 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1141 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1142 0); 1143 1144 /* disable emac */ 1145 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1146 EC_ED); 1147 for (i = 0; i < 200; i++) { 1148 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1149 BCE_ENET_CTL); 1150 if (!(val & EC_ED)) 1151 break; 1152 delay(10); 1153 } 1154 if (i == 200) { 1155 aprint_error_dev(&sc->bce_dev, 1156 "timed out disabling ethernet mac\n"); 1157 } 1158 1159 /* reset the dma engines */ 1160 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1161 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1162 /* if error on receive, wait to go idle */ 1163 if (val & RS_ERROR) { 1164 for (i = 0; i < 100; i++) { 1165 val = bus_space_read_4(sc->bce_btag, 1166 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1167 if (val & RS_DMA_IDLE) 1168 break; 1169 delay(10); 1170 } 1171 if (i == 100) { 1172 aprint_error_dev(&sc->bce_dev, 1173 "receive dma did not go idle after" 1174 " error\n"); 1175 } 1176 } 1177 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1178 BCE_DMA_RXSTATUS, 0); 1179 1180 /* reset ethernet mac */ 1181 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1182 EC_ES); 1183 for (i = 0; i < 200; i++) { 1184 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1185 BCE_ENET_CTL); 1186 if (!(val & EC_ES)) 1187 break; 1188 delay(10); 1189 } 1190 if (i == 200) { 1191 aprint_error_dev(&sc->bce_dev, 1192 "timed out resetting ethernet mac\n"); 1193 } 1194 } else { 1195 uint32_t reg_win; 1196 1197 /* remap the pci registers to the Sonics config registers */ 1198 1199 /* save the current map, so it can be restored */ 1200 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1201 BCE_REG_WIN); 1202 /* set register window to Sonics registers */ 1203 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1204 BCE_REG_WIN, BCE_SONICS_WIN); 1205 1206 /* enable SB to PCI interrupt */ 1207 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1208 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1209 BCE_SBINTVEC) | 1210 SBIV_ENET0); 1211 1212 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1213 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1214 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1215 BCE_SPCI_TR2) | 1216 SBTOPCI_PREF | SBTOPCI_BURST); 1217 1218 /* restore to ethernet register space */ 1219 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1220 reg_win); 1221 } 1222 1223 /* disable SB core if not in reset */ 1224 if (!(sbval & SBTML_RESET)) { 1225 1226 /* set the reject bit */ 1227 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1228 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1229 for (i = 0; i < 200; i++) { 1230 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1231 BCE_SBTMSTATELOW); 1232 if (val & SBTML_REJ) 1233 break; 1234 delay(1); 1235 } 1236 if (i == 200) { 1237 aprint_error_dev(&sc->bce_dev, 1238 "while resetting core, reject did not set\n"); 1239 } 1240 /* wait until busy is clear */ 1241 for (i = 0; i < 200; i++) { 1242 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1243 BCE_SBTMSTATEHI); 1244 if (!(val & 0x4)) 1245 break; 1246 delay(1); 1247 } 1248 if (i == 200) { 1249 aprint_error_dev(&sc->bce_dev, 1250 "while resetting core, busy did not clear\n"); 1251 } 1252 /* set reset and reject while enabling the clocks */ 1253 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1254 BCE_SBTMSTATELOW, 1255 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1256 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1257 BCE_SBTMSTATELOW); 1258 delay(10); 1259 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1260 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1261 delay(1); 1262 } 1263 /* enable clock */ 1264 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1265 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1266 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1267 delay(1); 1268 1269 /* clear any error bits that may be on */ 1270 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1271 if (val & 1) 1272 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1273 0); 1274 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1275 if (val & SBIM_MAGIC_ERRORBITS) 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1277 val & ~SBIM_MAGIC_ERRORBITS); 1278 1279 /* clear reset and allow it to propagate throughout the core */ 1280 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1281 SBTML_FGC | SBTML_CLK); 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1283 delay(1); 1284 1285 /* leave clock enabled */ 1286 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1287 SBTML_CLK); 1288 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1289 delay(1); 1290 1291 /* initialize MDC preamble, frequency */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1293 1294 /* enable phy, differs for internal, and external */ 1295 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1296 if (!(val & BCE_DC_IP)) { 1297 /* select external phy */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1299 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1300 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1301 val & ~BCE_DC_ER); 1302 delay(100); 1303 } 1304 } 1305 1306 /* Set up the receive filter. */ 1307 void 1308 bce_set_filter(struct ifnet *ifp) 1309 { 1310 struct bce_softc *sc = ifp->if_softc; 1311 1312 if (ifp->if_flags & IFF_PROMISC) { 1313 ifp->if_flags |= IFF_ALLMULTI; 1314 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1315 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1316 | ERC_PE); 1317 } else { 1318 ifp->if_flags &= ~IFF_ALLMULTI; 1319 1320 /* turn off promiscuous */ 1321 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1322 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1323 BCE_RX_CTL) & ~ERC_PE); 1324 1325 /* enable/disable broadcast */ 1326 if (ifp->if_flags & IFF_BROADCAST) 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1328 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1329 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1330 else 1331 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1332 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1333 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1334 1335 /* disable the filter */ 1336 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1337 0); 1338 1339 /* add our own address */ 1340 bce_add_mac(sc, sc->enaddr, 0); 1341 1342 /* for now accept all multicast */ 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1344 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1345 ERC_AM); 1346 ifp->if_flags |= IFF_ALLMULTI; 1347 1348 /* enable the filter */ 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1350 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1351 BCE_FILT_CTL) | 1); 1352 } 1353 } 1354 1355 static bool 1356 bce_resume(device_t self, const pmf_qual_t *qual) 1357 { 1358 struct bce_softc *sc = device_private(self); 1359 1360 bce_reset(sc); 1361 1362 return true; 1363 } 1364 1365 /* Read a PHY register on the MII. */ 1366 int 1367 bce_mii_read(device_t self, int phy, int reg) 1368 { 1369 struct bce_softc *sc = device_private(self); 1370 int i; 1371 uint32_t val; 1372 1373 /* clear mii_int */ 1374 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1375 1376 /* Read the PHY register */ 1377 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1378 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1379 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1380 1381 for (i = 0; i < BCE_TIMEOUT; i++) { 1382 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1383 if (val & BCE_MIINTR) 1384 break; 1385 delay(10); 1386 } 1387 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1388 if (i == BCE_TIMEOUT) { 1389 aprint_error_dev(&sc->bce_dev, 1390 "PHY read timed out reading phy %d, reg %d, val = " 1391 "0x%08x\n", phy, reg, val); 1392 return (0); 1393 } 1394 return (val & BCE_MICOMM_DATA); 1395 } 1396 1397 /* Write a PHY register on the MII */ 1398 void 1399 bce_mii_write(device_t self, int phy, int reg, int val) 1400 { 1401 struct bce_softc *sc = device_private(self); 1402 int i; 1403 uint32_t rval; 1404 1405 /* clear mii_int */ 1406 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1407 BCE_MIINTR); 1408 1409 /* Write the PHY register */ 1410 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1411 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1412 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1413 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1414 1415 /* wait for write to complete */ 1416 for (i = 0; i < BCE_TIMEOUT; i++) { 1417 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1418 BCE_MI_STS); 1419 if (rval & BCE_MIINTR) 1420 break; 1421 delay(10); 1422 } 1423 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1424 if (i == BCE_TIMEOUT) { 1425 aprint_error_dev(&sc->bce_dev, 1426 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1427 reg, val); 1428 } 1429 } 1430 1431 /* sync hardware duplex mode to software state */ 1432 void 1433 bce_statchg(device_t self) 1434 { 1435 struct bce_softc *sc = device_private(self); 1436 uint32_t reg; 1437 1438 /* if needed, change register to match duplex mode */ 1439 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1440 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1441 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1442 reg | EXC_FD); 1443 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1444 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1445 reg & ~EXC_FD); 1446 1447 /* 1448 * Enable activity led. 1449 * XXX This should be in a phy driver, but not currently. 1450 */ 1451 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1452 bce_mii_read(&sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1453 /* enable traffic meter led mode */ 1454 bce_mii_write(&sc->bce_dev, 1, 26, /* MAGIC */ 1455 bce_mii_read(&sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1456 } 1457 1458 /* One second timer, checks link status */ 1459 static void 1460 bce_tick(void *v) 1461 { 1462 struct bce_softc *sc = v; 1463 1464 /* Tick the MII. */ 1465 mii_tick(&sc->bce_mii); 1466 1467 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1468 } 1469
Indexes created Tue Sep 30 20:09:53 GMT 2025