if_bce.c revision 1.36
1 /* $NetBSD: if_bce.c,v 1.36 2012/02/20 02:14:34 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.36 2012/02/20 02:14:34 mrg Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rnd.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 device_t bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int); 178 static void bce_mii_write(device_t, int, int, int); 179 static void bce_statchg(device_t); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 183 bce_probe, bce_attach, NULL, NULL); 184 185 static const struct bce_product { 186 pci_vendor_id_t bp_vendor; 187 pci_product_id_t bp_product; 188 const char *bp_name; 189 } bce_products[] = { 190 { 191 PCI_VENDOR_BROADCOM, 192 PCI_PRODUCT_BROADCOM_BCM4401, 193 "Broadcom BCM4401 10/100 Ethernet" 194 }, 195 { 196 PCI_VENDOR_BROADCOM, 197 PCI_PRODUCT_BROADCOM_BCM4401_B0, 198 "Broadcom BCM4401-B0 10/100 Ethernet" 199 }, 200 { 201 202 0, 203 0, 204 NULL 205 }, 206 }; 207 208 static const struct bce_product * 209 bce_lookup(const struct pci_attach_args * pa) 210 { 211 const struct bce_product *bp; 212 213 for (bp = bce_products; bp->bp_name != NULL; bp++) { 214 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 215 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 216 return (bp); 217 } 218 219 return (NULL); 220 } 221 222 /* 223 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 224 * against drivers product list, and return its name if a match is found. 225 */ 226 static int 227 bce_probe(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 230 231 if (bce_lookup(pa) != NULL) 232 return (1); 233 234 return (0); 235 } 236 237 static void 238 bce_attach(device_t parent, device_t self, void *aux) 239 { 240 struct bce_softc *sc = device_private(self); 241 struct pci_attach_args *pa = aux; 242 const struct bce_product *bp; 243 pci_chipset_tag_t pc = pa->pa_pc; 244 pci_intr_handle_t ih; 245 const char *intrstr = NULL; 246 uint32_t command; 247 pcireg_t memtype, pmode; 248 bus_addr_t memaddr; 249 bus_size_t memsize; 250 void *kva; 251 bus_dma_segment_t seg; 252 int error, i, pmreg, rseg; 253 struct ifnet *ifp; 254 255 sc->bce_dev = self; 256 257 bp = bce_lookup(pa); 258 KASSERT(bp != NULL); 259 260 sc->bce_pa = *pa; 261 262 /* BCM440x can only address 30 bits (1GB) */ 263 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 264 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 265 aprint_error_dev(self, 266 "WARNING: failed to restrict dma range," 267 " falling back to parent bus dma range\n"); 268 sc->bce_dmatag = pa->pa_dmat; 269 } 270 271 aprint_naive(": Ethernet controller\n"); 272 aprint_normal(": %s\n", bp->bp_name); 273 274 /* 275 * Map control/status registers. 276 */ 277 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 278 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 279 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 280 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 281 282 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 283 aprint_error_dev(self, "failed to enable memory mapping!\n"); 284 return; 285 } 286 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 287 switch (memtype) { 288 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 289 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 290 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 291 &sc->bce_bhandle, &memaddr, &memsize) == 0) 292 break; 293 default: 294 aprint_error_dev(self, "unable to find mem space\n"); 295 return; 296 } 297 298 /* Get it out of power save mode if needed. */ 299 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 300 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 301 if (pmode == 3) { 302 /* 303 * The card has lost all configuration data in 304 * this state, so punt. 305 */ 306 aprint_error_dev(self, 307 "unable to wake up from power state D3\n"); 308 return; 309 } 310 if (pmode != 0) { 311 aprint_normal_dev(self, 312 "waking up from power state D%d\n", pmode); 313 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 314 } 315 } 316 if (pci_intr_map(pa, &ih)) { 317 aprint_error_dev(self, "couldn't map interrupt\n"); 318 return; 319 } 320 intrstr = pci_intr_string(pc, ih); 321 322 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 323 324 if (sc->bce_intrhand == NULL) { 325 aprint_error_dev(self, "couldn't establish interrupt\n"); 326 if (intrstr != NULL) 327 aprint_error(" at %s", intrstr); 328 aprint_error("\n"); 329 return; 330 } 331 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 332 333 /* reset the chip */ 334 bce_reset(sc); 335 336 /* 337 * Allocate DMA-safe memory for ring descriptors. 338 * The receive, and transmit rings can not share the same 339 * 4k space, however both are allocated at once here. 340 */ 341 /* 342 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 343 * due to the limition above. ?? 344 */ 345 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 346 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 347 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 348 aprint_error_dev(self, 349 "unable to alloc space for ring descriptors, error = %d\n", 350 error); 351 return; 352 } 353 /* map ring space to kernel */ 354 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 355 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 356 aprint_error_dev(self, 357 "unable to map DMA buffers, error = %d\n", error); 358 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 359 return; 360 } 361 /* create a dma map for the ring */ 362 if ((error = bus_dmamap_create(sc->bce_dmatag, 363 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 364 &sc->bce_ring_map))) { 365 aprint_error_dev(self, 366 "unable to create ring DMA map, error = %d\n", error); 367 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 368 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 369 return; 370 } 371 /* connect the ring space to the dma map */ 372 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 373 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 374 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 375 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 376 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 377 return; 378 } 379 /* save the ring space in softc */ 380 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 381 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 382 383 /* Create the transmit buffer DMA maps. */ 384 for (i = 0; i < BCE_NTXDESC; i++) { 385 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 386 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 387 aprint_error_dev(self, 388 "unable to create tx DMA map, error = %d\n", error); 389 } 390 sc->bce_cdata.bce_tx_chain[i] = NULL; 391 } 392 393 /* Create the receive buffer DMA maps. */ 394 for (i = 0; i < BCE_NRXDESC; i++) { 395 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 396 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 397 aprint_error_dev(self, 398 "unable to create rx DMA map, error = %d\n", error); 399 } 400 sc->bce_cdata.bce_rx_chain[i] = NULL; 401 } 402 403 /* Set up ifnet structure */ 404 ifp = &sc->ethercom.ec_if; 405 strcpy(ifp->if_xname, device_xname(self)); 406 ifp->if_softc = sc; 407 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 408 ifp->if_ioctl = bce_ioctl; 409 ifp->if_start = bce_start; 410 ifp->if_watchdog = bce_watchdog; 411 ifp->if_init = bce_init; 412 ifp->if_stop = bce_stop; 413 IFQ_SET_READY(&ifp->if_snd); 414 415 /* Initialize our media structures and probe the MII. */ 416 417 sc->bce_mii.mii_ifp = ifp; 418 sc->bce_mii.mii_readreg = bce_mii_read; 419 sc->bce_mii.mii_writereg = bce_mii_write; 420 sc->bce_mii.mii_statchg = bce_statchg; 421 422 sc->ethercom.ec_mii = &sc->bce_mii; 423 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 424 ether_mediastatus); 425 mii_attach(sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 426 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 427 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 428 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 429 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 430 } else 431 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 432 /* get the phy */ 433 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 434 BCE_MAGIC_PHY) & 0x1f; 435 /* 436 * Enable activity led. 437 * XXX This should be in a phy driver, but not currently. 438 */ 439 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 440 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 441 /* enable traffic meter led mode */ 442 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 443 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 444 445 /* Attach the interface */ 446 if_attach(ifp); 447 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 448 BCE_MAGIC_ENET0); 449 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 450 BCE_MAGIC_ENET1); 451 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 452 BCE_MAGIC_ENET2); 453 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 454 BCE_MAGIC_ENET3); 455 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 456 BCE_MAGIC_ENET4); 457 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 458 BCE_MAGIC_ENET5); 459 aprint_normal_dev(self, "Ethernet address %s\n", 460 ether_sprintf(sc->enaddr)); 461 ether_ifattach(ifp, sc->enaddr); 462 rnd_attach_source(&sc->rnd_source, device_xname(self), 463 RND_TYPE_NET, 0); 464 callout_init(&sc->bce_timeout, 0); 465 466 if (pmf_device_register(self, NULL, bce_resume)) 467 pmf_class_network_register(self, ifp); 468 else 469 aprint_error_dev(self, "couldn't establish power handler\n"); 470 } 471 472 /* handle media, and ethernet requests */ 473 static int 474 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 475 { 476 int s, error; 477 478 s = splnet(); 479 error = ether_ioctl(ifp, cmd, data); 480 if (error == ENETRESET) { 481 /* change multicast list */ 482 error = 0; 483 } 484 485 /* Try to get more packets going. */ 486 bce_start(ifp); 487 488 splx(s); 489 return error; 490 } 491 492 /* Start packet transmission on the interface. */ 493 static void 494 bce_start(struct ifnet *ifp) 495 { 496 struct bce_softc *sc = ifp->if_softc; 497 struct mbuf *m0; 498 bus_dmamap_t dmamap; 499 int txstart; 500 int txsfree; 501 int newpkts = 0; 502 int error; 503 504 /* 505 * do not start another if currently transmitting, and more 506 * descriptors(tx slots) are needed for next packet. 507 */ 508 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 509 return; 510 511 /* determine number of descriptors available */ 512 if (sc->bce_txsnext >= sc->bce_txin) 513 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 514 else 515 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 516 517 /* 518 * Loop through the send queue, setting up transmit descriptors 519 * until we drain the queue, or use up all available transmit 520 * descriptors. 521 */ 522 while (txsfree > 0) { 523 int seg; 524 525 /* Grab a packet off the queue. */ 526 IFQ_POLL(&ifp->if_snd, m0); 527 if (m0 == NULL) 528 break; 529 530 /* get the transmit slot dma map */ 531 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 532 533 /* 534 * Load the DMA map. If this fails, the packet either 535 * didn't fit in the alloted number of segments, or we 536 * were short on resources. If the packet will not fit, 537 * it will be dropped. If short on resources, it will 538 * be tried again later. 539 */ 540 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 541 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 542 if (error == EFBIG) { 543 aprint_error_dev(sc->bce_dev, 544 "Tx packet consumes too many DMA segments, " 545 "dropping...\n"); 546 IFQ_DEQUEUE(&ifp->if_snd, m0); 547 m_freem(m0); 548 ifp->if_oerrors++; 549 continue; 550 } else if (error) { 551 /* short on resources, come back later */ 552 aprint_error_dev(sc->bce_dev, 553 "unable to load Tx buffer, error = %d\n", 554 error); 555 break; 556 } 557 /* If not enough descriptors available, try again later */ 558 if (dmamap->dm_nsegs > txsfree) { 559 ifp->if_flags |= IFF_OACTIVE; 560 bus_dmamap_unload(sc->bce_dmatag, dmamap); 561 break; 562 } 563 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 564 565 /* So take it off the queue */ 566 IFQ_DEQUEUE(&ifp->if_snd, m0); 567 568 /* save the pointer so it can be freed later */ 569 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 570 571 /* Sync the data DMA map. */ 572 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 573 BUS_DMASYNC_PREWRITE); 574 575 /* Initialize the transmit descriptor(s). */ 576 txstart = sc->bce_txsnext; 577 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 578 uint32_t ctrl; 579 580 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 581 if (seg == 0) 582 ctrl |= CTRL_SOF; 583 if (seg == dmamap->dm_nsegs - 1) 584 ctrl |= CTRL_EOF; 585 if (sc->bce_txsnext == BCE_NTXDESC - 1) 586 ctrl |= CTRL_EOT; 587 ctrl |= CTRL_IOC; 588 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 589 sc->bce_tx_ring[sc->bce_txsnext].addr = 590 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 591 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 592 sc->bce_txsnext = 0; 593 else 594 sc->bce_txsnext++; 595 txsfree--; 596 } 597 /* sync descriptors being used */ 598 if ( sc->bce_txsnext > txstart ) { 599 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 600 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 601 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 602 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 603 } else { 604 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 605 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 606 sizeof(struct bce_dma_slot) * 607 (BCE_NTXDESC - txstart), 608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 609 if ( sc->bce_txsnext != 0 ) { 610 bus_dmamap_sync(sc->bce_dmatag, 611 sc->bce_ring_map, PAGE_SIZE, 612 sc->bce_txsnext * 613 sizeof(struct bce_dma_slot), 614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 615 } 616 } 617 618 /* Give the packet to the chip. */ 619 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 620 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 621 622 newpkts++; 623 624 /* Pass the packet to any BPF listeners. */ 625 bpf_mtap(ifp, m0); 626 } 627 if (txsfree == 0) { 628 /* No more slots left; notify upper layer. */ 629 ifp->if_flags |= IFF_OACTIVE; 630 } 631 if (newpkts) { 632 /* Set a watchdog timer in case the chip flakes out. */ 633 ifp->if_timer = 5; 634 } 635 } 636 637 /* Watchdog timer handler. */ 638 static void 639 bce_watchdog(struct ifnet *ifp) 640 { 641 struct bce_softc *sc = ifp->if_softc; 642 643 aprint_error_dev(sc->bce_dev, "device timeout\n"); 644 ifp->if_oerrors++; 645 646 (void) bce_init(ifp); 647 648 /* Try to get more packets going. */ 649 bce_start(ifp); 650 } 651 652 int 653 bce_intr(void *xsc) 654 { 655 struct bce_softc *sc; 656 struct ifnet *ifp; 657 uint32_t intstatus; 658 int wantinit; 659 int handled = 0; 660 661 sc = xsc; 662 ifp = &sc->ethercom.ec_if; 663 664 for (wantinit = 0; wantinit == 0;) { 665 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 666 BCE_INT_STS); 667 668 /* ignore if not ours, or unsolicited interrupts */ 669 intstatus &= sc->bce_intmask; 670 if (intstatus == 0) 671 break; 672 673 handled = 1; 674 675 /* Ack interrupt */ 676 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 677 intstatus); 678 679 /* Receive interrupts. */ 680 if (intstatus & I_RI) 681 bce_rxintr(sc); 682 /* Transmit interrupts. */ 683 if (intstatus & I_XI) 684 bce_txintr(sc); 685 /* Error interrupts */ 686 if (intstatus & ~(I_RI | I_XI)) { 687 const char *msg = NULL; 688 if (intstatus & I_XU) 689 msg = "transmit fifo underflow"; 690 if (intstatus & I_RO) { 691 msg = "receive fifo overflow"; 692 ifp->if_ierrors++; 693 } 694 if (intstatus & I_RU) 695 msg = "receive descriptor underflow"; 696 if (intstatus & I_DE) 697 msg = "descriptor protocol error"; 698 if (intstatus & I_PD) 699 msg = "data error"; 700 if (intstatus & I_PC) 701 msg = "descriptor error"; 702 if (intstatus & I_TO) 703 msg = "general purpose timeout"; 704 if (msg != NULL) 705 aprint_error_dev(sc->bce_dev, "%s\n", msg); 706 wantinit = 1; 707 } 708 } 709 710 if (handled) { 711 if (wantinit) 712 bce_init(ifp); 713 rnd_add_uint32(&sc->rnd_source, intstatus); 714 /* Try to get more packets going. */ 715 bce_start(ifp); 716 } 717 return (handled); 718 } 719 720 /* Receive interrupt handler */ 721 void 722 bce_rxintr(struct bce_softc *sc) 723 { 724 struct ifnet *ifp = &sc->ethercom.ec_if; 725 struct rx_pph *pph; 726 struct mbuf *m; 727 int curr; 728 int len; 729 int i; 730 731 /* get pointer to active receive slot */ 732 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 733 & RS_CD_MASK; 734 curr = curr / sizeof(struct bce_dma_slot); 735 if (curr >= BCE_NRXDESC) 736 curr = BCE_NRXDESC - 1; 737 738 /* process packets up to but not current packet being worked on */ 739 for (i = sc->bce_rxin; i != curr; 740 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 741 /* complete any post dma memory ops on packet */ 742 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 743 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 744 BUS_DMASYNC_POSTREAD); 745 746 /* 747 * If the packet had an error, simply recycle the buffer, 748 * resetting the len, and flags. 749 */ 750 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 751 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 752 ifp->if_ierrors++; 753 pph->len = 0; 754 pph->flags = 0; 755 continue; 756 } 757 /* receive the packet */ 758 len = pph->len; 759 if (len == 0) 760 continue; /* no packet if empty */ 761 pph->len = 0; 762 pph->flags = 0; 763 /* bump past pre header to packet */ 764 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 765 766 /* 767 * The chip includes the CRC with every packet. Trim 768 * it off here. 769 */ 770 len -= ETHER_CRC_LEN; 771 772 /* 773 * If the packet is small enough to fit in a 774 * single header mbuf, allocate one and copy 775 * the data into it. This greatly reduces 776 * memory consumption when receiving lots 777 * of small packets. 778 * 779 * Otherwise, add a new buffer to the receive 780 * chain. If this fails, drop the packet and 781 * recycle the old buffer. 782 */ 783 if (len <= (MHLEN - 2)) { 784 MGETHDR(m, M_DONTWAIT, MT_DATA); 785 if (m == NULL) 786 goto dropit; 787 m->m_data += 2; 788 memcpy(mtod(m, void *), 789 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 790 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 791 } else { 792 m = sc->bce_cdata.bce_rx_chain[i]; 793 if (bce_add_rxbuf(sc, i) != 0) { 794 dropit: 795 ifp->if_ierrors++; 796 /* continue to use old buffer */ 797 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 798 bus_dmamap_sync(sc->bce_dmatag, 799 sc->bce_cdata.bce_rx_map[i], 0, 800 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 801 BUS_DMASYNC_PREREAD); 802 continue; 803 } 804 } 805 806 m->m_pkthdr.rcvif = ifp; 807 m->m_pkthdr.len = m->m_len = len; 808 ifp->if_ipackets++; 809 810 /* 811 * Pass this up to any BPF listeners, but only 812 * pass it up the stack if it's for us. 813 */ 814 bpf_mtap(ifp, m); 815 816 /* Pass it on. */ 817 (*ifp->if_input) (ifp, m); 818 819 /* re-check current in case it changed */ 820 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 821 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 822 sizeof(struct bce_dma_slot); 823 if (curr >= BCE_NRXDESC) 824 curr = BCE_NRXDESC - 1; 825 } 826 sc->bce_rxin = curr; 827 } 828 829 /* Transmit interrupt handler */ 830 void 831 bce_txintr(struct bce_softc *sc) 832 { 833 struct ifnet *ifp = &sc->ethercom.ec_if; 834 int curr; 835 int i; 836 837 ifp->if_flags &= ~IFF_OACTIVE; 838 839 /* 840 * Go through the Tx list and free mbufs for those 841 * frames which have been transmitted. 842 */ 843 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 844 RS_CD_MASK; 845 curr = curr / sizeof(struct bce_dma_slot); 846 if (curr >= BCE_NTXDESC) 847 curr = BCE_NTXDESC - 1; 848 for (i = sc->bce_txin; i != curr; 849 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 850 /* do any post dma memory ops on transmit data */ 851 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 852 continue; 853 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 854 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 855 BUS_DMASYNC_POSTWRITE); 856 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 857 m_freem(sc->bce_cdata.bce_tx_chain[i]); 858 sc->bce_cdata.bce_tx_chain[i] = NULL; 859 ifp->if_opackets++; 860 } 861 sc->bce_txin = curr; 862 863 /* 864 * If there are no more pending transmissions, cancel the watchdog 865 * timer 866 */ 867 if (sc->bce_txsnext == sc->bce_txin) 868 ifp->if_timer = 0; 869 } 870 871 /* initialize the interface */ 872 static int 873 bce_init(struct ifnet *ifp) 874 { 875 struct bce_softc *sc = ifp->if_softc; 876 uint32_t reg_win; 877 int error; 878 int i; 879 880 /* Cancel any pending I/O. */ 881 bce_stop(ifp, 0); 882 883 /* enable pci inerrupts, bursts, and prefetch */ 884 885 /* remap the pci registers to the Sonics config registers */ 886 887 /* save the current map, so it can be restored */ 888 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 889 BCE_REG_WIN); 890 891 /* set register window to Sonics registers */ 892 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 893 BCE_SONICS_WIN); 894 895 /* enable SB to PCI interrupt */ 896 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 897 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 898 SBIV_ENET0); 899 900 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 901 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 902 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 903 SBTOPCI_PREF | SBTOPCI_BURST); 904 905 /* restore to ethernet register space */ 906 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 907 reg_win); 908 909 /* Reset the chip to a known state. */ 910 bce_reset(sc); 911 912 /* Initialize transmit descriptors */ 913 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 914 sc->bce_txsnext = 0; 915 sc->bce_txin = 0; 916 917 /* enable crc32 generation */ 918 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 919 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 920 BCE_EMC_CG); 921 922 /* setup DMA interrupt control */ 923 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 924 925 /* setup packet filter */ 926 bce_set_filter(ifp); 927 928 /* set max frame length, account for possible vlan tag */ 929 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 930 ETHER_MAX_LEN + 32); 931 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 932 ETHER_MAX_LEN + 32); 933 934 /* set tx watermark */ 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 936 937 /* enable transmit */ 938 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 939 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 940 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 941 942 /* 943 * Give the receive ring to the chip, and 944 * start the receive DMA engine. 945 */ 946 sc->bce_rxin = 0; 947 948 /* clear the rx descriptor ring */ 949 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 950 /* enable receive */ 951 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 952 30 << 1 | 1); /* MAGIC */ 953 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 954 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 955 956 /* Initalize receive descriptors */ 957 for (i = 0; i < BCE_NRXDESC; i++) { 958 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 959 if ((error = bce_add_rxbuf(sc, i)) != 0) { 960 aprint_error_dev(sc->bce_dev, 961 "unable to allocate or map rx(%d) " 962 "mbuf, error = %d\n", i, error); 963 bce_rxdrain(sc); 964 return (error); 965 } 966 } else 967 BCE_INIT_RXDESC(sc, i); 968 } 969 970 /* Enable interrupts */ 971 sc->bce_intmask = 972 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 973 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 974 sc->bce_intmask); 975 976 /* start the receive dma */ 977 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 978 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 979 980 /* set media */ 981 if ((error = ether_mediachange(ifp)) != 0) 982 return error; 983 984 /* turn on the ethernet mac */ 985 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 986 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 987 BCE_ENET_CTL) | EC_EE); 988 989 /* start timer */ 990 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 991 992 /* mark as running, and no outputs active */ 993 ifp->if_flags |= IFF_RUNNING; 994 ifp->if_flags &= ~IFF_OACTIVE; 995 996 return 0; 997 } 998 999 /* add a mac address to packet filter */ 1000 void 1001 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1002 { 1003 int i; 1004 uint32_t rval; 1005 1006 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1007 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1008 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1009 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1010 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1011 idx << 16 | 8); /* MAGIC */ 1012 /* wait for write to complete */ 1013 for (i = 0; i < 100; i++) { 1014 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1015 BCE_FILT_CTL); 1016 if (!(rval & 0x80000000)) /* MAGIC */ 1017 break; 1018 delay(10); 1019 } 1020 if (i == 100) { 1021 aprint_error_dev(sc->bce_dev, 1022 "timed out writing pkt filter ctl\n"); 1023 } 1024 } 1025 1026 /* Add a receive buffer to the indiciated descriptor. */ 1027 static int 1028 bce_add_rxbuf(struct bce_softc *sc, int idx) 1029 { 1030 struct mbuf *m; 1031 int error; 1032 1033 MGETHDR(m, M_DONTWAIT, MT_DATA); 1034 if (m == NULL) 1035 return (ENOBUFS); 1036 1037 MCLGET(m, M_DONTWAIT); 1038 if ((m->m_flags & M_EXT) == 0) { 1039 m_freem(m); 1040 return (ENOBUFS); 1041 } 1042 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1043 bus_dmamap_unload(sc->bce_dmatag, 1044 sc->bce_cdata.bce_rx_map[idx]); 1045 1046 sc->bce_cdata.bce_rx_chain[idx] = m; 1047 1048 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1049 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1050 BUS_DMA_READ | BUS_DMA_NOWAIT); 1051 if (error) 1052 return (error); 1053 1054 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1055 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1056 1057 BCE_INIT_RXDESC(sc, idx); 1058 1059 return (0); 1060 1061 } 1062 1063 /* Drain the receive queue. */ 1064 static void 1065 bce_rxdrain(struct bce_softc *sc) 1066 { 1067 int i; 1068 1069 for (i = 0; i < BCE_NRXDESC; i++) { 1070 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1071 bus_dmamap_unload(sc->bce_dmatag, 1072 sc->bce_cdata.bce_rx_map[i]); 1073 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1074 sc->bce_cdata.bce_rx_chain[i] = NULL; 1075 } 1076 } 1077 } 1078 1079 /* Stop transmission on the interface */ 1080 static void 1081 bce_stop(struct ifnet *ifp, int disable) 1082 { 1083 struct bce_softc *sc = ifp->if_softc; 1084 int i; 1085 uint32_t val; 1086 1087 /* Stop the 1 second timer */ 1088 callout_stop(&sc->bce_timeout); 1089 1090 /* Down the MII. */ 1091 mii_down(&sc->bce_mii); 1092 1093 /* Disable interrupts. */ 1094 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1095 sc->bce_intmask = 0; 1096 delay(10); 1097 1098 /* Disable emac */ 1099 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1100 for (i = 0; i < 200; i++) { 1101 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1102 BCE_ENET_CTL); 1103 if (!(val & EC_ED)) 1104 break; 1105 delay(10); 1106 } 1107 1108 /* Stop the DMA */ 1109 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1110 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1111 delay(10); 1112 1113 /* Release any queued transmit buffers. */ 1114 for (i = 0; i < BCE_NTXDESC; i++) { 1115 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1116 bus_dmamap_unload(sc->bce_dmatag, 1117 sc->bce_cdata.bce_tx_map[i]); 1118 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1119 sc->bce_cdata.bce_tx_chain[i] = NULL; 1120 } 1121 } 1122 1123 /* Mark the interface down and cancel the watchdog timer. */ 1124 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1125 ifp->if_timer = 0; 1126 1127 /* drain receive queue */ 1128 if (disable) 1129 bce_rxdrain(sc); 1130 } 1131 1132 /* reset the chip */ 1133 static void 1134 bce_reset(struct bce_softc *sc) 1135 { 1136 uint32_t val; 1137 uint32_t sbval; 1138 int i; 1139 1140 /* if SB core is up */ 1141 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1142 BCE_SBTMSTATELOW); 1143 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1144 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1145 0); 1146 1147 /* disable emac */ 1148 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1149 EC_ED); 1150 for (i = 0; i < 200; i++) { 1151 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1152 BCE_ENET_CTL); 1153 if (!(val & EC_ED)) 1154 break; 1155 delay(10); 1156 } 1157 if (i == 200) { 1158 aprint_error_dev(sc->bce_dev, 1159 "timed out disabling ethernet mac\n"); 1160 } 1161 1162 /* reset the dma engines */ 1163 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1164 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1165 /* if error on receive, wait to go idle */ 1166 if (val & RS_ERROR) { 1167 for (i = 0; i < 100; i++) { 1168 val = bus_space_read_4(sc->bce_btag, 1169 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1170 if (val & RS_DMA_IDLE) 1171 break; 1172 delay(10); 1173 } 1174 if (i == 100) { 1175 aprint_error_dev(sc->bce_dev, 1176 "receive dma did not go idle after" 1177 " error\n"); 1178 } 1179 } 1180 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1181 BCE_DMA_RXSTATUS, 0); 1182 1183 /* reset ethernet mac */ 1184 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1185 EC_ES); 1186 for (i = 0; i < 200; i++) { 1187 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1188 BCE_ENET_CTL); 1189 if (!(val & EC_ES)) 1190 break; 1191 delay(10); 1192 } 1193 if (i == 200) { 1194 aprint_error_dev(sc->bce_dev, 1195 "timed out resetting ethernet mac\n"); 1196 } 1197 } else { 1198 uint32_t reg_win; 1199 1200 /* remap the pci registers to the Sonics config registers */ 1201 1202 /* save the current map, so it can be restored */ 1203 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1204 BCE_REG_WIN); 1205 /* set register window to Sonics registers */ 1206 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1207 BCE_REG_WIN, BCE_SONICS_WIN); 1208 1209 /* enable SB to PCI interrupt */ 1210 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1211 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1212 BCE_SBINTVEC) | 1213 SBIV_ENET0); 1214 1215 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1216 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1217 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1218 BCE_SPCI_TR2) | 1219 SBTOPCI_PREF | SBTOPCI_BURST); 1220 1221 /* restore to ethernet register space */ 1222 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1223 reg_win); 1224 } 1225 1226 /* disable SB core if not in reset */ 1227 if (!(sbval & SBTML_RESET)) { 1228 1229 /* set the reject bit */ 1230 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1231 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1232 for (i = 0; i < 200; i++) { 1233 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1234 BCE_SBTMSTATELOW); 1235 if (val & SBTML_REJ) 1236 break; 1237 delay(1); 1238 } 1239 if (i == 200) { 1240 aprint_error_dev(sc->bce_dev, 1241 "while resetting core, reject did not set\n"); 1242 } 1243 /* wait until busy is clear */ 1244 for (i = 0; i < 200; i++) { 1245 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1246 BCE_SBTMSTATEHI); 1247 if (!(val & 0x4)) 1248 break; 1249 delay(1); 1250 } 1251 if (i == 200) { 1252 aprint_error_dev(sc->bce_dev, 1253 "while resetting core, busy did not clear\n"); 1254 } 1255 /* set reset and reject while enabling the clocks */ 1256 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1257 BCE_SBTMSTATELOW, 1258 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1259 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1260 BCE_SBTMSTATELOW); 1261 delay(10); 1262 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1263 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1264 delay(1); 1265 } 1266 /* enable clock */ 1267 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1268 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1269 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1270 delay(1); 1271 1272 /* clear any error bits that may be on */ 1273 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1274 if (val & 1) 1275 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1276 0); 1277 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1278 if (val & SBIM_MAGIC_ERRORBITS) 1279 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1280 val & ~SBIM_MAGIC_ERRORBITS); 1281 1282 /* clear reset and allow it to propagate throughout the core */ 1283 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1284 SBTML_FGC | SBTML_CLK); 1285 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1286 delay(1); 1287 1288 /* leave clock enabled */ 1289 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1290 SBTML_CLK); 1291 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1292 delay(1); 1293 1294 /* initialize MDC preamble, frequency */ 1295 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1296 1297 /* enable phy, differs for internal, and external */ 1298 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1299 if (!(val & BCE_DC_IP)) { 1300 /* select external phy */ 1301 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1302 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1303 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1304 val & ~BCE_DC_ER); 1305 delay(100); 1306 } 1307 } 1308 1309 /* Set up the receive filter. */ 1310 void 1311 bce_set_filter(struct ifnet *ifp) 1312 { 1313 struct bce_softc *sc = ifp->if_softc; 1314 1315 if (ifp->if_flags & IFF_PROMISC) { 1316 ifp->if_flags |= IFF_ALLMULTI; 1317 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1318 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1319 | ERC_PE); 1320 } else { 1321 ifp->if_flags &= ~IFF_ALLMULTI; 1322 1323 /* turn off promiscuous */ 1324 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1325 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1326 BCE_RX_CTL) & ~ERC_PE); 1327 1328 /* enable/disable broadcast */ 1329 if (ifp->if_flags & IFF_BROADCAST) 1330 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1331 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1332 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1333 else 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1335 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1336 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1337 1338 /* disable the filter */ 1339 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1340 0); 1341 1342 /* add our own address */ 1343 bce_add_mac(sc, sc->enaddr, 0); 1344 1345 /* for now accept all multicast */ 1346 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1347 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1348 ERC_AM); 1349 ifp->if_flags |= IFF_ALLMULTI; 1350 1351 /* enable the filter */ 1352 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1353 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1354 BCE_FILT_CTL) | 1); 1355 } 1356 } 1357 1358 static bool 1359 bce_resume(device_t self, const pmf_qual_t *qual) 1360 { 1361 struct bce_softc *sc = device_private(self); 1362 1363 bce_reset(sc); 1364 1365 return true; 1366 } 1367 1368 /* Read a PHY register on the MII. */ 1369 int 1370 bce_mii_read(device_t self, int phy, int reg) 1371 { 1372 struct bce_softc *sc = device_private(self); 1373 int i; 1374 uint32_t val; 1375 1376 /* clear mii_int */ 1377 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1378 1379 /* Read the PHY register */ 1380 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1381 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1382 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1383 1384 for (i = 0; i < BCE_TIMEOUT; i++) { 1385 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1386 if (val & BCE_MIINTR) 1387 break; 1388 delay(10); 1389 } 1390 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1391 if (i == BCE_TIMEOUT) { 1392 aprint_error_dev(sc->bce_dev, 1393 "PHY read timed out reading phy %d, reg %d, val = " 1394 "0x%08x\n", phy, reg, val); 1395 return (0); 1396 } 1397 return (val & BCE_MICOMM_DATA); 1398 } 1399 1400 /* Write a PHY register on the MII */ 1401 void 1402 bce_mii_write(device_t self, int phy, int reg, int val) 1403 { 1404 struct bce_softc *sc = device_private(self); 1405 int i; 1406 uint32_t rval; 1407 1408 /* clear mii_int */ 1409 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1410 BCE_MIINTR); 1411 1412 /* Write the PHY register */ 1413 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1414 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1415 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1416 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1417 1418 /* wait for write to complete */ 1419 for (i = 0; i < BCE_TIMEOUT; i++) { 1420 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1421 BCE_MI_STS); 1422 if (rval & BCE_MIINTR) 1423 break; 1424 delay(10); 1425 } 1426 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1427 if (i == BCE_TIMEOUT) { 1428 aprint_error_dev(sc->bce_dev, 1429 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1430 reg, val); 1431 } 1432 } 1433 1434 /* sync hardware duplex mode to software state */ 1435 void 1436 bce_statchg(device_t self) 1437 { 1438 struct bce_softc *sc = device_private(self); 1439 uint32_t reg; 1440 1441 /* if needed, change register to match duplex mode */ 1442 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1443 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1444 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1445 reg | EXC_FD); 1446 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1447 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1448 reg & ~EXC_FD); 1449 1450 /* 1451 * Enable activity led. 1452 * XXX This should be in a phy driver, but not currently. 1453 */ 1454 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1455 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1456 /* enable traffic meter led mode */ 1457 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1458 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1459 } 1460 1461 /* One second timer, checks link status */ 1462 static void 1463 bce_tick(void *v) 1464 { 1465 struct bce_softc *sc = v; 1466 1467 /* Tick the MII. */ 1468 mii_tick(&sc->bce_mii); 1469 1470 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1471 } 1472
Indexes created Tue Sep 30 20:09:53 GMT 2025