if_bce.c revision 1.4
1 /* $NetBSD: if_bce.c,v 1.4 2004/04/23 16:03:33 joda Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/miidevs.h> 66 #include <dev/mii/brgphyreg.h> 67 68 #include <dev/pci/if_bcereg.h> 69 70 #include <uvm/uvm_extern.h> 71 72 /* transmit buffer max frags allowed */ 73 #define BCE_NTXFRAGS 16 74 75 /* ring descriptor */ 76 struct bce_dma_slot { 77 u_int32_t ctrl; 78 u_int32_t addr; 79 }; 80 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 81 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 82 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 83 #define CTRL_EOF 0x40000000 /* end of frame */ 84 #define CTRL_SOF 0x80000000 /* start of frame */ 85 86 /* Packet status is returned in a pre-packet header */ 87 struct rx_pph { 88 u_int16_t len; 89 u_int16_t flags; 90 u_int16_t pad[12]; 91 }; 92 93 /* packet status flags bits */ 94 #define RXF_NO 0x8 /* odd number of nibbles */ 95 #define RXF_RXER 0x4 /* receive symbol error */ 96 #define RXF_CRC 0x2 /* crc error */ 97 #define RXF_OV 0x1 /* fifo overflow */ 98 99 /* number of descriptors used in a ring */ 100 #define BCE_NRXDESC 128 101 #define BCE_NTXDESC 128 102 103 /* 104 * Mbuf pointers. We need these to keep track of the virtual addresses 105 * of our mbuf chains since we can only convert from physical to virtual, 106 * not the other way around. 107 */ 108 struct bce_chain_data { 109 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 110 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 111 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 112 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 113 }; 114 115 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 116 117 struct bce_softc { 118 struct device bce_dev; 119 bus_space_tag_t bce_btag; 120 bus_space_handle_t bce_bhandle; 121 bus_dma_tag_t bce_dmatag; 122 struct ethercom ethercom; /* interface info */ 123 void *bce_intrhand; 124 struct pci_attach_args bce_pa; 125 struct mii_data bce_mii; 126 u_int32_t bce_phy; /* eeprom indicated phy */ 127 struct ifmedia bce_ifmedia; /* media info *//* Check */ 128 u_int8_t enaddr[ETHER_ADDR_LEN]; 129 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 130 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 131 struct bce_chain_data bce_cdata; /* mbufs */ 132 bus_dmamap_t bce_ring_map; 133 u_int32_t bce_rxin; /* last rx descriptor seen */ 134 u_int32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 struct callout bce_timeout; 138 }; 139 140 /* for ring descriptors */ 141 #define BCE_RXBUF_LEN (MCLBYTES - 4) 142 #define BCE_INIT_RXDESC(sc, x) \ 143 do { \ 144 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 145 \ 146 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 147 __bced->addr = \ 148 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 149 + 0x40000000); \ 150 if (x != (BCE_NRXDESC - 1)) \ 151 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 152 else \ 153 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 154 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 155 sizeof(struct bce_dma_slot) * x, \ 156 sizeof(struct bce_dma_slot), \ 157 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 158 } while (/* CONSTCOND */ 0) 159 160 static int bce_probe(struct device *, struct cfdata *, void *); 161 static void bce_attach(struct device *, struct device *, void *); 162 static int bce_ioctl(struct ifnet *, u_long, caddr_t); 163 static void bce_start(struct ifnet *); 164 static void bce_watchdog(struct ifnet *); 165 static int bce_intr(void *); 166 static void bce_rxintr(struct bce_softc *); 167 static void bce_txintr(struct bce_softc *); 168 static int bce_init(struct ifnet *); 169 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 170 static int bce_add_rxbuf(struct bce_softc *, int); 171 static void bce_rxdrain(struct bce_softc *); 172 static void bce_stop(struct ifnet *, int); 173 static void bce_reset(struct bce_softc *); 174 static void bce_set_filter(struct ifnet *); 175 static int bce_mii_read(struct device *, int, int); 176 static void bce_mii_write(struct device *, int, int, int); 177 static void bce_statchg(struct device *); 178 static int bce_mediachange(struct ifnet *); 179 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 180 static void bce_tick(void *); 181 182 #define BCE_DEBUG 183 #ifdef BCE_DEBUG 184 #define DPRINTF(x) do { \ 185 if (bcedebug) \ 186 printf x; \ 187 } while (/* CONSTCOND */ 0) 188 #define DPRINTFN(n,x) do { \ 189 if (bcedebug >= (n)) \ 190 printf x; \ 191 } while (/* CONSTCOND */ 0) 192 int bcedebug = 0; 193 #else 194 #define DPRINTF(x) 195 #define DPRINTFN(n,x) 196 #endif 197 198 #if __NetBSD_Version__ >= 106080000 199 CFATTACH_DECL(bce, sizeof(struct bce_softc), 200 bce_probe, bce_attach, NULL, NULL); 201 #else 202 struct cfattach bce_ca = { 203 sizeof(struct bce_softc), bce_probe, bce_attach 204 }; 205 #endif 206 207 #if __NetBSD_Version__ >= 106120000 208 #define APRINT_ERROR aprint_error 209 #define APRINT_NORMAL aprint_normal 210 #else 211 #define APRINT_ERROR printf 212 #define APRINT_NORMAL printf 213 #endif 214 215 216 static const struct bce_product { 217 pci_vendor_id_t bp_vendor; 218 pci_product_id_t bp_product; 219 const char *bp_name; 220 } bce_products[] = { 221 { 222 PCI_VENDOR_BROADCOM, 223 PCI_PRODUCT_BROADCOM_BCM4401, 224 "Broadcom BCM4401 10/100 Ethernet" 225 }, 226 { 227 0, 228 0, 229 NULL 230 }, 231 }; 232 233 static const struct bce_product * 234 bce_lookup(const struct pci_attach_args * pa) 235 { 236 const struct bce_product *bp; 237 238 for (bp = bce_products; bp->bp_name != NULL; bp++) { 239 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 240 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 241 return (bp); 242 } 243 244 return (NULL); 245 } 246 247 /* 248 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 249 * against drivers product list, and return its name if a match is found. 250 */ 251 int 252 bce_probe(parent, match, aux) 253 struct device *parent; 254 struct cfdata *match; 255 void *aux; 256 { 257 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 258 259 if (bce_lookup(pa) != NULL) 260 return (1); 261 262 return (0); 263 } 264 265 void 266 bce_attach(parent, self, aux) 267 struct device *parent, *self; 268 void *aux; 269 { 270 struct bce_softc *sc = (struct bce_softc *) self; 271 struct pci_attach_args *pa = aux; 272 const struct bce_product *bp; 273 pci_chipset_tag_t pc = pa->pa_pc; 274 pci_intr_handle_t ih; 275 const char *intrstr = NULL; 276 caddr_t kva; 277 bus_dma_segment_t seg; 278 int rseg; 279 u_int32_t command; 280 struct ifnet *ifp; 281 pcireg_t memtype; 282 bus_addr_t memaddr; 283 bus_size_t memsize; 284 int pmreg; 285 pcireg_t pmode; 286 int error; 287 int i; 288 289 bp = bce_lookup(pa); 290 KASSERT(bp != NULL); 291 292 sc->bce_pa = *pa; 293 sc->bce_dmatag = pa->pa_dmat; 294 295 #if __NetBSD_Version__ >= 106120000 296 aprint_naive(": Ethernet controller\n"); 297 #endif 298 APRINT_NORMAL(": %s\n", bp->bp_name); 299 300 /* 301 * Map control/status registers. 302 */ 303 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 305 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 306 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 307 308 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 309 APRINT_ERROR("%s: failed to enable memory mapping!\n", 310 sc->bce_dev.dv_xname); 311 return; 312 } 313 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 314 switch (memtype) { 315 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 316 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 317 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 318 &sc->bce_bhandle, &memaddr, &memsize) == 0) 319 break; 320 default: 321 APRINT_ERROR("%s: unable to find mem space\n", 322 sc->bce_dev.dv_xname); 323 return; 324 } 325 326 /* Get it out of power save mode if needed. */ 327 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 328 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 329 if (pmode == 3) { 330 /* 331 * The card has lost all configuration data in 332 * this state, so punt. 333 */ 334 printf("%s: unable to wake up from power state D3\n", 335 sc->bce_dev.dv_xname); 336 return; 337 } 338 if (pmode != 0) { 339 printf("%s: waking up from power state D%d\n", 340 sc->bce_dev.dv_xname, pmode); 341 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 342 } 343 } 344 if (pci_intr_map(pa, &ih)) { 345 APRINT_ERROR("%s: couldn't map interrupt\n", 346 sc->bce_dev.dv_xname); 347 return; 348 } 349 intrstr = pci_intr_string(pc, ih); 350 351 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 352 353 if (sc->bce_intrhand == NULL) { 354 APRINT_ERROR("%s: couldn't establish interrupt", 355 sc->bce_dev.dv_xname); 356 if (intrstr != NULL) 357 APRINT_NORMAL(" at %s", intrstr); 358 APRINT_NORMAL("\n"); 359 return; 360 } 361 APRINT_NORMAL("%s: interrupting at %s\n", 362 sc->bce_dev.dv_xname, intrstr); 363 364 /* reset the chip */ 365 bce_reset(sc); 366 367 /* 368 * Allocate DMA-safe memory for ring descriptors. 369 * The receive, and transmit rings can not share the same 370 * 4k space, however both are allocated at once here. 371 */ 372 /* 373 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 374 * due to the limition above. ?? 375 */ 376 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 377 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 378 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 379 printf("%s: unable to alloc space for ring descriptors, " 380 "error = %d\n", sc->bce_dev.dv_xname, error); 381 return; 382 } 383 /* map ring space to kernel */ 384 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 385 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 386 printf("%s: unable to map DMA buffers, error = %d\n", 387 sc->bce_dev.dv_xname, error); 388 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 389 return; 390 } 391 /* create a dma map for the ring */ 392 if ((error = bus_dmamap_create(sc->bce_dmatag, 393 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 394 &sc->bce_ring_map))) { 395 printf("%s: unable to create ring DMA map, error = %d\n", 396 sc->bce_dev.dv_xname, error); 397 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 398 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 399 return; 400 } 401 /* connect the ring space to the dma map */ 402 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 403 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 404 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 405 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 406 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 407 return; 408 } 409 /* save the ring space in softc */ 410 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 411 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 412 413 /* Create the transmit buffer DMA maps. */ 414 for (i = 0; i < BCE_NTXDESC; i++) { 415 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 416 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 417 printf("%s: unable to create tx DMA map, error = %d\n", 418 sc->bce_dev.dv_xname, error); 419 } 420 sc->bce_cdata.bce_tx_chain[i] = NULL; 421 } 422 423 /* Create the receive buffer DMA maps. */ 424 for (i = 0; i < BCE_NRXDESC; i++) { 425 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 426 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 427 printf("%s: unable to create rx DMA map, error = %d\n", 428 sc->bce_dev.dv_xname, error); 429 } 430 sc->bce_cdata.bce_rx_chain[i] = NULL; 431 } 432 433 /* Set up ifnet structure */ 434 ifp = &sc->ethercom.ec_if; 435 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 436 ifp->if_softc = sc; 437 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 438 ifp->if_ioctl = bce_ioctl; 439 ifp->if_start = bce_start; 440 ifp->if_watchdog = bce_watchdog; 441 ifp->if_init = bce_init; 442 ifp->if_stop = bce_stop; 443 IFQ_SET_READY(&ifp->if_snd); 444 445 /* Initialize our media structures and probe the MII. */ 446 447 sc->bce_mii.mii_ifp = ifp; 448 sc->bce_mii.mii_readreg = bce_mii_read; 449 sc->bce_mii.mii_writereg = bce_mii_write; 450 sc->bce_mii.mii_statchg = bce_statchg; 451 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 452 bce_mediastatus); 453 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 454 MII_OFFSET_ANY, 0); 455 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 456 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 457 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 458 } else 459 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 460 /* get the phy */ 461 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 462 BCE_MAGIC_PHY) & 0x1f; 463 /* 464 * Enable activity led. 465 * XXX This should be in a phy driver, but not currently. 466 */ 467 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 468 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 469 /* enable traffic meter led mode */ 470 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 471 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 472 473 474 /* Attach the interface */ 475 if_attach(ifp); 476 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 477 BCE_MAGIC_ENET0); 478 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 479 BCE_MAGIC_ENET1); 480 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 481 BCE_MAGIC_ENET2); 482 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 483 BCE_MAGIC_ENET3); 484 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 485 BCE_MAGIC_ENET4); 486 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 487 BCE_MAGIC_ENET5); 488 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 489 ether_sprintf(sc->enaddr)); 490 ether_ifattach(ifp, sc->enaddr); 491 callout_init(&sc->bce_timeout); 492 } 493 494 /* handle media, and ethernet requests */ 495 static int 496 bce_ioctl(ifp, cmd, data) 497 struct ifnet *ifp; 498 u_long cmd; 499 caddr_t data; 500 { 501 struct bce_softc *sc = ifp->if_softc; 502 struct ifreq *ifr = (struct ifreq *) data; 503 int s, error; 504 505 s = splnet(); 506 switch (cmd) { 507 case SIOCSIFMEDIA: 508 case SIOCGIFMEDIA: 509 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 510 break; 511 default: 512 error = ether_ioctl(ifp, cmd, data); 513 if (error == ENETRESET) { 514 /* change multicast list */ 515 error = 0; 516 } 517 break; 518 } 519 520 /* Try to get more packets going. */ 521 bce_start(ifp); 522 523 splx(s); 524 return error; 525 } 526 527 /* Start packet transmission on the interface. */ 528 static void 529 bce_start(ifp) 530 struct ifnet *ifp; 531 { 532 struct bce_softc *sc = ifp->if_softc; 533 struct mbuf *m0; 534 bus_dmamap_t dmamap; 535 int txstart; 536 int txsfree; 537 int newpkts = 0; 538 int error; 539 540 /* 541 * do not start another if currently transmitting, and more 542 * descriptors(tx slots) are needed for next packet. 543 */ 544 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 545 return; 546 547 /* determine number of descriptors available */ 548 if (sc->bce_txsnext >= sc->bce_txin) 549 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 550 else 551 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 552 553 /* 554 * Loop through the send queue, setting up transmit descriptors 555 * until we drain the queue, or use up all available transmit 556 * descriptors. 557 */ 558 while (txsfree > 0) { 559 int seg; 560 561 /* Grab a packet off the queue. */ 562 IFQ_POLL(&ifp->if_snd, m0); 563 if (m0 == NULL) 564 break; 565 566 /* get the transmit slot dma map */ 567 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 568 569 /* 570 * Load the DMA map. If this fails, the packet either 571 * didn't fit in the alloted number of segments, or we 572 * were short on resources. If the packet will not fit, 573 * it will be dropped. If short on resources, it will 574 * be tried again later. 575 */ 576 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 577 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 578 if (error == EFBIG) { 579 printf("%s: Tx packet consumes too many DMA segments, " 580 "dropping...\n", sc->bce_dev.dv_xname); 581 IFQ_DEQUEUE(&ifp->if_snd, m0); 582 m_freem(m0); 583 ifp->if_oerrors++; 584 continue; 585 } else if (error) { 586 /* short on resources, come back later */ 587 printf("%s: unable to load Tx buffer, error = %d\n", 588 sc->bce_dev.dv_xname, error); 589 break; 590 } 591 /* If not enough descriptors available, try again later */ 592 if (dmamap->dm_nsegs > txsfree) { 593 ifp->if_flags |= IFF_OACTIVE; 594 bus_dmamap_unload(sc->bce_dmatag, dmamap); 595 break; 596 } 597 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 598 599 /* So take it off the queue */ 600 IFQ_DEQUEUE(&ifp->if_snd, m0); 601 602 /* save the pointer so it can be freed later */ 603 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 604 605 /* Sync the data DMA map. */ 606 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 607 BUS_DMASYNC_PREWRITE); 608 609 /* Initialize the transmit descriptor(s). */ 610 txstart = sc->bce_txsnext; 611 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 612 u_int32_t ctrl; 613 614 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 615 if (seg == 0) 616 ctrl |= CTRL_SOF; 617 if (seg == dmamap->dm_nsegs - 1) 618 ctrl |= CTRL_EOF; 619 if (sc->bce_txsnext == BCE_NTXDESC - 1) 620 ctrl |= CTRL_EOT; 621 ctrl |= CTRL_IOC; 622 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 623 sc->bce_tx_ring[sc->bce_txsnext].addr = 624 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 625 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 626 sc->bce_txsnext = 0; 627 else 628 sc->bce_txsnext++; 629 txsfree--; 630 } 631 /* sync descriptors being used */ 632 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 633 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 634 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 635 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 636 637 /* Give the packet to the chip. */ 638 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 639 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 640 641 newpkts++; 642 643 #if NBPFILTER > 0 644 /* Pass the packet to any BPF listeners. */ 645 if (ifp->if_bpf) 646 bpf_mtap(ifp->if_bpf, m0); 647 #endif /* NBPFILTER > 0 */ 648 } 649 if (txsfree == 0) { 650 /* No more slots left; notify upper layer. */ 651 ifp->if_flags |= IFF_OACTIVE; 652 } 653 if (newpkts) { 654 /* Set a watchdog timer in case the chip flakes out. */ 655 ifp->if_timer = 5; 656 } 657 } 658 659 /* Watchdog timer handler. */ 660 static void 661 bce_watchdog(ifp) 662 struct ifnet *ifp; 663 { 664 struct bce_softc *sc = ifp->if_softc; 665 666 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 667 ifp->if_oerrors++; 668 669 (void) bce_init(ifp); 670 671 /* Try to get more packets going. */ 672 bce_start(ifp); 673 } 674 675 int 676 bce_intr(xsc) 677 void *xsc; 678 { 679 struct bce_softc *sc; 680 struct ifnet *ifp; 681 u_int32_t intstatus; 682 u_int32_t intmask; 683 int wantinit; 684 int handled = 0; 685 686 sc = xsc; 687 ifp = &sc->ethercom.ec_if; 688 689 690 for (wantinit = 0; wantinit == 0;) { 691 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 692 BCE_INT_STS); 693 intmask = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 694 BCE_INT_MASK); 695 696 /* ignore if not ours, or unsolicited interrupts */ 697 intstatus &= intmask; 698 if (intstatus == 0) 699 break; 700 701 handled = 1; 702 703 /* Ack interrupt */ 704 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 705 intstatus); 706 707 /* Receive interrupts. */ 708 if (intstatus & I_RI) 709 bce_rxintr(sc); 710 /* Transmit interrupts. */ 711 if (intstatus & I_XI) 712 bce_txintr(sc); 713 /* Error interrupts */ 714 if (intstatus & ~(I_RI | I_XI)) { 715 if (intstatus & I_XU) 716 printf("%s: transmit fifo underflow\n", 717 sc->bce_dev.dv_xname); 718 if (intstatus & I_RO) { 719 printf("%s: receive fifo overflow\n", 720 sc->bce_dev.dv_xname); 721 ifp->if_ierrors++; 722 } 723 if (intstatus & I_RU) 724 printf("%s: receive descriptor underflow\n", 725 sc->bce_dev.dv_xname); 726 if (intstatus & I_DE) 727 printf("%s: descriptor protocol error\n", 728 sc->bce_dev.dv_xname); 729 if (intstatus & I_PD) 730 printf("%s: data error\n", 731 sc->bce_dev.dv_xname); 732 if (intstatus & I_PC) 733 printf("%s: descriptor error\n", 734 sc->bce_dev.dv_xname); 735 if (intstatus & I_TO) 736 printf("%s: general purpose timeout\n", 737 sc->bce_dev.dv_xname); 738 wantinit = 1; 739 } 740 } 741 742 if (handled) { 743 if (wantinit) 744 bce_init(ifp); 745 /* Try to get more packets going. */ 746 bce_start(ifp); 747 } 748 return (handled); 749 } 750 751 /* Receive interrupt handler */ 752 void 753 bce_rxintr(sc) 754 struct bce_softc *sc; 755 { 756 struct ifnet *ifp = &sc->ethercom.ec_if; 757 struct rx_pph *pph; 758 struct mbuf *m; 759 int curr; 760 int len; 761 int i; 762 763 /* get pointer to active receive slot */ 764 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 765 & RS_CD_MASK; 766 curr = curr / sizeof(struct bce_dma_slot); 767 if (curr >= BCE_NRXDESC) 768 curr = BCE_NRXDESC - 1; 769 770 /* process packets up to but not current packet being worked on */ 771 for (i = sc->bce_rxin; i != curr; 772 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 773 /* complete any post dma memory ops on packet */ 774 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 775 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 776 BUS_DMASYNC_POSTREAD); 777 778 /* 779 * If the packet had an error, simply recycle the buffer, 780 * resetting the len, and flags. 781 */ 782 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 783 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 784 ifp->if_ierrors++; 785 pph->len = 0; 786 pph->flags = 0; 787 continue; 788 } 789 /* receive the packet */ 790 len = pph->len; 791 if (len == 0) 792 continue; /* no packet if empty */ 793 pph->len = 0; 794 pph->flags = 0; 795 /* bump past pre header to packet */ 796 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 797 798 /* 799 * If the packet is small enough to fit in a 800 * single header mbuf, allocate one and copy 801 * the data into it. This greatly reduces 802 * memory consumption when receiving lots 803 * of small packets. 804 * 805 * Otherwise, add a new buffer to the receive 806 * chain. If this fails, drop the packet and 807 * recycle the old buffer. 808 */ 809 if (len <= (MHLEN - 2)) { 810 MGETHDR(m, M_DONTWAIT, MT_DATA); 811 if (m == NULL) 812 goto dropit; 813 m->m_data += 2; 814 memcpy(mtod(m, caddr_t), 815 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 816 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 817 } else { 818 m = sc->bce_cdata.bce_rx_chain[i]; 819 if (bce_add_rxbuf(sc, i) != 0) { 820 dropit: 821 ifp->if_ierrors++; 822 /* continue to use old buffer */ 823 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 824 bus_dmamap_sync(sc->bce_dmatag, 825 sc->bce_cdata.bce_rx_map[i], 0, 826 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 827 BUS_DMASYNC_PREREAD); 828 continue; 829 } 830 } 831 832 m->m_flags |= M_HASFCS; 833 m->m_pkthdr.rcvif = ifp; 834 m->m_pkthdr.len = m->m_len = len; 835 ifp->if_ipackets++; 836 837 #if NBPFILTER > 0 838 /* 839 * Pass this up to any BPF listeners, but only 840 * pass it up the stack if it's for us. 841 */ 842 if (ifp->if_bpf) 843 bpf_mtap(ifp->if_bpf, m); 844 #endif /* NBPFILTER > 0 */ 845 846 /* Pass it on. */ 847 (*ifp->if_input) (ifp, m); 848 849 /* re-check current in case it changed */ 850 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 851 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 852 sizeof(struct bce_dma_slot); 853 if (curr >= BCE_NRXDESC) 854 curr = BCE_NRXDESC - 1; 855 } 856 sc->bce_rxin = curr; 857 } 858 859 /* Transmit interrupt handler */ 860 void 861 bce_txintr(sc) 862 struct bce_softc *sc; 863 { 864 struct ifnet *ifp = &sc->ethercom.ec_if; 865 int curr; 866 int i; 867 868 ifp->if_flags &= ~IFF_OACTIVE; 869 870 /* 871 * Go through the Tx list and free mbufs for those 872 * frames which have been transmitted. 873 */ 874 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 875 RS_CD_MASK; 876 curr = curr / sizeof(struct bce_dma_slot); 877 if (curr >= BCE_NTXDESC) 878 curr = BCE_NTXDESC - 1; 879 for (i = sc->bce_txin; i != curr; 880 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 881 /* do any post dma memory ops on transmit data */ 882 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 883 continue; 884 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 885 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 886 BUS_DMASYNC_POSTWRITE); 887 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 888 m_freem(sc->bce_cdata.bce_tx_chain[i]); 889 sc->bce_cdata.bce_tx_chain[i] = NULL; 890 ifp->if_opackets++; 891 } 892 sc->bce_txin = curr; 893 894 /* 895 * If there are no more pending transmissions, cancel the watchdog 896 * timer 897 */ 898 if (sc->bce_txsnext == sc->bce_txin) 899 ifp->if_timer = 0; 900 } 901 902 /* initialize the interface */ 903 static int 904 bce_init(ifp) 905 struct ifnet *ifp; 906 { 907 struct bce_softc *sc = ifp->if_softc; 908 u_int32_t reg_win; 909 int error; 910 int i; 911 912 /* Cancel any pending I/O. */ 913 bce_stop(ifp, 0); 914 915 /* enable pci inerrupts, bursts, and prefetch */ 916 917 /* remap the pci registers to the Sonics config registers */ 918 919 /* save the current map, so it can be restored */ 920 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 921 BCE_REG_WIN); 922 923 /* set register window to Sonics registers */ 924 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 925 BCE_SONICS_WIN); 926 927 /* enable SB to PCI interrupt */ 928 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 929 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 930 SBIV_ENET0); 931 932 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 934 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 935 SBTOPCI_PREF | SBTOPCI_BURST); 936 937 /* restore to ethernet register space */ 938 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 939 reg_win); 940 941 /* Reset the chip to a known state. */ 942 bce_reset(sc); 943 944 /* Initialize transmit descriptors */ 945 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 946 sc->bce_txsnext = 0; 947 sc->bce_txin = 0; 948 949 /* enable crc32 generation */ 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 951 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 952 BCE_EMC_CG); 953 954 /* setup DMA interrupt control */ 955 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 956 957 /* setup packet filter */ 958 bce_set_filter(ifp); 959 960 /* set max frame length, account for possible vlan tag */ 961 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 962 ETHER_MAX_LEN + 32); 963 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 964 ETHER_MAX_LEN + 32); 965 966 /* set tx watermark */ 967 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 968 969 /* enable transmit */ 970 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 971 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 972 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 973 974 /* 975 * Give the receive ring to the chip, and 976 * start the receive DMA engine. 977 */ 978 sc->bce_rxin = 0; 979 980 /* clear the rx descriptor ring */ 981 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 982 /* enable receive */ 983 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 984 30 << 1 | 1); /* MAGIC */ 985 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 986 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 987 988 /* Initalize receive descriptors */ 989 for (i = 0; i < BCE_NRXDESC; i++) { 990 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 991 if ((error = bce_add_rxbuf(sc, i)) != 0) { 992 printf("%s: unable to allocate or map rx(%d) " 993 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 994 i, error); 995 bce_rxdrain(sc); 996 return (error); 997 } 998 } else 999 BCE_INIT_RXDESC(sc, i); 1000 } 1001 1002 /* Enable interrupts */ 1003 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 1004 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO); 1005 1006 /* start the receive dma */ 1007 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 1008 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1009 1010 /* set media */ 1011 mii_mediachg(&sc->bce_mii); 1012 1013 /* turn on the ethernet mac */ 1014 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1015 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1016 BCE_ENET_CTL) | EC_EE); 1017 1018 /* start timer */ 1019 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1020 1021 /* mark as running, and no outputs active */ 1022 ifp->if_flags |= IFF_RUNNING; 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 return 0; 1026 } 1027 1028 /* add a mac address to packet filter */ 1029 void 1030 bce_add_mac(sc, mac, idx) 1031 struct bce_softc *sc; 1032 u_int8_t *mac; 1033 unsigned long idx; 1034 { 1035 int i; 1036 u_int32_t rval; 1037 1038 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1039 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1040 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1041 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1042 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1043 idx << 16 | 8); /* MAGIC */ 1044 /* wait for write to complete */ 1045 for (i = 0; i < 100; i++) { 1046 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1047 BCE_FILT_CTL); 1048 if (!(rval & 0x80000000)) /* MAGIC */ 1049 break; 1050 delay(10); 1051 } 1052 if (i == 100) { 1053 printf("%s: timed out writting pkt filter ctl\n", 1054 sc->bce_dev.dv_xname); 1055 } 1056 } 1057 1058 /* Add a receive buffer to the indiciated descriptor. */ 1059 static int 1060 bce_add_rxbuf(sc, idx) 1061 struct bce_softc *sc; 1062 int idx; 1063 { 1064 struct mbuf *m; 1065 int error; 1066 1067 MGETHDR(m, M_DONTWAIT, MT_DATA); 1068 if (m == NULL) 1069 return (ENOBUFS); 1070 1071 MCLGET(m, M_DONTWAIT); 1072 if ((m->m_flags & M_EXT) == 0) { 1073 m_freem(m); 1074 return (ENOBUFS); 1075 } 1076 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1077 bus_dmamap_unload(sc->bce_dmatag, 1078 sc->bce_cdata.bce_rx_map[idx]); 1079 1080 sc->bce_cdata.bce_rx_chain[idx] = m; 1081 1082 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1083 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1084 BUS_DMA_READ | BUS_DMA_NOWAIT); 1085 if (error) 1086 return (error); 1087 1088 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1089 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1090 1091 BCE_INIT_RXDESC(sc, idx); 1092 1093 return (0); 1094 1095 } 1096 1097 /* Drain the receive queue. */ 1098 static void 1099 bce_rxdrain(sc) 1100 struct bce_softc *sc; 1101 { 1102 int i; 1103 1104 for (i = 0; i < BCE_NRXDESC; i++) { 1105 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1106 bus_dmamap_unload(sc->bce_dmatag, 1107 sc->bce_cdata.bce_rx_map[i]); 1108 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1109 sc->bce_cdata.bce_rx_chain[i] = NULL; 1110 } 1111 } 1112 } 1113 1114 /* Stop transmission on the interface */ 1115 static void 1116 bce_stop(ifp, disable) 1117 struct ifnet *ifp; 1118 int disable; 1119 { 1120 struct bce_softc *sc = ifp->if_softc; 1121 int i; 1122 u_int32_t val; 1123 1124 /* Stop the 1 second timer */ 1125 callout_stop(&sc->bce_timeout); 1126 1127 /* Down the MII. */ 1128 mii_down(&sc->bce_mii); 1129 1130 /* Disable interrupts. */ 1131 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1132 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK); 1133 1134 /* Disable emac */ 1135 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1136 for (i = 0; i < 200; i++) { 1137 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1138 BCE_ENET_CTL); 1139 if (!(val & EC_ED)) 1140 break; 1141 delay(10); 1142 } 1143 1144 /* Stop the DMA */ 1145 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1146 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1147 delay(10); 1148 1149 /* Release any queued transmit buffers. */ 1150 for (i = 0; i < BCE_NTXDESC; i++) { 1151 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1152 bus_dmamap_unload(sc->bce_dmatag, 1153 sc->bce_cdata.bce_tx_map[i]); 1154 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1155 sc->bce_cdata.bce_tx_chain[i] = NULL; 1156 } 1157 } 1158 1159 /* drain receive queue */ 1160 if (disable) 1161 bce_rxdrain(sc); 1162 1163 /* Mark the interface down and cancel the watchdog timer. */ 1164 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1165 ifp->if_timer = 0; 1166 } 1167 1168 /* reset the chip */ 1169 static void 1170 bce_reset(sc) 1171 struct bce_softc *sc; 1172 { 1173 u_int32_t val; 1174 u_int32_t sbval; 1175 int i; 1176 1177 /* if SB core is up */ 1178 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1179 BCE_SBTMSTATELOW); 1180 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1181 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1182 0); 1183 1184 /* disable emac */ 1185 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1186 EC_ED); 1187 for (i = 0; i < 200; i++) { 1188 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1189 BCE_ENET_CTL); 1190 if (!(val & EC_ED)) 1191 break; 1192 delay(10); 1193 } 1194 if (i == 200) 1195 printf("%s: timed out disabling ethernet mac\n", 1196 sc->bce_dev.dv_xname); 1197 1198 /* reset the dma engines */ 1199 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1200 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1201 /* if error on receive, wait to go idle */ 1202 if (val & RS_ERROR) { 1203 for (i = 0; i < 100; i++) { 1204 val = bus_space_read_4(sc->bce_btag, 1205 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1206 if (val & RS_DMA_IDLE) 1207 break; 1208 delay(10); 1209 } 1210 if (i == 100) 1211 printf("%s: receive dma did not go idle after" 1212 " error\n", sc->bce_dev.dv_xname); 1213 } 1214 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1215 BCE_DMA_RXSTATUS, 0); 1216 1217 /* reset ethernet mac */ 1218 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1219 EC_ES); 1220 for (i = 0; i < 200; i++) { 1221 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1222 BCE_ENET_CTL); 1223 if (!(val & EC_ES)) 1224 break; 1225 delay(10); 1226 } 1227 if (i == 200) 1228 printf("%s: timed out restting ethernet mac\n", 1229 sc->bce_dev.dv_xname); 1230 } else { 1231 u_int32_t reg_win; 1232 1233 /* remap the pci registers to the Sonics config registers */ 1234 1235 /* save the current map, so it can be restored */ 1236 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1237 BCE_REG_WIN); 1238 /* set register window to Sonics registers */ 1239 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1240 BCE_REG_WIN, BCE_SONICS_WIN); 1241 1242 /* enable SB to PCI interrupt */ 1243 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1244 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1245 BCE_SBINTVEC) | 1246 SBIV_ENET0); 1247 1248 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1249 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1250 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1251 BCE_SPCI_TR2) | 1252 SBTOPCI_PREF | SBTOPCI_BURST); 1253 1254 /* restore to ethernet register space */ 1255 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1256 reg_win); 1257 } 1258 1259 /* disable SB core if not in reset */ 1260 if (!(sbval & SBTML_RESET)) { 1261 1262 /* set the reject bit */ 1263 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1264 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1265 for (i = 0; i < 200; i++) { 1266 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1267 BCE_SBTMSTATELOW); 1268 if (val & SBTML_REJ) 1269 break; 1270 delay(1); 1271 } 1272 if (i == 200) 1273 printf("%s: while restting core, reject did not set\n", 1274 sc->bce_dev.dv_xname); 1275 /* wait until busy is clear */ 1276 for (i = 0; i < 200; i++) { 1277 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1278 BCE_SBTMSTATEHI); 1279 if (!(val & 0x4)) 1280 break; 1281 delay(1); 1282 } 1283 if (i == 200) 1284 printf("%s: while restting core, busy did not clear\n", 1285 sc->bce_dev.dv_xname); 1286 /* set reset and reject while enabling the clocks */ 1287 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1288 BCE_SBTMSTATELOW, 1289 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1290 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1291 BCE_SBTMSTATELOW); 1292 delay(10); 1293 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1294 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1295 delay(1); 1296 } 1297 /* enable clock */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1299 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1300 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1301 delay(1); 1302 1303 /* clear any error bits that may be on */ 1304 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1305 if (val & 1) 1306 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1307 0); 1308 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1309 if (val & SBIM_MAGIC_ERRORBITS) 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1311 val & ~SBIM_MAGIC_ERRORBITS); 1312 1313 /* clear reset and allow it to propagate throughout the core */ 1314 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1315 SBTML_FGC | SBTML_CLK); 1316 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1317 delay(1); 1318 1319 /* leave clock enabled */ 1320 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1321 SBTML_CLK); 1322 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1323 delay(1); 1324 1325 /* initialize MDC preamble, frequency */ 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1327 1328 /* enable phy, differs for internal, and external */ 1329 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1330 if (!(val & BCE_DC_IP)) { 1331 /* select external phy */ 1332 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1333 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1335 val & ~BCE_DC_ER); 1336 delay(100); 1337 } 1338 } 1339 1340 /* Set up the receive filter. */ 1341 void 1342 bce_set_filter(ifp) 1343 struct ifnet *ifp; 1344 { 1345 struct bce_softc *sc = ifp->if_softc; 1346 1347 if (ifp->if_flags & IFF_PROMISC) { 1348 ifp->if_flags |= IFF_ALLMULTI; 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1350 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1351 | ERC_PE); 1352 } else { 1353 ifp->if_flags &= ~IFF_ALLMULTI; 1354 1355 /* turn off promiscuous */ 1356 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1357 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1358 BCE_RX_CTL) & ~ERC_PE); 1359 1360 /* enable/disable broadcast */ 1361 if (ifp->if_flags & IFF_BROADCAST) 1362 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1363 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1364 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1365 else 1366 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1367 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1368 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1369 1370 /* disable the filter */ 1371 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1372 0); 1373 1374 /* add our own address */ 1375 bce_add_mac(sc, sc->enaddr, 0); 1376 1377 /* for now accept all multicast */ 1378 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1379 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1380 ERC_AM); 1381 ifp->if_flags |= IFF_ALLMULTI; 1382 1383 /* enable the filter */ 1384 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1385 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1386 BCE_FILT_CTL) | 1); 1387 } 1388 } 1389 1390 /* Read a PHY register on the MII. */ 1391 int 1392 bce_mii_read(self, phy, reg) 1393 struct device *self; 1394 int phy, reg; 1395 { 1396 struct bce_softc *sc = (struct bce_softc *) self; 1397 int i; 1398 u_int32_t val; 1399 1400 /* clear mii_int */ 1401 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1402 1403 /* Read the PHY register */ 1404 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1405 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1406 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1407 1408 for (i = 0; i < BCE_TIMEOUT; i++) { 1409 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1410 if (val & BCE_MIINTR) 1411 break; 1412 delay(10); 1413 } 1414 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1415 if (i == BCE_TIMEOUT) { 1416 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1417 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1418 return (0); 1419 } 1420 return (val & BCE_MICOMM_DATA); 1421 } 1422 1423 /* Write a PHY register on the MII */ 1424 void 1425 bce_mii_write(self, phy, reg, val) 1426 struct device *self; 1427 int phy, reg, val; 1428 { 1429 struct bce_softc *sc = (struct bce_softc *) self; 1430 int i; 1431 u_int32_t rval; 1432 1433 /* clear mii_int */ 1434 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1435 BCE_MIINTR); 1436 1437 /* Write the PHY register */ 1438 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1439 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1440 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1441 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1442 1443 /* wait for write to complete */ 1444 for (i = 0; i < BCE_TIMEOUT; i++) { 1445 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1446 BCE_MI_STS); 1447 if (rval & BCE_MIINTR) 1448 break; 1449 delay(10); 1450 } 1451 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1452 if (i == BCE_TIMEOUT) { 1453 printf("%s: PHY timed out writting phy %d, reg %d, val " 1454 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1455 } 1456 } 1457 1458 /* sync hardware duplex mode to software state */ 1459 void 1460 bce_statchg(self) 1461 struct device *self; 1462 { 1463 struct bce_softc *sc = (struct bce_softc *) self; 1464 u_int32_t reg; 1465 1466 /* if needed, change register to match duplex mode */ 1467 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1468 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1469 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1470 reg | EXC_FD); 1471 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1472 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1473 reg & ~EXC_FD); 1474 1475 /* 1476 * Enable activity led. 1477 * XXX This should be in a phy driver, but not currently. 1478 */ 1479 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1480 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1481 /* enable traffic meter led mode */ 1482 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1483 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1484 } 1485 1486 /* Set hardware to newly-selected media */ 1487 int 1488 bce_mediachange(ifp) 1489 struct ifnet *ifp; 1490 { 1491 struct bce_softc *sc = ifp->if_softc; 1492 1493 if (ifp->if_flags & IFF_UP) 1494 mii_mediachg(&sc->bce_mii); 1495 return (0); 1496 } 1497 1498 /* Get the current interface media status */ 1499 static void 1500 bce_mediastatus(ifp, ifmr) 1501 struct ifnet *ifp; 1502 struct ifmediareq *ifmr; 1503 { 1504 struct bce_softc *sc = ifp->if_softc; 1505 1506 mii_pollstat(&sc->bce_mii); 1507 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1508 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1509 } 1510 1511 /* One second timer, checks link status */ 1512 static void 1513 bce_tick(v) 1514 void *v; 1515 { 1516 struct bce_softc *sc = v; 1517 1518 /* Tick the MII. */ 1519 mii_tick(&sc->bce_mii); 1520 1521 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1522 } 1523
Indexes created Tue Sep 30 20:09:53 GMT 2025