if_bce.c revision 1.45
1 /* $NetBSD: if_bce.c,v 1.45 2017/04/19 06:52:11 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff (at) snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.45 2017/04/19 06:52:11 msaitoh Exp $"); 39 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 #include <sys/rndsource.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/miidevs.h> 67 #include <dev/mii/brgphyreg.h> 68 69 #include <dev/pci/if_bcereg.h> 70 71 /* transmit buffer max frags allowed */ 72 #define BCE_NTXFRAGS 16 73 74 /* ring descriptor */ 75 struct bce_dma_slot { 76 uint32_t ctrl; 77 uint32_t addr; 78 }; 79 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 80 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 81 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 82 #define CTRL_EOF 0x40000000 /* end of frame */ 83 #define CTRL_SOF 0x80000000 /* start of frame */ 84 85 /* Packet status is returned in a pre-packet header */ 86 struct rx_pph { 87 uint16_t len; 88 uint16_t flags; 89 uint16_t pad[12]; 90 }; 91 92 /* packet status flags bits */ 93 #define RXF_NO 0x8 /* odd number of nibbles */ 94 #define RXF_RXER 0x4 /* receive symbol error */ 95 #define RXF_CRC 0x2 /* crc error */ 96 #define RXF_OV 0x1 /* fifo overflow */ 97 98 /* number of descriptors used in a ring */ 99 #define BCE_NRXDESC 128 100 #define BCE_NTXDESC 128 101 102 /* 103 * Mbuf pointers. We need these to keep track of the virtual addresses 104 * of our mbuf chains since we can only convert from physical to virtual, 105 * not the other way around. 106 */ 107 struct bce_chain_data { 108 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 109 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 110 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 111 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 112 }; 113 114 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 115 116 struct bce_softc { 117 device_t bce_dev; 118 bus_space_tag_t bce_btag; 119 bus_space_handle_t bce_bhandle; 120 bus_dma_tag_t bce_dmatag; 121 struct ethercom ethercom; /* interface info */ 122 void *bce_intrhand; 123 struct pci_attach_args bce_pa; 124 struct mii_data bce_mii; 125 uint32_t bce_phy; /* eeprom indicated phy */ 126 struct ifmedia bce_ifmedia; /* media info *//* Check */ 127 uint8_t enaddr[ETHER_ADDR_LEN]; 128 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 129 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 130 struct bce_chain_data bce_cdata; /* mbufs */ 131 bus_dmamap_t bce_ring_map; 132 uint32_t bce_intmask; /* current intr mask */ 133 uint32_t bce_rxin; /* last rx descriptor seen */ 134 uint32_t bce_txin; /* last tx descriptor seen */ 135 int bce_txsfree; /* no. tx slots available */ 136 int bce_txsnext; /* next available tx slot */ 137 callout_t bce_timeout; 138 krndsource_t rnd_source; 139 }; 140 141 /* for ring descriptors */ 142 #define BCE_RXBUF_LEN (MCLBYTES - 4) 143 #define BCE_INIT_RXDESC(sc, x) \ 144 do { \ 145 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 146 \ 147 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 148 __bced->addr = \ 149 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 150 + 0x40000000); \ 151 if (x != (BCE_NRXDESC - 1)) \ 152 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 153 else \ 154 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 155 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 156 sizeof(struct bce_dma_slot) * x, \ 157 sizeof(struct bce_dma_slot), \ 158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 159 } while (/* CONSTCOND */ 0) 160 161 static int bce_probe(device_t, cfdata_t, void *); 162 static void bce_attach(device_t, device_t, void *); 163 static int bce_ioctl(struct ifnet *, u_long, void *); 164 static void bce_start(struct ifnet *); 165 static void bce_watchdog(struct ifnet *); 166 static int bce_intr(void *); 167 static void bce_rxintr(struct bce_softc *); 168 static void bce_txintr(struct bce_softc *); 169 static int bce_init(struct ifnet *); 170 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 171 static int bce_add_rxbuf(struct bce_softc *, int); 172 static void bce_rxdrain(struct bce_softc *); 173 static void bce_stop(struct ifnet *, int); 174 static void bce_reset(struct bce_softc *); 175 static bool bce_resume(device_t, const pmf_qual_t *); 176 static void bce_set_filter(struct ifnet *); 177 static int bce_mii_read(device_t, int, int); 178 static void bce_mii_write(device_t, int, int, int); 179 static void bce_statchg(struct ifnet *); 180 static void bce_tick(void *); 181 182 CFATTACH_DECL_NEW(bce, sizeof(struct bce_softc), 183 bce_probe, bce_attach, NULL, NULL); 184 185 static const struct bce_product { 186 pci_vendor_id_t bp_vendor; 187 pci_product_id_t bp_product; 188 const char *bp_name; 189 } bce_products[] = { 190 { 191 PCI_VENDOR_BROADCOM, 192 PCI_PRODUCT_BROADCOM_BCM4401, 193 "Broadcom BCM4401 10/100 Ethernet" 194 }, 195 { 196 PCI_VENDOR_BROADCOM, 197 PCI_PRODUCT_BROADCOM_BCM4401_B0, 198 "Broadcom BCM4401-B0 10/100 Ethernet" 199 }, 200 { 201 202 0, 203 0, 204 NULL 205 }, 206 }; 207 208 static const struct bce_product * 209 bce_lookup(const struct pci_attach_args * pa) 210 { 211 const struct bce_product *bp; 212 213 for (bp = bce_products; bp->bp_name != NULL; bp++) { 214 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 215 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 216 return (bp); 217 } 218 219 return (NULL); 220 } 221 222 /* 223 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 224 * against drivers product list, and return its name if a match is found. 225 */ 226 static int 227 bce_probe(device_t parent, cfdata_t match, void *aux) 228 { 229 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 230 231 if (bce_lookup(pa) != NULL) 232 return (1); 233 234 return (0); 235 } 236 237 static void 238 bce_attach(device_t parent, device_t self, void *aux) 239 { 240 struct bce_softc *sc = device_private(self); 241 struct pci_attach_args *pa = aux; 242 const struct bce_product *bp; 243 pci_chipset_tag_t pc = pa->pa_pc; 244 pci_intr_handle_t ih; 245 const char *intrstr = NULL; 246 uint32_t command; 247 pcireg_t memtype, pmode; 248 bus_addr_t memaddr; 249 bus_size_t memsize; 250 void *kva; 251 bus_dma_segment_t seg; 252 int error, i, pmreg, rseg; 253 struct ifnet *ifp; 254 char intrbuf[PCI_INTRSTR_LEN]; 255 256 sc->bce_dev = self; 257 258 bp = bce_lookup(pa); 259 KASSERT(bp != NULL); 260 261 sc->bce_pa = *pa; 262 263 /* BCM440x can only address 30 bits (1GB) */ 264 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 265 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 266 aprint_error_dev(self, 267 "WARNING: failed to restrict dma range," 268 " falling back to parent bus dma range\n"); 269 sc->bce_dmatag = pa->pa_dmat; 270 } 271 272 aprint_naive(": Ethernet controller\n"); 273 aprint_normal(": %s\n", bp->bp_name); 274 275 /* 276 * Map control/status registers. 277 */ 278 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 279 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 280 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 281 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 282 283 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 284 aprint_error_dev(self, "failed to enable memory mapping!\n"); 285 return; 286 } 287 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 288 switch (memtype) { 289 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 290 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 291 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 292 &sc->bce_bhandle, &memaddr, &memsize) == 0) 293 break; 294 default: 295 aprint_error_dev(self, "unable to find mem space\n"); 296 return; 297 } 298 299 /* Get it out of power save mode if needed. */ 300 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, NULL)) { 301 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) 302 & PCI_PMCSR_STATE_MASK; 303 if (pmode == PCI_PMCSR_STATE_D3) { 304 /* 305 * The card has lost all configuration data in 306 * this state, so punt. 307 */ 308 aprint_error_dev(self, 309 "unable to wake up from power state D3\n"); 310 return; 311 } 312 if (pmode != PCI_PMCSR_STATE_D0) { 313 aprint_normal_dev(self, 314 "waking up from power state D%d\n", pmode); 315 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 0); 316 } 317 } 318 if (pci_intr_map(pa, &ih)) { 319 aprint_error_dev(self, "couldn't map interrupt\n"); 320 return; 321 } 322 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 323 324 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 325 326 if (sc->bce_intrhand == NULL) { 327 aprint_error_dev(self, "couldn't establish interrupt\n"); 328 if (intrstr != NULL) 329 aprint_error(" at %s", intrstr); 330 aprint_error("\n"); 331 return; 332 } 333 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 334 335 /* reset the chip */ 336 bce_reset(sc); 337 338 /* 339 * Allocate DMA-safe memory for ring descriptors. 340 * The receive, and transmit rings can not share the same 341 * 4k space, however both are allocated at once here. 342 */ 343 /* 344 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 345 * due to the limition above. ?? 346 */ 347 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 348 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 349 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 350 aprint_error_dev(self, 351 "unable to alloc space for ring descriptors, error = %d\n", 352 error); 353 return; 354 } 355 /* map ring space to kernel */ 356 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 357 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 358 aprint_error_dev(self, 359 "unable to map DMA buffers, error = %d\n", error); 360 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 361 return; 362 } 363 /* create a dma map for the ring */ 364 if ((error = bus_dmamap_create(sc->bce_dmatag, 365 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 366 &sc->bce_ring_map))) { 367 aprint_error_dev(self, 368 "unable to create ring DMA map, error = %d\n", error); 369 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 370 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 371 return; 372 } 373 /* connect the ring space to the dma map */ 374 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 375 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 376 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 377 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 378 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 379 return; 380 } 381 /* save the ring space in softc */ 382 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 383 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 384 385 /* Create the transmit buffer DMA maps. */ 386 for (i = 0; i < BCE_NTXDESC; i++) { 387 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 388 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 389 aprint_error_dev(self, 390 "unable to create tx DMA map, error = %d\n", error); 391 } 392 sc->bce_cdata.bce_tx_chain[i] = NULL; 393 } 394 395 /* Create the receive buffer DMA maps. */ 396 for (i = 0; i < BCE_NRXDESC; i++) { 397 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 398 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 399 aprint_error_dev(self, 400 "unable to create rx DMA map, error = %d\n", error); 401 } 402 sc->bce_cdata.bce_rx_chain[i] = NULL; 403 } 404 405 /* Set up ifnet structure */ 406 ifp = &sc->ethercom.ec_if; 407 strcpy(ifp->if_xname, device_xname(self)); 408 ifp->if_softc = sc; 409 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 410 ifp->if_ioctl = bce_ioctl; 411 ifp->if_start = bce_start; 412 ifp->if_watchdog = bce_watchdog; 413 ifp->if_init = bce_init; 414 ifp->if_stop = bce_stop; 415 IFQ_SET_READY(&ifp->if_snd); 416 417 /* Initialize our media structures and probe the MII. */ 418 419 sc->bce_mii.mii_ifp = ifp; 420 sc->bce_mii.mii_readreg = bce_mii_read; 421 sc->bce_mii.mii_writereg = bce_mii_write; 422 sc->bce_mii.mii_statchg = bce_statchg; 423 424 sc->ethercom.ec_mii = &sc->bce_mii; 425 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 426 ether_mediastatus); 427 mii_attach(sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 428 MII_OFFSET_ANY, MIIF_FORCEANEG|MIIF_DOPAUSE); 429 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 430 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 431 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 432 } else 433 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 434 /* get the phy */ 435 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 436 BCE_MAGIC_PHY) & 0x1f; 437 /* 438 * Enable activity led. 439 * XXX This should be in a phy driver, but not currently. 440 */ 441 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 442 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 443 /* enable traffic meter led mode */ 444 bce_mii_write(sc->bce_dev, 1, 27, /* MAGIC */ 445 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 446 447 /* Attach the interface */ 448 if_attach(ifp); 449 if_deferred_start_init(ifp, NULL); 450 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 451 BCE_MAGIC_ENET0); 452 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 453 BCE_MAGIC_ENET1); 454 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 455 BCE_MAGIC_ENET2); 456 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 457 BCE_MAGIC_ENET3); 458 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 459 BCE_MAGIC_ENET4); 460 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 461 BCE_MAGIC_ENET5); 462 aprint_normal_dev(self, "Ethernet address %s\n", 463 ether_sprintf(sc->enaddr)); 464 ether_ifattach(ifp, sc->enaddr); 465 rnd_attach_source(&sc->rnd_source, device_xname(self), 466 RND_TYPE_NET, RND_FLAG_DEFAULT); 467 callout_init(&sc->bce_timeout, 0); 468 469 if (pmf_device_register(self, NULL, bce_resume)) 470 pmf_class_network_register(self, ifp); 471 else 472 aprint_error_dev(self, "couldn't establish power handler\n"); 473 } 474 475 /* handle media, and ethernet requests */ 476 static int 477 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 478 { 479 int s, error; 480 481 s = splnet(); 482 error = ether_ioctl(ifp, cmd, data); 483 if (error == ENETRESET) { 484 /* change multicast list */ 485 error = 0; 486 } 487 488 /* Try to get more packets going. */ 489 bce_start(ifp); 490 491 splx(s); 492 return error; 493 } 494 495 /* Start packet transmission on the interface. */ 496 static void 497 bce_start(struct ifnet *ifp) 498 { 499 struct bce_softc *sc = ifp->if_softc; 500 struct mbuf *m0; 501 bus_dmamap_t dmamap; 502 int txstart; 503 int txsfree; 504 int newpkts = 0; 505 int error; 506 507 /* 508 * do not start another if currently transmitting, and more 509 * descriptors(tx slots) are needed for next packet. 510 */ 511 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 512 return; 513 514 /* determine number of descriptors available */ 515 if (sc->bce_txsnext >= sc->bce_txin) 516 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 517 else 518 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 519 520 /* 521 * Loop through the send queue, setting up transmit descriptors 522 * until we drain the queue, or use up all available transmit 523 * descriptors. 524 */ 525 while (txsfree > 0) { 526 int seg; 527 528 /* Grab a packet off the queue. */ 529 IFQ_POLL(&ifp->if_snd, m0); 530 if (m0 == NULL) 531 break; 532 533 /* get the transmit slot dma map */ 534 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 535 536 /* 537 * Load the DMA map. If this fails, the packet either 538 * didn't fit in the alloted number of segments, or we 539 * were short on resources. If the packet will not fit, 540 * it will be dropped. If short on resources, it will 541 * be tried again later. 542 */ 543 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 544 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 545 if (error == EFBIG) { 546 aprint_error_dev(sc->bce_dev, 547 "Tx packet consumes too many DMA segments, " 548 "dropping...\n"); 549 IFQ_DEQUEUE(&ifp->if_snd, m0); 550 m_freem(m0); 551 ifp->if_oerrors++; 552 continue; 553 } else if (error) { 554 /* short on resources, come back later */ 555 aprint_error_dev(sc->bce_dev, 556 "unable to load Tx buffer, error = %d\n", 557 error); 558 break; 559 } 560 /* If not enough descriptors available, try again later */ 561 if (dmamap->dm_nsegs > txsfree) { 562 ifp->if_flags |= IFF_OACTIVE; 563 bus_dmamap_unload(sc->bce_dmatag, dmamap); 564 break; 565 } 566 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 567 568 /* So take it off the queue */ 569 IFQ_DEQUEUE(&ifp->if_snd, m0); 570 571 /* save the pointer so it can be freed later */ 572 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 573 574 /* Sync the data DMA map. */ 575 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 576 BUS_DMASYNC_PREWRITE); 577 578 /* Initialize the transmit descriptor(s). */ 579 txstart = sc->bce_txsnext; 580 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 581 uint32_t ctrl; 582 583 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 584 if (seg == 0) 585 ctrl |= CTRL_SOF; 586 if (seg == dmamap->dm_nsegs - 1) 587 ctrl |= CTRL_EOF; 588 if (sc->bce_txsnext == BCE_NTXDESC - 1) 589 ctrl |= CTRL_EOT; 590 ctrl |= CTRL_IOC; 591 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 592 sc->bce_tx_ring[sc->bce_txsnext].addr = 593 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 594 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 595 sc->bce_txsnext = 0; 596 else 597 sc->bce_txsnext++; 598 txsfree--; 599 } 600 /* sync descriptors being used */ 601 if ( sc->bce_txsnext > txstart ) { 602 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 603 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 604 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 606 } else { 607 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 608 PAGE_SIZE + sizeof(struct bce_dma_slot) * txstart, 609 sizeof(struct bce_dma_slot) * 610 (BCE_NTXDESC - txstart), 611 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 612 if ( sc->bce_txsnext != 0 ) { 613 bus_dmamap_sync(sc->bce_dmatag, 614 sc->bce_ring_map, PAGE_SIZE, 615 sc->bce_txsnext * 616 sizeof(struct bce_dma_slot), 617 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 618 } 619 } 620 621 /* Give the packet to the chip. */ 622 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 623 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 624 625 newpkts++; 626 627 /* Pass the packet to any BPF listeners. */ 628 bpf_mtap(ifp, m0); 629 } 630 if (txsfree == 0) { 631 /* No more slots left; notify upper layer. */ 632 ifp->if_flags |= IFF_OACTIVE; 633 } 634 if (newpkts) { 635 /* Set a watchdog timer in case the chip flakes out. */ 636 ifp->if_timer = 5; 637 } 638 } 639 640 /* Watchdog timer handler. */ 641 static void 642 bce_watchdog(struct ifnet *ifp) 643 { 644 struct bce_softc *sc = ifp->if_softc; 645 646 aprint_error_dev(sc->bce_dev, "device timeout\n"); 647 ifp->if_oerrors++; 648 649 (void) bce_init(ifp); 650 651 /* Try to get more packets going. */ 652 bce_start(ifp); 653 } 654 655 int 656 bce_intr(void *xsc) 657 { 658 struct bce_softc *sc; 659 struct ifnet *ifp; 660 uint32_t intstatus; 661 int wantinit; 662 int handled = 0; 663 664 sc = xsc; 665 ifp = &sc->ethercom.ec_if; 666 667 for (wantinit = 0; wantinit == 0;) { 668 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 669 BCE_INT_STS); 670 671 /* ignore if not ours, or unsolicited interrupts */ 672 intstatus &= sc->bce_intmask; 673 if (intstatus == 0) 674 break; 675 676 handled = 1; 677 678 /* Ack interrupt */ 679 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 680 intstatus); 681 682 /* Receive interrupts. */ 683 if (intstatus & I_RI) 684 bce_rxintr(sc); 685 /* Transmit interrupts. */ 686 if (intstatus & I_XI) 687 bce_txintr(sc); 688 /* Error interrupts */ 689 if (intstatus & ~(I_RI | I_XI)) { 690 const char *msg = NULL; 691 if (intstatus & I_XU) 692 msg = "transmit fifo underflow"; 693 if (intstatus & I_RO) { 694 msg = "receive fifo overflow"; 695 ifp->if_ierrors++; 696 } 697 if (intstatus & I_RU) 698 msg = "receive descriptor underflow"; 699 if (intstatus & I_DE) 700 msg = "descriptor protocol error"; 701 if (intstatus & I_PD) 702 msg = "data error"; 703 if (intstatus & I_PC) 704 msg = "descriptor error"; 705 if (intstatus & I_TO) 706 msg = "general purpose timeout"; 707 if (msg != NULL) 708 aprint_error_dev(sc->bce_dev, "%s\n", msg); 709 wantinit = 1; 710 } 711 } 712 713 if (handled) { 714 if (wantinit) 715 bce_init(ifp); 716 rnd_add_uint32(&sc->rnd_source, intstatus); 717 /* Try to get more packets going. */ 718 if_schedule_deferred_start(ifp); 719 } 720 return (handled); 721 } 722 723 /* Receive interrupt handler */ 724 void 725 bce_rxintr(struct bce_softc *sc) 726 { 727 struct ifnet *ifp = &sc->ethercom.ec_if; 728 struct rx_pph *pph; 729 struct mbuf *m; 730 int curr; 731 int len; 732 int i; 733 734 /* get pointer to active receive slot */ 735 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 736 & RS_CD_MASK; 737 curr = curr / sizeof(struct bce_dma_slot); 738 if (curr >= BCE_NRXDESC) 739 curr = BCE_NRXDESC - 1; 740 741 /* process packets up to but not current packet being worked on */ 742 for (i = sc->bce_rxin; i != curr; 743 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 744 /* complete any post dma memory ops on packet */ 745 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 746 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 747 BUS_DMASYNC_POSTREAD); 748 749 /* 750 * If the packet had an error, simply recycle the buffer, 751 * resetting the len, and flags. 752 */ 753 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 754 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 755 ifp->if_ierrors++; 756 pph->len = 0; 757 pph->flags = 0; 758 continue; 759 } 760 /* receive the packet */ 761 len = pph->len; 762 if (len == 0) 763 continue; /* no packet if empty */ 764 pph->len = 0; 765 pph->flags = 0; 766 /* bump past pre header to packet */ 767 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 768 769 /* 770 * The chip includes the CRC with every packet. Trim 771 * it off here. 772 */ 773 len -= ETHER_CRC_LEN; 774 775 /* 776 * If the packet is small enough to fit in a 777 * single header mbuf, allocate one and copy 778 * the data into it. This greatly reduces 779 * memory consumption when receiving lots 780 * of small packets. 781 * 782 * Otherwise, add a new buffer to the receive 783 * chain. If this fails, drop the packet and 784 * recycle the old buffer. 785 */ 786 if (len <= (MHLEN - 2)) { 787 MGETHDR(m, M_DONTWAIT, MT_DATA); 788 if (m == NULL) 789 goto dropit; 790 m->m_data += 2; 791 memcpy(mtod(m, void *), 792 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 793 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 794 } else { 795 m = sc->bce_cdata.bce_rx_chain[i]; 796 if (bce_add_rxbuf(sc, i) != 0) { 797 dropit: 798 ifp->if_ierrors++; 799 /* continue to use old buffer */ 800 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 801 bus_dmamap_sync(sc->bce_dmatag, 802 sc->bce_cdata.bce_rx_map[i], 0, 803 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 804 BUS_DMASYNC_PREREAD); 805 continue; 806 } 807 } 808 809 m_set_rcvif(m, ifp); 810 m->m_pkthdr.len = m->m_len = len; 811 812 /* Pass it on. */ 813 if_percpuq_enqueue(ifp->if_percpuq, m); 814 815 /* re-check current in case it changed */ 816 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 817 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 818 sizeof(struct bce_dma_slot); 819 if (curr >= BCE_NRXDESC) 820 curr = BCE_NRXDESC - 1; 821 } 822 sc->bce_rxin = curr; 823 } 824 825 /* Transmit interrupt handler */ 826 void 827 bce_txintr(struct bce_softc *sc) 828 { 829 struct ifnet *ifp = &sc->ethercom.ec_if; 830 int curr; 831 int i; 832 833 ifp->if_flags &= ~IFF_OACTIVE; 834 835 /* 836 * Go through the Tx list and free mbufs for those 837 * frames which have been transmitted. 838 */ 839 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 840 RS_CD_MASK; 841 curr = curr / sizeof(struct bce_dma_slot); 842 if (curr >= BCE_NTXDESC) 843 curr = BCE_NTXDESC - 1; 844 for (i = sc->bce_txin; i != curr; 845 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 846 /* do any post dma memory ops on transmit data */ 847 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 848 continue; 849 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 850 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 851 BUS_DMASYNC_POSTWRITE); 852 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 853 m_freem(sc->bce_cdata.bce_tx_chain[i]); 854 sc->bce_cdata.bce_tx_chain[i] = NULL; 855 ifp->if_opackets++; 856 } 857 sc->bce_txin = curr; 858 859 /* 860 * If there are no more pending transmissions, cancel the watchdog 861 * timer 862 */ 863 if (sc->bce_txsnext == sc->bce_txin) 864 ifp->if_timer = 0; 865 } 866 867 /* initialize the interface */ 868 static int 869 bce_init(struct ifnet *ifp) 870 { 871 struct bce_softc *sc = ifp->if_softc; 872 uint32_t reg_win; 873 int error; 874 int i; 875 876 /* Cancel any pending I/O. */ 877 bce_stop(ifp, 0); 878 879 /* enable pci inerrupts, bursts, and prefetch */ 880 881 /* remap the pci registers to the Sonics config registers */ 882 883 /* save the current map, so it can be restored */ 884 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 885 BCE_REG_WIN); 886 887 /* set register window to Sonics registers */ 888 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 889 BCE_SONICS_WIN); 890 891 /* enable SB to PCI interrupt */ 892 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 893 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 894 SBIV_ENET0); 895 896 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 897 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 898 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 899 SBTOPCI_PREF | SBTOPCI_BURST); 900 901 /* restore to ethernet register space */ 902 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 903 reg_win); 904 905 /* Reset the chip to a known state. */ 906 bce_reset(sc); 907 908 /* Initialize transmit descriptors */ 909 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 910 sc->bce_txsnext = 0; 911 sc->bce_txin = 0; 912 913 /* enable crc32 generation */ 914 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 915 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 916 BCE_EMC_CG); 917 918 /* setup DMA interrupt control */ 919 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 920 921 /* setup packet filter */ 922 bce_set_filter(ifp); 923 924 /* set max frame length, account for possible vlan tag */ 925 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 926 ETHER_MAX_LEN + 32); 927 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 928 ETHER_MAX_LEN + 32); 929 930 /* set tx watermark */ 931 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 932 933 /* enable transmit */ 934 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 936 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 937 938 /* 939 * Give the receive ring to the chip, and 940 * start the receive DMA engine. 941 */ 942 sc->bce_rxin = 0; 943 944 /* clear the rx descriptor ring */ 945 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 946 /* enable receive */ 947 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 948 30 << 1 | 1); /* MAGIC */ 949 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 950 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 951 952 /* Initalize receive descriptors */ 953 for (i = 0; i < BCE_NRXDESC; i++) { 954 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 955 if ((error = bce_add_rxbuf(sc, i)) != 0) { 956 aprint_error_dev(sc->bce_dev, 957 "unable to allocate or map rx(%d) " 958 "mbuf, error = %d\n", i, error); 959 bce_rxdrain(sc); 960 return (error); 961 } 962 } else 963 BCE_INIT_RXDESC(sc, i); 964 } 965 966 /* Enable interrupts */ 967 sc->bce_intmask = 968 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 969 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 970 sc->bce_intmask); 971 972 /* start the receive dma */ 973 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 974 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 975 976 /* set media */ 977 if ((error = ether_mediachange(ifp)) != 0) 978 return error; 979 980 /* turn on the ethernet mac */ 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 982 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 983 BCE_ENET_CTL) | EC_EE); 984 985 /* start timer */ 986 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 987 988 /* mark as running, and no outputs active */ 989 ifp->if_flags |= IFF_RUNNING; 990 ifp->if_flags &= ~IFF_OACTIVE; 991 992 return 0; 993 } 994 995 /* add a mac address to packet filter */ 996 void 997 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 998 { 999 int i; 1000 uint32_t rval; 1001 1002 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1003 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1004 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1005 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1006 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1007 idx << 16 | 8); /* MAGIC */ 1008 /* wait for write to complete */ 1009 for (i = 0; i < 100; i++) { 1010 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1011 BCE_FILT_CTL); 1012 if (!(rval & 0x80000000)) /* MAGIC */ 1013 break; 1014 delay(10); 1015 } 1016 if (i == 100) { 1017 aprint_error_dev(sc->bce_dev, 1018 "timed out writing pkt filter ctl\n"); 1019 } 1020 } 1021 1022 /* Add a receive buffer to the indiciated descriptor. */ 1023 static int 1024 bce_add_rxbuf(struct bce_softc *sc, int idx) 1025 { 1026 struct mbuf *m; 1027 int error; 1028 1029 MGETHDR(m, M_DONTWAIT, MT_DATA); 1030 if (m == NULL) 1031 return (ENOBUFS); 1032 1033 MCLGET(m, M_DONTWAIT); 1034 if ((m->m_flags & M_EXT) == 0) { 1035 m_freem(m); 1036 return (ENOBUFS); 1037 } 1038 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1039 bus_dmamap_unload(sc->bce_dmatag, 1040 sc->bce_cdata.bce_rx_map[idx]); 1041 1042 sc->bce_cdata.bce_rx_chain[idx] = m; 1043 1044 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1045 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1046 BUS_DMA_READ | BUS_DMA_NOWAIT); 1047 if (error) 1048 return (error); 1049 1050 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1051 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1052 1053 BCE_INIT_RXDESC(sc, idx); 1054 1055 return (0); 1056 1057 } 1058 1059 /* Drain the receive queue. */ 1060 static void 1061 bce_rxdrain(struct bce_softc *sc) 1062 { 1063 int i; 1064 1065 for (i = 0; i < BCE_NRXDESC; i++) { 1066 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1067 bus_dmamap_unload(sc->bce_dmatag, 1068 sc->bce_cdata.bce_rx_map[i]); 1069 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1070 sc->bce_cdata.bce_rx_chain[i] = NULL; 1071 } 1072 } 1073 } 1074 1075 /* Stop transmission on the interface */ 1076 static void 1077 bce_stop(struct ifnet *ifp, int disable) 1078 { 1079 struct bce_softc *sc = ifp->if_softc; 1080 int i; 1081 uint32_t val; 1082 1083 /* Stop the 1 second timer */ 1084 callout_stop(&sc->bce_timeout); 1085 1086 /* Down the MII. */ 1087 mii_down(&sc->bce_mii); 1088 1089 /* Disable interrupts. */ 1090 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1091 sc->bce_intmask = 0; 1092 delay(10); 1093 1094 /* Disable emac */ 1095 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1096 for (i = 0; i < 200; i++) { 1097 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1098 BCE_ENET_CTL); 1099 if (!(val & EC_ED)) 1100 break; 1101 delay(10); 1102 } 1103 1104 /* Stop the DMA */ 1105 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1106 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1107 delay(10); 1108 1109 /* Release any queued transmit buffers. */ 1110 for (i = 0; i < BCE_NTXDESC; i++) { 1111 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1112 bus_dmamap_unload(sc->bce_dmatag, 1113 sc->bce_cdata.bce_tx_map[i]); 1114 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1115 sc->bce_cdata.bce_tx_chain[i] = NULL; 1116 } 1117 } 1118 1119 /* Mark the interface down and cancel the watchdog timer. */ 1120 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1121 ifp->if_timer = 0; 1122 1123 /* drain receive queue */ 1124 if (disable) 1125 bce_rxdrain(sc); 1126 } 1127 1128 /* reset the chip */ 1129 static void 1130 bce_reset(struct bce_softc *sc) 1131 { 1132 uint32_t val; 1133 uint32_t sbval; 1134 int i; 1135 1136 /* if SB core is up */ 1137 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1138 BCE_SBTMSTATELOW); 1139 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1140 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1141 0); 1142 1143 /* disable emac */ 1144 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1145 EC_ED); 1146 for (i = 0; i < 200; i++) { 1147 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1148 BCE_ENET_CTL); 1149 if (!(val & EC_ED)) 1150 break; 1151 delay(10); 1152 } 1153 if (i == 200) { 1154 aprint_error_dev(sc->bce_dev, 1155 "timed out disabling ethernet mac\n"); 1156 } 1157 1158 /* reset the dma engines */ 1159 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1160 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1161 /* if error on receive, wait to go idle */ 1162 if (val & RS_ERROR) { 1163 for (i = 0; i < 100; i++) { 1164 val = bus_space_read_4(sc->bce_btag, 1165 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1166 if (val & RS_DMA_IDLE) 1167 break; 1168 delay(10); 1169 } 1170 if (i == 100) { 1171 aprint_error_dev(sc->bce_dev, 1172 "receive dma did not go idle after" 1173 " error\n"); 1174 } 1175 } 1176 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1177 BCE_DMA_RXSTATUS, 0); 1178 1179 /* reset ethernet mac */ 1180 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1181 EC_ES); 1182 for (i = 0; i < 200; i++) { 1183 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1184 BCE_ENET_CTL); 1185 if (!(val & EC_ES)) 1186 break; 1187 delay(10); 1188 } 1189 if (i == 200) { 1190 aprint_error_dev(sc->bce_dev, 1191 "timed out resetting ethernet mac\n"); 1192 } 1193 } else { 1194 uint32_t reg_win; 1195 1196 /* remap the pci registers to the Sonics config registers */ 1197 1198 /* save the current map, so it can be restored */ 1199 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1200 BCE_REG_WIN); 1201 /* set register window to Sonics registers */ 1202 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1203 BCE_REG_WIN, BCE_SONICS_WIN); 1204 1205 /* enable SB to PCI interrupt */ 1206 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1207 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1208 BCE_SBINTVEC) | 1209 SBIV_ENET0); 1210 1211 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1212 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1213 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1214 BCE_SPCI_TR2) | 1215 SBTOPCI_PREF | SBTOPCI_BURST); 1216 1217 /* restore to ethernet register space */ 1218 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1219 reg_win); 1220 } 1221 1222 /* disable SB core if not in reset */ 1223 if (!(sbval & SBTML_RESET)) { 1224 1225 /* set the reject bit */ 1226 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1227 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1228 for (i = 0; i < 200; i++) { 1229 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1230 BCE_SBTMSTATELOW); 1231 if (val & SBTML_REJ) 1232 break; 1233 delay(1); 1234 } 1235 if (i == 200) { 1236 aprint_error_dev(sc->bce_dev, 1237 "while resetting core, reject did not set\n"); 1238 } 1239 /* wait until busy is clear */ 1240 for (i = 0; i < 200; i++) { 1241 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1242 BCE_SBTMSTATEHI); 1243 if (!(val & 0x4)) 1244 break; 1245 delay(1); 1246 } 1247 if (i == 200) { 1248 aprint_error_dev(sc->bce_dev, 1249 "while resetting core, busy did not clear\n"); 1250 } 1251 /* set reset and reject while enabling the clocks */ 1252 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1253 BCE_SBTMSTATELOW, 1254 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1255 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1256 BCE_SBTMSTATELOW); 1257 delay(10); 1258 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1259 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1260 delay(1); 1261 } 1262 /* enable clock */ 1263 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1264 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1265 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1266 delay(1); 1267 1268 /* clear any error bits that may be on */ 1269 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1270 if (val & 1) 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1272 0); 1273 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1274 if (val & SBIM_MAGIC_ERRORBITS) 1275 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1276 val & ~SBIM_MAGIC_ERRORBITS); 1277 1278 /* clear reset and allow it to propagate throughout the core */ 1279 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1280 SBTML_FGC | SBTML_CLK); 1281 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1282 delay(1); 1283 1284 /* leave clock enabled */ 1285 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1286 SBTML_CLK); 1287 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1288 delay(1); 1289 1290 /* initialize MDC preamble, frequency */ 1291 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1292 1293 /* enable phy, differs for internal, and external */ 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1295 if (!(val & BCE_DC_IP)) { 1296 /* select external phy */ 1297 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1298 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1299 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1300 val & ~BCE_DC_ER); 1301 delay(100); 1302 } 1303 } 1304 1305 /* Set up the receive filter. */ 1306 void 1307 bce_set_filter(struct ifnet *ifp) 1308 { 1309 struct bce_softc *sc = ifp->if_softc; 1310 1311 if (ifp->if_flags & IFF_PROMISC) { 1312 ifp->if_flags |= IFF_ALLMULTI; 1313 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1314 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1315 | ERC_PE); 1316 } else { 1317 ifp->if_flags &= ~IFF_ALLMULTI; 1318 1319 /* turn off promiscuous */ 1320 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1321 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1322 BCE_RX_CTL) & ~ERC_PE); 1323 1324 /* enable/disable broadcast */ 1325 if (ifp->if_flags & IFF_BROADCAST) 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1327 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1328 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1329 else 1330 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1331 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1332 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1333 1334 /* disable the filter */ 1335 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1336 0); 1337 1338 /* add our own address */ 1339 bce_add_mac(sc, sc->enaddr, 0); 1340 1341 /* for now accept all multicast */ 1342 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1343 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1344 ERC_AM); 1345 ifp->if_flags |= IFF_ALLMULTI; 1346 1347 /* enable the filter */ 1348 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1349 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1350 BCE_FILT_CTL) | 1); 1351 } 1352 } 1353 1354 static bool 1355 bce_resume(device_t self, const pmf_qual_t *qual) 1356 { 1357 struct bce_softc *sc = device_private(self); 1358 1359 bce_reset(sc); 1360 1361 return true; 1362 } 1363 1364 /* Read a PHY register on the MII. */ 1365 int 1366 bce_mii_read(device_t self, int phy, int reg) 1367 { 1368 struct bce_softc *sc = device_private(self); 1369 int i; 1370 uint32_t val; 1371 1372 /* clear mii_int */ 1373 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1374 1375 /* Read the PHY register */ 1376 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1377 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1378 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1379 1380 for (i = 0; i < BCE_TIMEOUT; i++) { 1381 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1382 if (val & BCE_MIINTR) 1383 break; 1384 delay(10); 1385 } 1386 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1387 if (i == BCE_TIMEOUT) { 1388 aprint_error_dev(sc->bce_dev, 1389 "PHY read timed out reading phy %d, reg %d, val = " 1390 "0x%08x\n", phy, reg, val); 1391 return (0); 1392 } 1393 return (val & BCE_MICOMM_DATA); 1394 } 1395 1396 /* Write a PHY register on the MII */ 1397 void 1398 bce_mii_write(device_t self, int phy, int reg, int val) 1399 { 1400 struct bce_softc *sc = device_private(self); 1401 int i; 1402 uint32_t rval; 1403 1404 /* clear mii_int */ 1405 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1406 BCE_MIINTR); 1407 1408 /* Write the PHY register */ 1409 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1410 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1411 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1412 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1413 1414 /* wait for write to complete */ 1415 for (i = 0; i < BCE_TIMEOUT; i++) { 1416 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1417 BCE_MI_STS); 1418 if (rval & BCE_MIINTR) 1419 break; 1420 delay(10); 1421 } 1422 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1423 if (i == BCE_TIMEOUT) { 1424 aprint_error_dev(sc->bce_dev, 1425 "PHY timed out writing phy %d, reg %d, val = 0x%08x\n", phy, 1426 reg, val); 1427 } 1428 } 1429 1430 /* sync hardware duplex mode to software state */ 1431 void 1432 bce_statchg(struct ifnet *ifp) 1433 { 1434 struct bce_softc *sc = ifp->if_softc; 1435 uint32_t reg; 1436 1437 /* if needed, change register to match duplex mode */ 1438 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1439 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1440 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1441 reg | EXC_FD); 1442 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1443 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1444 reg & ~EXC_FD); 1445 1446 /* 1447 * Enable activity led. 1448 * XXX This should be in a phy driver, but not currently. 1449 */ 1450 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1451 bce_mii_read(sc->bce_dev, 1, 26) & 0x7fff); /* MAGIC */ 1452 /* enable traffic meter led mode */ 1453 bce_mii_write(sc->bce_dev, 1, 26, /* MAGIC */ 1454 bce_mii_read(sc->bce_dev, 1, 27) | (1 << 6)); /* MAGIC */ 1455 } 1456 1457 /* One second timer, checks link status */ 1458 static void 1459 bce_tick(void *v) 1460 { 1461 struct bce_softc *sc = v; 1462 1463 /* Tick the MII. */ 1464 mii_tick(&sc->bce_mii); 1465 1466 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1467 } 1468
Indexes created Tue Sep 30 11:09:46 GMT 2025